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-rw-r--r--src/r600_textured_videofuncs.c2
-rw-r--r--src/radeon_textured_video.c24
-rw-r--r--src/radeon_textured_videofuncs.c36
-rw-r--r--src/radeon_video.h2
4 files changed, 39 insertions, 25 deletions
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 5e6c561..ab3c498 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -224,7 +224,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
if (info->cs) {
accel_state->dst_mc_addr = 0;
accel_state->src_mc_addr[0] = 0;
- accel_state->src_bo[0] = pPriv->src_bo;
+ accel_state->src_bo[0] = pPriv->src_bo[pPriv->currentBuffer];
accel_state->src_bo[1] = NULL;
accel_state->dst_bo = radeon_get_pixmap_bo(pPixmap);
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index b708f52..04a2401 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -319,16 +319,19 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
if (info->ChipFamily >= CHIP_FAMILY_R600)
pPriv->video_offset = radeon_legacy_allocate_memory(pScrn,
&pPriv->video_memory,
- size * 2, 256);
+ size, 256);
else
pPriv->video_offset = radeon_legacy_allocate_memory(pScrn,
&pPriv->video_memory,
- size * 2, 64);
+ size, 64);
if (pPriv->video_offset == 0)
return BadAlloc;
- if (info->cs)
- pPriv->src_bo = pPriv->video_memory;
+ if (info->cs) {
+ pPriv->src_bo[0] = pPriv->video_memory;
+ radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size,
+ info->ChipFamily >= CHIP_FAMILY_R600 ? 256 : 64);
+ }
}
/* Bicubic filter loading */
@@ -366,14 +369,21 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->src_offset = pPriv->video_offset;
if (info->cs) {
+ struct radeon_bo *src_bo;
int ret;
- ret = radeon_bo_map(pPriv->src_bo, 1);
+
+ pPriv->currentBuffer ^= 1;
+
+ src_bo = pPriv->src_bo[pPriv->currentBuffer];
+
+ ret = radeon_bo_map(src_bo, 1);
if (ret)
return BadAlloc;
- pPriv->src_addr = pPriv->src_bo->ptr;
+ pPriv->src_addr = src_bo->ptr;
} else {
pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset);
+ RADEONWaitForIdleMMIO(pScrn);
}
pPriv->src_pitch = dstPitch;
@@ -460,7 +470,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
#if defined(XF86DRM_MODE)
if (info->cs)
- radeon_bo_unmap(pPriv->src_bo);
+ radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]);
#endif
#ifdef XF86DRI
if (info->directRenderingEnabled) {
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index d26e7c0..8b55efc 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -93,6 +93,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
struct radeon_exa_pixmap_priv *driver_priv;
+ struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer];
uint32_t txformat, txsize, txpitch, txoffset;
uint32_t dst_pitch, dst_format;
uint32_t colorpitch;
@@ -107,7 +108,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
int ret;
radeon_cs_space_reset_bos(info->cs);
- radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+ radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
@@ -237,7 +238,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
- OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+ OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, src_bo);
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
@@ -264,7 +265,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST);
OUT_ACCEL_REG(RADEON_PP_TXFORMAT_1, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1);
- OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo);
+ OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_1,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
@@ -288,7 +289,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST);
OUT_ACCEL_REG(RADEON_PP_TXFORMAT_2, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ1);
- OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo);
+ OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, src_bo);
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_2,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
@@ -321,7 +322,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
- OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+ OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, src_bo);
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
@@ -468,6 +469,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
struct radeon_exa_pixmap_priv *driver_priv;
+ struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer];
uint32_t txformat;
uint32_t txfilter, txsize, txpitch, txoffset;
uint32_t dst_pitch, dst_format;
@@ -493,7 +495,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
int ret;
radeon_cs_space_reset_bos(info->cs);
- radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+ radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
@@ -660,21 +662,21 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
- OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, src_bo);
OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter);
OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0);
OUT_ACCEL_REG(R200_PP_TXSIZE_1, txsize);
OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch);
- OUT_TEXTURE_REG(R200_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R200_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
OUT_ACCEL_REG(R200_PP_TXFILTER_2, txfilter);
OUT_ACCEL_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
OUT_ACCEL_REG(R200_PP_TXFORMAT_X_2, 0);
OUT_ACCEL_REG(R200_PP_TXSIZE_2, txsize);
OUT_ACCEL_REG(R200_PP_TXPITCH_2, txpitch);
- OUT_TEXTURE_REG(R200_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R200_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, src_bo);
/* similar to r300 code. Note the big problem is that hardware constants
* are 8 bits only, representing 0.0-1.0. We can get that up (using bias
@@ -816,7 +818,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
(pPriv->w - 1) |
((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
- OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, src_bo);
/* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */
OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
@@ -1017,6 +1019,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
struct radeon_exa_pixmap_priv *driver_priv;
+ struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer];
uint32_t txfilter, txformat0, txformat1, txoffset, txpitch;
uint32_t dst_pitch, dst_format;
uint32_t txenable, colorpitch, bicubic_offset;
@@ -1032,7 +1035,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
int ret;
radeon_cs_space_reset_bos(info->cs);
- radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+ radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
@@ -1161,7 +1164,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
else
OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
- OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, src_bo);
FINISH_ACCEL();
txenable = R300_TEX_0_ENABLE;
@@ -1183,13 +1186,13 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2);
OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
- OUT_TEXTURE_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset, src_bo);
OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT));
OUT_ACCEL_REG(R300_TX_FILTER1_2, 0);
OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3);
OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch);
- OUT_TEXTURE_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset, src_bo);
FINISH_ACCEL();
txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE;
}
@@ -2465,6 +2468,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
struct radeon_exa_pixmap_priv *driver_priv;
+ struct radeon_bo *src_bo = pPriv->src_bo[pPriv->currentBuffer];
uint32_t txfilter, txformat0, txformat1, txoffset, txpitch;
uint32_t dst_pitch, dst_format;
uint32_t txenable, colorpitch, bicubic_offset;
@@ -2480,7 +2484,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
int ret;
radeon_cs_space_reset_bos(info->cs);
- radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+ radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
if (pPriv->bicubic_enabled)
radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
@@ -2612,7 +2616,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
OUT_ACCEL_REG(R300_TX_FORMAT0_0, txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
- OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, pPriv->src_bo);
+ OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, src_bo);
FINISH_ACCEL();
txenable = R300_TEX_0_ENABLE;
diff --git a/src/radeon_video.h b/src/radeon_video.h
index 989942c..1b8f684 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -119,7 +119,7 @@ typedef struct {
int src_x, src_y;
int vsync;
- struct radeon_bo *src_bo;
+ struct radeon_bo *src_bo[2];
} RADEONPortPrivRec, *RADEONPortPrivPtr;
/* Reference color space transform data */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-21 19:05:43 +0000