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path: root/arch/mips/include/asm/mipsregs.h
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2015-04-08MIPS: math-emu: Define IEEE 754-2008 feature control bitsMaciej W. Rozycki1-2/+7
2015-04-08MIPS: math-emu: Implement the FCCR, FEXR and FENR registersMaciej W. Rozycki1-12/+57
2015-04-08MIPS: mipsregs.h: Reindent CP0 Cause macrosMaciej W. Rozycki1-16/+16
2015-04-08MIPS: mipsregs.h: Move TX39 macros out of the wayMaciej W. Rozycki1-33/+33
2015-04-08MIPS: mipsregs.h: Reorder CP1 macro definitionsMaciej W. Rozycki1-72/+75
2015-04-08MIPS: mipsregs.h: Remove broken commentsMaciej W. Rozycki1-6/+0
2015-03-31MIPS: Add architectural FDC IRQ fieldsJames Hogan1-0/+4
2015-03-31MIPS: Add arch CDMM definitions and probingJames Hogan1-0/+11
2015-02-21Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+4
2015-02-20MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill1-0/+1
2015-02-17MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras1-0/+2
2015-02-17MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras1-0/+1
2015-01-30MIPS: mipsregs.h: Add write_32bit_cp1_register()James Hogan1-0/+15
2014-12-11Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+43
2014-11-24MIPS: Add CP0 macros for extended EntryLo registersSteven J. Hill1-0/+40
2014-11-24MIPS: define bits introduced for hybrid FPRsPaul Burton1-0/+3
2014-11-24MIPS: cpu-probe: Set the FTLB probability bit on supported coresMarkos Chandras1-0/+2
2014-11-07MIPS: Fix build with binutils 2.24.51+Manuel Lauss1-1/+10
2014-08-02MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFTDan Carpenter1-1/+0
2014-08-02MIPS: define MAAR register accessors & bitsPaul Burton1-0/+12
2014-08-02MIPS: kernel: cpu-probe: Detect unique RI/XI exceptionsLeonid Yegoshin1-0/+1
2014-08-02MIPS: asm: Add register definitions for Hardware Table WalkerMarkos Chandras1-0/+44
2014-05-30MIPS: Add function get_ebase_cpunumDavid Daney1-0/+9
2014-05-24MIPS: MT: Remove SMTC supportRalf Baechle1-132/+1
2014-05-23MIPS: Disable MIPS16/microMIPS crap for platforms not supporting these ASEs.Ralf Baechle1-1/+8
2014-03-26MIPS: Add MSA register definitions & accessPaul Burton1-0/+1
2014-03-06MIPS: Add CP0 CMGCRBase definitions & accessorPaul Burton1-0/+6
2014-03-06MIPS: Define Config1 cache field shifts & sizesPaul Burton1-0/+12
2014-03-06MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras1-0/+3
2014-01-23MIPS: include linux/types.hQais Yousef1-0/+1
2014-01-22MIPS: Add support for FTLBsLeonid Yegoshin1-0/+2
2014-01-22MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin1-0/+13
2014-01-22MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill1-0/+29
2014-01-22MIPS: Add missing bits for Config registersLeonid Yegoshin1-2/+38
2013-09-19MIPS: Add MIPS R5 config5 register.Ralf Baechle1-0/+7
2013-07-01MIPS: microMIPS: Fix improper definition of ISA exception bit.Steven J. Hill1-1/+1
2013-05-09MIPS: microMIPS: Add support for exception handling.Steven J. Hill1-0/+1
2013-05-01MIPS: microMIPS: Add instruction utility macros.Steven J. Hill1-0/+18
2013-03-19MIPS: Fix code generation for non-DSP capable CPUsFlorian Fainelli1-19/+190
2013-02-21Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...Ralf Baechle1-186/+125
2013-02-19MIPS: Probe for and report hardware virtualization support.David Daney1-0/+1
2013-02-17MIPS: dsp: Simplify the DSP macros.Steven J. Hill1-201/+30
2013-02-17MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill1-0/+89
2013-02-17MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill1-17/+36
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill1-0/+1
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-199/+199
2013-02-01MIPS: Whitespace cleanups and reformatting.Steven J. Hill1-11/+15
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-8/+0
2012-12-12MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORTDavid Daney1-1/+1
2012-10-11MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill1-0/+1