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2020-12-23drm/amdgpu: take runtime pm reference when we attach a bufferdrm-nextAlex Deucher1-2/+14
And drop it when we detach. If the shared buffer is in vram, we need to make sure we don't put the device into runtime suspend. Acked-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23ALSA: hda/hdmi - enable runtime pm for CI AMD display audioAlex Deucher1-3/+6
We are able to power down the GPU and audio via the GPU driver so flag these asics as supporting runtime pm. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: Enable GPU reset for vangoghAlex Deucher1-0/+1
Enable GPU reset when we encounter a hang. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: fix mode2 reset sequence for vangoghAlex Deucher1-1/+33
We need to save and restore PCI config space. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu/nv: add mode2 reset handlingAlex Deucher1-2/+12
Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add mode2 reset support for vangoghAlex Deucher1-0/+6
GPU reset is handled via SMU similar to previous APUs. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add another raven1 gfxoff quirkAlex Deucher1-0/+2
HP Elite Disk 705 G4 Micro seems to have issues with gfxoff. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207899 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/radeon: fix check order in radeon_bo_moveChristian König1-30/+24
Reorder the code to fix checking if blitting is available. Signed-off-by: Christian König <christian.koenig@amd.com> Fixes: 28a68f828266 ("drm/radeon/ttm: use multihop") Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/403847/ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: fix check order in amdgpu_bo_moveChristian König1-30/+23
Reorder the code to fix checking if blitting is available. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/401019/ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23usb: typec: ucsi: check cci busy during PPM resetLiang Liang (Leo)1-1/+1
[Why] Following the spec of UCSI, EC may return CCI_BUSY for PPM reset cmd. [How] Check CCI_BUSY bit. Jira ID: SCSWATH-10 Signed-off-by: Liang Liang (Leo) <liang.liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: drop psp ih programming for sriov guest on naviHawking Zhang1-16/+2
the psp access ih path is not needed in navi Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jane Jian <Jane.Jian@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/display: Use common error handling code in dc_create()Markus Elfring1-9/+6
Adjust a jump target so that a bit of exception handling can be better reused at the end of this function. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/display: Return directly after a failed kzalloc() in dc_create()Markus Elfring1-4/+2
* Return directly after a call of the function “kzalloc” failed at the beginning. * Delete a label which became unnecessary with this refactoring. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdkfd: check both client id and src id in interrupt handlersAlex Deucher1-11/+35
We can have the same src ids for different client ids so make sure to check both the client id and the source id when handling interrupts. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: fix handling of irq domains on soc15 and newer GPUsAlex Deucher1-1/+2
We need to take into account the client id otherwise we'll end up sending generic events for any src id that is registered. We only support irq domains on pre-soc15 parts so client is always legacy. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: de-initialize software ih ringHawking Zhang3-0/+3
tear down software ih ring and its state. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: set ih soft ring enabled flag for vega and naviHawking Zhang2-0/+6
software ih ring is enabled in vega10 and navi ih block by default. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: enable software ih ring for vega20 ih blockHawking Zhang1-0/+7
software ih ring will be used as a workaround in case hardware ih ring 1 and ring 2 don't work Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/pm: support overdrive vddgfx offset setting(V2)Evan Quan4-2/+70
This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. For these ASICs, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset". V2: limit the smu_version check for Sienna Cichlid only Here are some sample usages about this new OD setting: 1. Check current vddgfx offset setting by cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 0mV ... ... 2. Set new vddgfx offset by echo "vo 10" > /sys/class/drm/card0/device/pp_od_clk_voltage cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 10mV ... ... 3. Commit the new setting by echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/pm: enable Sienna Cichlid overdrive supportEvan Quan2-1/+243
Enable Sienna Cichlid gfxclk/uclk overdrive support. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/pm: populate Sienna Cichlid default overdrive table settingsEvan Quan1-0/+38
Populate the bootup overdrive table settings. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/pm: Add interface for request WGPsJinzhou Su3-3/+41
When user specifies a reduced WGP(CU) config via disalbe_cu module parameter, this does not disable the clocks which uses additional power. This interface send active WGP number to SMU and SMU will cooperate with RLC to power off relative WGPs. v2: Add request active WGPs in Vangogh smu post init. Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amd/pm: add pptable_funcs documentation (v3)Ryan Taylor1-0/+526
Documents the hooks in struct pptable_funcs. v2: Improved documentation accuracy. v3: Improved set_default_od_settings() definition. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: don't create ih ring 1 and ring 2 for APUHawking Zhang1-11/+12
APUs don't support ih ring 1 and ring 2. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: drop ih reroute function from psp v11Hawking Zhang1-36/+0
For all the ASICs that integrate psp v11, vega20 doesn't support ih reroute. arcturus and later will allow kernel driver to program ih_cfg_index/data through mmio directly. navi1x and onwards will only support grb_ih_set command in sriov configuration. psp_v11_0_reroute_ih is not needed any more. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: drop IH_CHICKEN programming from vega10 ih blockHawking Zhang1-3/+1
except for RENOIR, it is not correct to have IH_CHICKEN programming in vega10 ih block. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocksHawking Zhang2-6/+0
IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only valid when IH_RB_CNTL.MC_SPACE is programed to 0x3, frame buffer physical address. For both bus address and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE field Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: retire the vega20 code path from navi10 ih blockHawking Zhang1-38/+2
already switched to vega20 ih block for vega20 and arcturus. no need to add vega20 support in navi10 ih block Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to vega20 ih block for vega20/arcturusHawking Zhang1-4/+5
replace navi10 ih block with vega20 ih block for vega20 and arcturus Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: reroute vmc/utcl2 interrupts to ih ring 1 for arcturusHawking Zhang1-0/+34
in case page faults overwhlem the interrupt handlers and the driver lost the valuable interrupt information Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: create vega20 ih blocksHawking Zhang3-0/+692
vega20 ih blocks will be used for vega20/arcturus Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add osssys v4_2 ip headers (v2)Hawking Zhang2-0/+1645
v1: add osssys v4_2 register offset and shift masks header files. vega20 and arcturus will refer to these ip headers. (Hawking) v2: clean up osssys v4_2 registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2020-12-23drm/amdgpu: switch to common decode iv helperHawking Zhang2-92/+2
The iv format is the same for all the soc15 adpater and onwards and can share a common function to decode iv. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add a helper function to decode ivHawking Zhang2-1/+46
since from soc15, all the chips share the same iv format. create a common helper to decode iv Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for navi10Hawking Zhang1-38/+14
all the ih rb control register offsets are cached at the beginning of navi10 ih_sw_init. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to ih_enable_ring for navi10Hawking Zhang1-90/+12
use navi10_ih_enable_ring to enable all the available ring buffers for navi1x and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for navi10Hawking Zhang1-133/+33
replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to ih_init_register_offset for navi10Hawking Zhang1-0/+3
Initialize ih control registers offset through helper function navi10_ih_init_register_offset. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for navi10Hawking Zhang1-0/+45
navi10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for navi1x and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add helper to enable an ih ring for navi10Hawking Zhang1-0/+52
navi10_ih_enable_ring will be used to enable an ih ring for navi1x and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add helper to init ih ring regs for navi10Hawking Zhang1-0/+47
navi10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: correct ih cg programming for vega10 ih blockHawking Zhang1-6/+2
vega10/12 and RAVEN don't support soft override ih_buffer_mem_clk. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for vega10Hawking Zhang1-40/+14
all the ih rb control register offsets are cached at the beginning of ih_sw_init. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to ih_enable_ring for vega10Hawking Zhang1-87/+8
use vega10_ih_enable_ring to enable all the available ring buffers for vega10/12, RAVEN series and RENOIR APUs Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for vega10Hawking Zhang1-134/+34
replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: switch to ih_init_register_offset for vega10Hawking Zhang1-0/+3
Initialize ih control registers offset through helper function vega10_ih_init_register_offset. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for vega10Hawking Zhang1-0/+45
vega10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for vega10/12, RAVEN series and RENOIR APUs Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add helper to enable an ih ring for vega10Hawking Zhang1-0/+52
vega10_ih_enable_ring will be used to enable an ih ring for vega10/12, RAVEN series and RENOIR. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add helper to init ih ring regs for vega10Hawking Zhang1-0/+47
vega10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: add amdgpu_ih_regs structureHawking Zhang1-0/+13
amdgpu_ih_regs holds all the registers for an ih ring Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 18:11:34 +0000