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authorHarry Wentland <harry.wentland@amd.com>2015-07-31 21:21:08 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-09-21 17:45:15 -0400
commit7be25cce3466809be0b38e62ed6105281cfd7445 (patch)
treef32533c7af1dea2a10c6f92135d485f4c273ef4a /arch/microblaze
parentc3bee645b6c3858d755618b8ee709bf059a6331c (diff)
amd/dal: Display Capability Service
Reads, parses, caches an enumerates display (sink) capabilities. Uses I2cAux component to read capabilities from the receiver. While parsing the EDID, DCS will call Timing Service to get timing parameters for DMT and CVT EDID timings. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Display Adapter | | Capability Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
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