diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2020-09-18 11:37:43 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2020-09-23 10:57:51 +0530 |
| commit | b7132285c65b52afd73139a8386184ff81c3fcb7 (patch) | |
| tree | 50423d48e60c1e9b1e9928f84145d998458dfb09 /Documentation | |
| parent | 4feac940ec142f70dd8600c5b73bef1cab5fde10 (diff) | |
dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phy
When WIZ wraps a Cadence Torrent PHY (instead of Cadence Sierra PHY)
there is a difference in the refclk-dig node: Torrent only has two
clocks instead of Sierra's four clocks. Add minItems: 2 to solve this.
Additionally, in our use case we only need to use assigned-clock for a
single clock, but the current binding requires either no assigned-clocks
or two. Fix this by adding minItems: 1 to all the assigned-clock
properties.
There was also an extra trailing whitespace, which this patch removes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Link: https://lore.kernel.org/r/20200918083743.213874-2-tomi.valkeinen@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 5ffc95c62909..c33e9bc79521 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -45,9 +45,15 @@ properties: ranges: true assigned-clocks: + minItems: 1 maxItems: 2 assigned-clock-parents: + minItems: 1 + maxItems: 2 + + assigned-clock-rates: + minItems: 1 maxItems: 2 typec-dir-gpios: @@ -119,9 +125,10 @@ patternProperties: logic. properties: clocks: + minItems: 2 maxItems: 4 - description: Phandle to four clock nodes representing the inputs to - refclk_dig + description: Phandle to two (Torrent) or four (Sierra) clock nodes representing + the inputs to refclk_dig "#clock-cells": const: 0 @@ -203,7 +210,7 @@ examples: }; refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; |