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authorAlex Deucher <alexander.deucher@amd.com>2020-11-25 11:15:52 -0500
committerAlex Deucher <alexander.deucher@amd.com>2020-12-23 15:09:47 -0500
commitc05d36d26dbdb1af39f4469c50d755bab9ef7ffa (patch)
treef7a961de52236add5e0ef5e6383e8983fde4719d
parentba8833571849da5ff82295ca134a36575f7232d5 (diff)
drm/amdgpu: fix mode2 reset sequence for vangogh
We need to save and restore PCI config space. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c34
1 files changed, 33 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index ecd1a40c37a5..61fd196a6c66 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -336,6 +336,38 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
return ret;
}
+static int nv_asic_mode2_reset(struct amdgpu_device *adev)
+{
+ u32 i;
+ int ret = 0;
+
+ amdgpu_atombios_scratch_regs_engine_hung(adev, true);
+
+ /* disable BM */
+ pci_clear_master(adev->pdev);
+
+ amdgpu_device_cache_pci_state(adev->pdev);
+
+ ret = amdgpu_dpm_mode2_reset(adev);
+ if (ret)
+ dev_err(adev->dev, "GPU mode2 reset failed\n");
+
+ amdgpu_device_load_pci_state(adev->pdev);
+
+ /* wait for asic to come out of reset */
+ for (i = 0; i < adev->usec_timeout; i++) {
+ u32 memsize = adev->nbio.funcs->get_memsize(adev);
+
+ if (memsize != 0xffffffff)
+ break;
+ udelay(1);
+ }
+
+ amdgpu_atombios_scratch_regs_engine_hung(adev, false);
+
+ return ret;
+}
+
static bool nv_asic_supports_baco(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
@@ -393,7 +425,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
break;
case AMD_RESET_METHOD_MODE2:
dev_info(adev->dev, "MODE2 reset\n");
- ret = amdgpu_dpm_mode2_reset(adev);
+ ret = nv_asic_mode2_reset(adev);
break;
default:
dev_info(adev->dev, "MODE1 reset\n");