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authorHawking Zhang <Hawking.Zhang@amd.com>2020-12-22 18:16:11 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-12-23 15:07:50 -0500
commit4f1431db92d801ae055ae5babe50bcbe1ce2feee (patch)
tree0d141bf2a7bec34cd32e6955e2b16fb1b26c3a44
parent554f80bd762914f9cddd10c952c240158704464f (diff)
drm/amdgpu: drop psp ih programming for sriov guest on navi
the psp access ih path is not needed in navi Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jane Jian <Jane.Jian@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/navi10_ih.c18
1 files changed, 2 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 060357625504..f4e4040bbd25 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,14 +151,7 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
/* enable_intr field is only valid in ring0 */
if (ih == &adev->irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
- if (amdgpu_sriov_vf(adev)) {
- if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
- dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
- return -ETIMEDOUT;
- }
- } else {
- WREG32(ih_regs->ih_rb_cntl, tmp);
- }
+ WREG32(ih_regs->ih_rb_cntl, tmp);
if (enable) {
ih->enabled = true;
@@ -268,14 +261,7 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
}
- if (amdgpu_sriov_vf(adev)) {
- if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
- dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
- return -ETIMEDOUT;
- }
- } else {
- WREG32(ih_regs->ih_rb_cntl, tmp);
- }
+ WREG32(ih_regs->ih_rb_cntl, tmp);
if (ih == &adev->irq.ih) {
/* set the ih ring 0 writeback address whether it's enabled or not */