diff options
| author | Mohan Kumar <mkumard@nvidia.com> | 2020-08-05 15:22:20 +0530 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2020-08-05 12:27:47 +0200 |
| commit | 4106820b90ab0f963571d14bdbf9a2587ca80532 (patch) | |
| tree | 03bd439344ce911a5d0289a5f6c273938a8e5a92 | |
| parent | 6c17e9dd5cdd352276180f47c0a8b24a1d4661af (diff) | |
ALSA: hda: Add dma stop delay variable
A variable dma_stop_delay is added as a new member in hdac_bus
structure to avoid memory decode error incase DMA RUN bit is not
disabled in the given timeout from snd_hdac_stream_sync function and
followed by stream reset which results in memory decode error between
reset set and clear operation.
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Link: https://lore.kernel.org/r/20200805095221.5476-3-mkumard@nvidia.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
| -rw-r--r-- | include/sound/hdaudio.h | 3 | ||||
| -rw-r--r-- | sound/hda/hdac_stream.c | 7 |
2 files changed, 10 insertions, 0 deletions
diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index c1f78d9a6e47..6eed61e6cf8a 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -347,6 +347,9 @@ struct hdac_bus { int bdl_pos_adj; /* BDL position adjustment */ + /* delay time in us for dma stop */ + unsigned int dma_stop_delay; + /* locks */ spinlock_t reg_lock; struct mutex cmd_mutex; diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index a38a2af1654f..abe7a1b16fe1 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -150,9 +150,12 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) { unsigned char val; int timeout; + int dma_run_state; snd_hdac_stream_clear(azx_dev); + dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; + snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); udelay(3); timeout = 300; @@ -162,6 +165,10 @@ void snd_hdac_stream_reset(struct hdac_stream *azx_dev) if (val) break; } while (--timeout); + + if (azx_dev->bus->dma_stop_delay && dma_run_state) + udelay(azx_dev->bus->dma_stop_delay); + val &= ~SD_CTL_STREAM_RESET; snd_hdac_stream_writeb(azx_dev, SD_CTL, val); udelay(3); |