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authorArnd Bergmann <arnd@arndb.de>2017-06-23 16:33:43 +0200
committerArnd Bergmann <arnd@arndb.de>2017-06-23 16:37:22 +0200
commit2b29ca22ed8a79ef1942b6546ccab5953678028d (patch)
tree99c0aa11cea115c172cc66b57d9c2eab0d740586
parent9b3088135aba74c177529096a6925f3c0af077c2 (diff)
Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"
As I found by chance while merging another patch, the usage of a dma-mask in this DT node is wrong for multiple reasons: - dma-masks are a Linux specific concept, not a general hardware feature - In DT, we use the "dma-ranges" property to describe how DMA addresses related between devices. - The 40-bit mask appears to be completely unnecessary here, as the SoC cannot address that much memory anyway, so simply asking for a 64-bit mask (as supported by the device) should succeed anyway. The patch to remove the parsing of the property is getting merged through the crypto tree. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi1
2 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index f611e843094c..726528ce54e9 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -270,7 +270,6 @@
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_clk 1 26>;
- dma-mask = <0xff 0xffffffff>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 84d3bd80eb51..95f8e5f607f6 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -261,7 +261,6 @@
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_clk 1 26>;
- dma-mask = <0xff 0xffffffff>;
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC