diff options
| author | Colin Ian King <colin.king@canonical.com> | 2019-06-26 14:24:27 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-27 11:22:57 -0500 |
| commit | 440e80ce02cde7b810e4eb555768c2d77e7a27c8 (patch) | |
| tree | ec6dd60e0141942bae6b0b570c02af917efcc123 | |
| parent | 4130ff8027dd679a6f2e45c26fb95860e6d235a3 (diff) | |
drm/amd/display: fix a couple of spelling mistakesdrm-next-5.3-2019-06-27
There are a couple of spelling mistakes in dm_error messages and
a comment. Fix these.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index be49fc7f4abe..ffd0014ec3b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -126,7 +126,7 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. - * The value below is the absolute maximum value. The actual througput may be lower, but it'll always + * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always * be sufficient to process the input pixel rate fed into a single DSC engine. */ dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 77e7a0f8a527..ef5f84a144c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -47,7 +47,7 @@ static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_bl *buff_block_size = 64 * 1024; break; default: { - dm_error("%s: DPCD DSC buffer size not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__); return false; } } @@ -63,7 +63,7 @@ static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *lin else if (dpcd_line_buff_bit_depth == 8) *line_buff_bit_depth = 8; else { - dm_error("%s: DPCD DSC buffer depth not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__); return false; } @@ -123,7 +123,7 @@ static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput) *throughput = 1000; break; default: { - dm_error("%s: DPCD DSC througput mode not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__); return false; } } @@ -152,7 +152,7 @@ static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bp *bpp_increment_div = 1; break; default: { - dm_error("%s: DPCD DSC bits-per-pixel increment not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); return false; } } |