diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-03-01 15:23:53 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-03-03 13:53:58 -0800 |
| commit | b88f74d63dca9db0f1b1cb9ce4d85f706c7a7fab (patch) | |
| tree | 5dfa2da3f13fdc684f86138bcfa120bb3449bf97 | |
| parent | 83e7d111afd8d340ce8fe13ea139271400eb362e (diff) | |
i965: Fix Crystal Well PCI IDs.
The second digit was off by one, which meant we accidentally treated
GTn as GT(n-1). This also meant no support for GT1 at all.
NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | include/pci_ids/i965_pci_ids.h | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 18 |
2 files changed, 18 insertions, 18 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 09dca5b0ed..1e388f8cad 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -53,12 +53,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) -CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) -CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) -CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) -CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) -CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) -CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) -CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) -CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) -CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) +CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) +CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1) +CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2) +CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) +CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) +CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 9c00ba81c9..885f6c2d32 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -114,15 +114,15 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ |