diff options
| author | Rob Clark <robdclark@gmail.com> | 2013-04-05 12:54:37 -0400 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2013-04-05 14:33:16 -0400 |
| commit | aac7f06ad843eaa696363e8e9c7781ca30cb4914 (patch) | |
| tree | 4f9fa6b3ccbb17ea208822cb553c6080488607ee | |
| parent | 1fefc65d20c126e834b0b42a560ffdd8a3a1197e (diff) | |
freedreno: use autogenerated register defs
Switch to use the envytools generated headers for register/bitfield
definitions. This is the first step in preparing to add a3xx support,
since it avoids having conflicting names for a3xx and a2xx registers.
And since I'm using envytools for a3xx it is simpler to just use it for
everything.
This shouldn't cause any functional change, it is really just a lot of
renaming.
Signed-off-by: Rob Clark <robdclark@gmail.com>
23 files changed, 2116 insertions, 1617 deletions
diff --git a/src/gallium/drivers/freedreno/a2xx.xml.h b/src/gallium/drivers/freedreno/a2xx.xml.h new file mode 100644 index 0000000000..da13cfdbba --- /dev/null +++ b/src/gallium/drivers/freedreno/a2xx.xml.h @@ -0,0 +1,1473 @@ +#ifndef A2XX_XML +#define A2XX_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/freedreno/envytools/rnndb/a2xx.xml ( 30372 bytes, from 2013-04-05 17:32:29) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) +- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 2972 bytes, from 2013-04-05 17:32:38) +- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 7736 bytes, from 2013-04-04 20:24:12) + +Copyright (C) 2013 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +enum a2xx_rb_dither_type { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +}; + +enum a2xx_colorformatx { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, + COLORX_INVALID = 15, +}; + +enum a2xx_sq_surfaceformat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_10_11_11 = 16, + FMT_11_11_10 = 17, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_24_8 = 22, + FMT_24_8_FLOAT = 23, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_32_AS_8 = 39, + FMT_32_AS_8_8 = 40, + FMT_16_MPEG = 41, + FMT_16_16_MPEG = 42, + FMT_8_INTERLACED = 43, + FMT_32_AS_8_INTERLACED = 44, + FMT_32_AS_8_8_INTERLACED = 45, + FMT_16_INTERLACED = 46, + FMT_16_MPEG_INTERLACED = 47, + FMT_16_16_MPEG_INTERLACED = 48, + FMT_DXN = 49, + FMT_8_8_8_8_AS_16_16_16_16 = 50, + FMT_DXT1_AS_16_16_16_16 = 51, + FMT_DXT2_3_AS_16_16_16_16 = 52, + FMT_DXT4_5_AS_16_16_16_16 = 53, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_11_11_AS_16_16_16_16 = 55, + FMT_11_11_10_AS_16_16_16_16 = 56, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, + FMT_DXT3A_AS_1_1_1_1 = 61, + FMT_INVALID = 62, +}; + +enum a2xx_rb_depth_format { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1, + DEPTHX_INVALID = 2, +}; + +enum a2xx_sq_ps_vtx_mode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7, +}; + +enum a2xx_sq_sample_cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, +}; + +enum a2xx_dx_clip_space { + DXCLIP_OPENGL = 0, + DXCLIP_DIRECTX = 1, +}; + +enum a2xx_pa_su_sc_polymode { + POLY_DISABLED = 0, + POLY_DUALMODE = 1, +}; + +enum a2xx_rb_edram_mode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +}; + +enum a2xx_pa_sc_pattern_bit_order { + LITTLE = 0, + BIG = 1, +}; + +enum a2xx_pa_sc_auto_reset_cntl { + NEVER = 0, + EACH_PRIMITIVE = 1, + EACH_PACKET = 2, +}; + +enum a2xx_pa_pixcenter { + PIXCENTER_D3D = 0, + PIXCENTER_OGL = 1, +}; + +enum a2xx_pa_roundmode { + TRUNCATE = 0, + ROUND = 1, + ROUNDTOEVEN = 2, + ROUNDTOODD = 3, +}; + +enum a2xx_pa_quantmode { + ONE_SIXTEENTH = 0, + ONE_EIGTH = 1, + ONE_QUARTER = 2, + ONE_HALF = 3, + ONE = 4, +}; + +enum a2xx_rb_copy_sample_select { + SAMPLE_0 = 0, + SAMPLE_1 = 1, + SAMPLE_2 = 2, + SAMPLE_3 = 3, + SAMPLE_01 = 4, + SAMPLE_23 = 5, + SAMPLE_0123 = 6, +}; + +enum sq_tex_clamp { + SQ_TEX_WRAP = 0, + SQ_TEX_MIRROR = 1, + SQ_TEX_CLAMP_LAST_TEXEL = 2, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, + SQ_TEX_CLAMP_HALF_BORDER = 4, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, + SQ_TEX_CLAMP_BORDER = 6, + SQ_TEX_MIRROR_ONCE_BORDER = 7, +}; + +enum sq_tex_swiz { + SQ_TEX_X = 0, + SQ_TEX_Y = 1, + SQ_TEX_Z = 2, + SQ_TEX_W = 3, + SQ_TEX_ZERO = 4, + SQ_TEX_ONE = 5, +}; + +enum sq_tex_filter { + SQ_TEX_FILTER_POINT = 0, + SQ_TEX_FILTER_BILINEAR = 1, + SQ_TEX_FILTER_BICUBIC = 2, +}; + +#define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 + +#define REG_A2XX_RBBM_CNTL 0x0000003b + +#define REG_A2XX_RBBM_SOFT_RESET 0x0000003c + +#define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 + +#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 + +#define REG_A2XX_CP_RB_BASE 0x000001c0 + +#define REG_A2XX_CP_RB_CNTL 0x000001c1 + +#define REG_A2XX_CP_RB_RPTR_ADDR 0x000001c3 + +#define REG_A2XX_CP_RB_RPTR 0x000001c4 + +#define REG_A2XX_CP_RB_WPTR 0x000001c5 + +#define REG_A2XX_CP_RB_WPTR_DELAY 0x000001c6 + +#define REG_A2XX_CP_RB_RPTR_WR 0x000001c7 + +#define REG_A2XX_CP_RB_WPTR_BASE 0x000001c8 + +#define REG_A2XX_CP_QUEUE_THRESHOLDS 0x000001d5 + +#define REG_A2XX_SCRATCH_UMSK 0x000001dc + +#define REG_A2XX_SCRATCH_ADDR 0x000001dd + +#define REG_A2XX_CP_STATE_DEBUG_INDEX 0x000001ec + +#define REG_A2XX_CP_STATE_DEBUG_DATA 0x000001ed + +#define REG_A2XX_CP_INT_CNTL 0x000001f2 + +#define REG_A2XX_CP_INT_STATUS 0x000001f3 + +#define REG_A2XX_CP_INT_ACK 0x000001f4 + +#define REG_A2XX_CP_ME_CNTL 0x000001f6 + +#define REG_A2XX_CP_ME_STATUS 0x000001f7 + +#define REG_A2XX_CP_ME_RAM_WADDR 0x000001f8 + +#define REG_A2XX_CP_ME_RAM_RADDR 0x000001f9 + +#define REG_A2XX_CP_ME_RAM_DATA 0x000001fa + +#define REG_A2XX_CP_DEBUG 0x000001fc + +#define REG_A2XX_CP_CSQ_RB_STAT 0x000001fd + +#define REG_A2XX_CP_CSQ_IB1_STAT 0x000001fe + +#define REG_A2XX_CP_CSQ_IB2_STAT 0x000001ff + +#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 + +#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 + +#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 + +#define REG_A2XX_RBBM_DEBUG 0x0000039b + +#define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c + +#define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d + +#define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 + +#define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 + +#define REG_A2XX_RBBM_READ_ERROR 0x000003b3 + +#define REG_A2XX_RBBM_INT_CNTL 0x000003b4 + +#define REG_A2XX_RBBM_INT_STATUS 0x000003b5 + +#define REG_A2XX_RBBM_INT_ACK 0x000003b6 + +#define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 + +#define REG_A2XX_RBBM_PERIPHID1 0x000003f9 + +#define REG_A2XX_RBBM_PERIPHID2 0x000003fa + +#define REG_A2XX_CP_PERFMON_CNTL 0x00000444 + +#define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 + +#define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 + +#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 + +#define REG_A2XX_CP_ST_BASE 0x0000044d + +#define REG_A2XX_CP_ST_BUFSZ 0x0000044e + +#define REG_A2XX_CP_IB1_BASE 0x00000458 + +#define REG_A2XX_CP_IB1_BUFSZ 0x00000459 + +#define REG_A2XX_CP_IB2_BASE 0x0000045a + +#define REG_A2XX_CP_IB2_BUFSZ 0x0000045b + +#define REG_A2XX_CP_STAT 0x0000047f + +#define REG_A2XX_SCRATCH_REG0 0x00000578 + +#define REG_A2XX_SCRATCH_REG2 0x0000057a + +#define REG_A2XX_RBBM_STATUS 0x000005d0 + +#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 +#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f +#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 +static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) +{ + return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; +} +#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 +#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 +static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) +{ + return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; +} + +#define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) + +#define REG_A2XX_VSC_PIPE_CONFIG(i0) (0x00000c06 + 0x3*(i0)) + +#define REG_A2XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c07 + 0x3*(i0)) + +#define REG_A2XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c08 + 0x3*(i0)) + +#define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 + +#define REG_A2XX_PC_DEBUG_DATA 0x00000c39 + +#define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 + +#define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 + +#define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 + +#define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 + +#define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 + +#define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 + +#define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 + +#define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 + +#define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 + +#define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 + +#define REG_A2XX_SQ_INT_CNTL 0x00000d34 + +#define REG_A2XX_SQ_INT_STATUS 0x00000d35 + +#define REG_A2XX_SQ_INT_ACK 0x00000d36 + +#define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae + +#define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf + +#define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 + +#define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 + +#define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 + +#define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 + +#define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 + +#define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 + +#define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 + +#define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 + +#define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 + +#define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 + +#define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba + +#define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb + +#define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc + +#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd + +#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe + +#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf + +#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 + +#define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 + +#define REG_A2XX_TC_CNTL_STATUS 0x00000e00 +#define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 + +#define REG_A2XX_TP0_CHICKEN 0x00000e1e + +#define REG_A2XX_RB_BC_CONTROL 0x00000f01 +#define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 +#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 +#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 +static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) +{ + return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; +} +#define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 +#define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 +#define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 +#define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 +#define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 +#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 +#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 +static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) +{ + return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; +} +#define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 +#define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 +#define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 +#define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 +#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 +#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 +static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) +{ + return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; +} +#define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 +#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 +#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 +static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) +{ + return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; +} +#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 +#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 +static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) +{ + return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; +} +#define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 +#define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 +#define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 + +#define REG_A2XX_RB_EDRAM_INFO 0x00000f02 + +#define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 + +#define REG_A2XX_RB_DEBUG_DATA 0x00000f27 + +#define REG_A2XX_RB_SURFACE_INFO 0x00002000 + +#define REG_A2XX_RB_COLOR_INFO 0x00002001 +#define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f +#define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 +static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) +{ + return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; +} +#define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 +#define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 +static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) +{ + return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; +} +#define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 +#define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 +#define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 +static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) +{ + return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; +} +#define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 +#define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 +static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) +{ + return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; +} +#define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 +#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 +static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) +{ + return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; +} + +#define REG_A2XX_RB_DEPTH_INFO 0x00002002 +#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 +#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a2xx_rb_depth_format val) +{ + return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; +} +#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 +#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 +static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) +{ + return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; +} + +#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 + +#define REG_A2XX_COHER_DEST_BASE_0 0x00002006 + +#define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e +#define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 +#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff +#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 +static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) +{ + return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; +} +#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 +#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 +static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) +{ + return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; +} + +#define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f +#define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 +#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff +#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 +static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) +{ + return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; +} +#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 +#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 +static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) +{ + return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; +} + +#define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 +#define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff +#define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; +} +#define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 +#define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; +} +#define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 + +#define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 +#define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 +#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff +#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 +static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) +{ + return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; +} +#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 +#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 +static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) +{ + return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; +} + +#define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 +#define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 +#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff +#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 +static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) +{ + return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; +} +#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 +#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 +static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) +{ + return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; +} + +#define REG_A2XX_UNKNOWN_2010 0x00002010 + +#define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 + +#define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 + +#define REG_A2XX_VGT_INDX_OFFSET 0x00002102 + +#define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 + +#define REG_A2XX_RB_COLOR_MASK 0x00002104 +#define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 +#define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 +#define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 +#define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 + +#define REG_A2XX_RB_BLEND_RED 0x00002105 + +#define REG_A2XX_RB_BLEND_GREEN 0x00002106 + +#define REG_A2XX_RB_BLEND_BLUE 0x00002107 + +#define REG_A2XX_RB_BLEND_ALPHA 0x00002108 + +#define REG_A2XX_RB_FOG_COLOR 0x00002109 + +#define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c +#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff +#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 +static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) +{ + return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; +} +#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 +#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 +static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) +{ + return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; +} +#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 +#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 +static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) +{ + return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; +} + +#define REG_A2XX_RB_STENCILREFMASK 0x0000210d +#define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff +#define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 +static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) +{ + return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; +} +#define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 +#define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 +static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) +{ + return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; +} +#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 +#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 +static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) +{ + return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; +} + +#define REG_A2XX_RB_ALPHA_REF 0x0000210e + +#define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f +#define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff +#define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 +static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) +{ + return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; +} + +#define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 +#define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff +#define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 +static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) +{ + return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; +} + +#define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 +#define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff +#define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 +static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) +{ + return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; +} + +#define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 +#define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff +#define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 +static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) +{ + return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; +} + +#define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 +#define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff +#define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 +static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) +{ + return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; +} + +#define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 +#define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff +#define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 +static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) +{ + return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; +} + +#define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 +#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff +#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 +static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) +{ + return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; +} +#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 +#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 +static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) +{ + return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; +} +#define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 +#define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 +#define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 +#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 +#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 +#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 +static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) +{ + return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; +} +#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 +#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 +static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) +{ + return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; +} +#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 +#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 +static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) +{ + return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; +} +#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 + +#define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 +#define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 +#define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 +#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c +#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 +static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) +{ + return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; +} +#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 +#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 +static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) +{ + return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; +} +#define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 +#define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 +#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 + +#define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 + +#define REG_A2XX_SQ_WRAPPING_0 0x00002183 + +#define REG_A2XX_SQ_WRAPPING_1 0x00002184 + +#define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 + +#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 + +#define REG_A2XX_RB_DEPTHCONTROL 0x00002200 +#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 +#define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 +#define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 +#define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 +#define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 +#define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 +static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; +} +#define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 +#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 +#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 +#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 +#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 +#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 +#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 +#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 +#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; +} +#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 +#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 +static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) +{ + return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; +} + +#define REG_A2XX_RB_BLEND_CONTROL 0x00002201 +#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f +#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 +static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) +{ + return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; +} +#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 +#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 +static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val) +{ + return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; +} +#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 +#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 +static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) +{ + return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; +} +#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 +#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 +static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) +{ + return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; +} +#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 +#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 +static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val) +{ + return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; +} +#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 +#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 +static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) +{ + return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; +} +#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 +#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 + +#define REG_A2XX_RB_COLORCONTROL 0x00002202 +#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 +#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 +static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) +{ + return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; +} +#define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 +#define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 +#define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 +#define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 +#define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 +#define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 +static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) +{ + return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; +} +#define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 +#define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 +static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) +{ + return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; +} +#define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 +#define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 +static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) +{ + return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; +} +#define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 +static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) +{ + return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; +} +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 +static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) +{ + return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; +} +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 +static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) +{ + return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; +} +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 +#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 +static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) +{ + return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; +} + +#define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 +#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 +#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 +static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) +{ + return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; +} +#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 +#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 +static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) +{ + return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; +} +#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 +#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 +static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) +{ + return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; +} + +#define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 +#define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 +#define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 +#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 +#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 +static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) +{ + return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; +} +#define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 +#define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 +#define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 +#define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 +#define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 + +#define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 +#define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 +#define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 +#define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 +#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 +#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 +static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) +{ + return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; +} +#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 +#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 +static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) +{ + return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; +} +#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 +#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 +static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) +{ + return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; +} +#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 +#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 +#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 +#define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 +#define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 +#define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 +#define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 +#define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 +#define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 +#define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 +#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 +#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 +#define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 +#define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 +#define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 +#define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 + +#define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 +#define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 +#define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 +#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 +#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 +#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 +#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 +#define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 +#define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 +#define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 +#define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 + +#define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 +#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 +#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 +static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) +{ + return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; +} +#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 +#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 +static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) +{ + return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; +} +#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 +#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 +static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) +{ + return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; +} + +#define REG_A2XX_RB_MODECONTROL 0x00002208 +#define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 +#define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 +static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) +{ + return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; +} + +#define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 + +#define REG_A2XX_RB_SAMPLE_POS 0x0000220a + +#define REG_A2XX_CLEAR_COLOR 0x0000220b +#define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff +#define A2XX_CLEAR_COLOR_RED__SHIFT 0 +static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) +{ + return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; +} +#define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 +#define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 +static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) +{ + return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; +} +#define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 +#define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 +static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) +{ + return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; +} +#define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 +#define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 +static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) +{ + return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; +} + +#define REG_A2XX_A220_GRAS_CONTROL 0x00002210 + +#define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 +#define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff +#define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 +static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) +{ + return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; +} +#define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 +#define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 +static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) +{ + return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; +} + +#define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 +#define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff +#define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 +static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) +{ + return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; +} +#define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 +#define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 +static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) +{ + return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; +} + +#define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 +#define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff +#define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 +static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) +{ + return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; +} + +#define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 +#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff +#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 +static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) +{ + return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; +} +#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 +#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 +static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) +{ + return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; +} +#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 +#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 +static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) +{ + return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; +} +#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 +#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 +static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) +{ + return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; +} + +#define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 + +#define REG_A2XX_VGT_ENHANCE 0x00002294 + +#define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 +#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff +#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 +static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) +{ + return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; +} +#define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 +#define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 +#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 + +#define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 + +#define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 +#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 +#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 +static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) +{ + return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; +} +#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 +#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 +static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) +{ + return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; +} +#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 +#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 +static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) +{ + return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; +} + +#define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 +#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff +#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 +static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) +{ + return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; +} + +#define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 +#define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff +#define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 +static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) +{ + return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; +} + +#define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 +#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff +#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 +static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) +{ + return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; +} + +#define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 +#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff +#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 +static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) +{ + return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; +} + +#define REG_A2XX_SQ_VS_CONST 0x00002307 +#define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff +#define A2XX_SQ_VS_CONST_BASE__SHIFT 0 +static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) +{ + return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; +} +#define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 +#define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 +static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) +{ + return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; +} + +#define REG_A2XX_SQ_PS_CONST 0x00002308 +#define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff +#define A2XX_SQ_PS_CONST_BASE__SHIFT 0 +static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) +{ + return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; +} +#define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 +#define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 +static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) +{ + return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; +} + +#define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 + +#define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a + +#define REG_A2XX_PA_SC_AA_MASK 0x00002312 + +#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 + +#define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 + +#define REG_A2XX_RB_COPY_CONTROL 0x00002318 +#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 +#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 +static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) +{ + return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; +} +#define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 +#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 +#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 +static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) +{ + return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; +} + +#define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 + +#define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a +#define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff +#define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 +static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) +{ + return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; +} + +#define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b +#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 +#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 +static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) +{ + return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; +} +#define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 +#define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 +#define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 +static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) +{ + return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; +} +#define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 +#define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 +static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) +{ + return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; +} +#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 +#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 +static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) +{ + return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; +} +#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 +#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 +static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) +{ + return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; +} +#define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 +#define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 +#define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 +#define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 + +#define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c +#define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff +#define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 +static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) +{ + return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; +} +#define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 +#define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 +static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) +{ + return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; +} + +#define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d + +#define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 + +#define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 + +#define REG_A2XX_A225_GRAS_UCP0X 0x00002340 + +#define REG_A2XX_A225_GRAS_UCP5W 0x00002357 + +#define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 + +#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 + +#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 + +#define REG_A2XX_SQ_CONSTANT_0 0x00004000 + +#define REG_A2XX_SQ_FETCH_0 0x00004800 + +#define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 + +#define REG_A2XX_SQ_CF_LOOP 0x00004908 + +#define REG_A2XX_COHER_SIZE_PM4 0x00000a29 + +#define REG_A2XX_COHER_BASE_PM4 0x00000a2a + +#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b + +#define REG_A2XX_SQ_TEX_0 0x00000000 +#define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 +#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 +static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) +{ + return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; +} +#define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 +#define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 +static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) +{ + return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; +} +#define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 +#define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 +static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) +{ + return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; +} +#define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 +#define A2XX_SQ_TEX_0_PITCH__SHIFT 22 +static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) +{ + return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; +} + +#define REG_A2XX_SQ_TEX_1 0x00000001 + +#define REG_A2XX_SQ_TEX_2 0x00000002 +#define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff +#define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 +static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) +{ + return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; +} +#define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 +#define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 +static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) +{ + return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; +} + +#define REG_A2XX_SQ_TEX_3 0x00000003 +#define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e +#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 +static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) +{ + return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; +} +#define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 +#define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 +static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) +{ + return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; +} +#define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 +#define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 +static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) +{ + return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; +} +#define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 +#define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 +static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) +{ + return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; +} +#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 +#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 +static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) +{ + return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; +} +#define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 +#define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 +static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) +{ + return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; +} + + +#endif /* A2XX_XML */ diff --git a/src/gallium/drivers/freedreno/adreno_common.xml.h b/src/gallium/drivers/freedreno/adreno_common.xml.h new file mode 100644 index 0000000000..9dd0946f77 --- /dev/null +++ b/src/gallium/drivers/freedreno/adreno_common.xml.h @@ -0,0 +1,112 @@ +#ifndef ADRENO_COMMON_XML +#define ADRENO_COMMON_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 35685 bytes, from 2013-04-05 17:33:03) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) +- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 2972 bytes, from 2013-04-05 17:32:38) +- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 7736 bytes, from 2013-04-04 20:24:12) + +Copyright (C) 2013 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +enum adreno_pa_su_sc_draw { + PC_DRAW_POINTS = 0, + PC_DRAW_LINES = 1, + PC_DRAW_TRIANGLES = 2, +}; + +enum adreno_compare_func { + FUNC_NEVER = 0, + FUNC_LESS = 1, + FUNC_EQUAL = 2, + FUNC_LEQUAL = 3, + FUNC_GREATER = 4, + FUNC_NOTEQUAL = 5, + FUNC_GEQUAL = 6, + FUNC_ALWAYS = 7, +}; + +enum adreno_stencil_op { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7, +}; + +enum adreno_rb_blend_factor { + FACTOR_ZERO = 0, + FACTOR_ONE = 1, + FACTOR_SRC_COLOR = 4, + FACTOR_ONE_MINUS_SRC_COLOR = 5, + FACTOR_SRC_ALPHA = 6, + FACTOR_ONE_MINUS_SRC_ALPHA = 7, + FACTOR_DST_COLOR = 8, + FACTOR_ONE_MINUS_DST_COLOR = 9, + FACTOR_DST_ALPHA = 10, + FACTOR_ONE_MINUS_DST_ALPHA = 11, + FACTOR_CONSTANT_COLOR = 12, + FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, + FACTOR_CONSTANT_ALPHA = 14, + FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, + FACTOR_SRC_ALPHA_SATURATE = 16, +}; + +enum adreno_rb_blend_opcode { + BLEND_DST_PLUS_SRC = 0, + BLEND_SRC_MINUS_DST = 1, + BLEND_MIN_DST_SRC = 2, + BLEND_MAX_DST_SRC = 3, + BLEND_DST_MINUS_SRC = 4, + BLEND_DST_PLUS_SRC_BIAS = 5, +}; + +enum adreno_rb_surface_endian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +}; + +enum adreno_rb_dither_mode { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +}; + + +#endif /* ADRENO_COMMON_XML */ diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h new file mode 100644 index 0000000000..14bd343b09 --- /dev/null +++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h @@ -0,0 +1,160 @@ +#ifndef ADRENO_PM4_XML +#define ADRENO_PM4_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://0x04.net/cgit/index.cgi/rules-ng-ng +git clone git://0x04.net/rules-ng-ng + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 35685 bytes, from 2013-04-05 17:33:03) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) +- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 2972 bytes, from 2013-04-05 17:32:38) +- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 7736 bytes, from 2013-04-04 20:24:12) + +Copyright (C) 2013 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +enum vgt_event_type { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +}; + +enum pc_di_primtype { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_RECTLIST = 8, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +}; + +enum pc_di_src_sel { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3, +}; + +enum pc_di_index_size { + INDEX_SIZE_IGN = 0, + INDEX_SIZE_16_BIT = 0, + INDEX_SIZE_32_BIT = 1, + INDEX_SIZE_8_BIT = 2, + INDEX_SIZE_INVALID = 0, +}; + +enum pc_di_vis_cull_mode { + IGNORE_VISIBILITY = 0, +}; + +enum adreno_pm4_packet_type { + CP_TYPE0_PKT = 0, + CP_TYPE1_PKT = 0x40000000, + CP_TYPE2_PKT = 0x80000000, + CP_TYPE3_PKT = 0xc0000000, +}; + +enum adreno_pm4_type3_packets { + CP_ME_INIT = 72, + CP_NOP = 16, + CP_INDIRECT_BUFFER = 63, + CP_INDIRECT_BUFFER_PFD = 55, + CP_WAIT_FOR_IDLE = 38, + CP_WAIT_REG_MEM = 60, + CP_WAIT_REG_EQ = 82, + CP_WAT_REG_GTE = 83, + CP_WAIT_UNTIL_READ = 92, + CP_WAIT_IB_PFD_COMPLETE = 93, + CP_REG_RMW = 33, + CP_SET_BIN_DATA = 47, + CP_REG_TO_MEM = 62, + CP_MEM_WRITE = 61, + CP_MEM_WRITE_CNTR = 79, + CP_COND_EXEC = 68, + CP_COND_WRITE = 69, + CP_EVENT_WRITE = 70, + CP_EVENT_WRITE_SHD = 88, + CP_EVENT_WRITE_CFL = 89, + CP_EVENT_WRITE_ZPD = 91, + CP_DRAW_INDX = 34, + CP_DRAW_INDX_2 = 54, + CP_DRAW_INDX_BIN = 52, + CP_DRAW_INDX_2_BIN = 53, + CP_VIZ_QUERY = 35, + CP_SET_STATE = 37, + CP_SET_CONSTANT = 45, + CP_IM_LOAD = 39, + CP_IM_LOAD_IMMEDIATE = 43, + CP_LOAD_CONSTANT_CONTEXT = 46, + CP_INVALIDATE_STATE = 59, + CP_SET_SHADER_BASES = 74, + CP_SET_BIN_MASK = 80, + CP_SET_BIN_SELECT = 81, + CP_CONTEXT_UPDATE = 94, + CP_INTERRUPT = 64, + CP_IM_STORE = 44, + CP_SET_BIN_BASE_OFFSET = 75, + CP_SET_DRAW_INIT_FLAGS = 75, + CP_SET_PROTECTED_MODE = 95, + CP_LOAD_STATE = 48, + CP_COND_INDIRECT_BUFFER_PFE = 58, + CP_COND_INDIRECT_BUFFER_PFD = 50, + CP_INDIRECT_BUFFER_PFE = 63, +}; + + +#endif /* ADRENO_PM4_XML */ diff --git a/src/gallium/drivers/freedreno/disasm.c b/src/gallium/drivers/freedreno/disasm.c index ee14ced15d..bdb4886cbe 100644 --- a/src/gallium/drivers/freedreno/disasm.c +++ b/src/gallium/drivers/freedreno/disasm.c @@ -31,7 +31,7 @@ #include <string.h> #include "disasm.h" -#include "instr.h" +#include "instr-a2xx.h" static const char *levels[] = { "\t", diff --git a/src/gallium/drivers/freedreno/freedreno_a2xx_reg.h b/src/gallium/drivers/freedreno/freedreno_a2xx_reg.h deleted file mode 100644 index 7c5982cce9..0000000000 --- a/src/gallium/drivers/freedreno/freedreno_a2xx_reg.h +++ /dev/null @@ -1,1172 +0,0 @@ -/* - * Copyright (c) 2012 Rob Clark <robdclark@gmail.com> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef FREEDRENO_A2XX_REG_H_ -#define FREEDRENO_A2XX_REG_H_ - -#include <GLES2/gl2.h> - -/* convert float to dword */ -static inline uint32_t f2d(float f) -{ - union { - float f; - uint32_t d; - } u = { - .f = f, - }; - return u.d; -} - -/* convert float to 12.4 fixed point */ -static inline uint32_t f2d12_4(float f) -{ - return (uint32_t)(f * 8.0); -} - -/* convert x,y to dword */ -static inline uint32_t xy2d(uint16_t x, uint16_t y) -{ - return ((y & 0x3fff) << 16) | (x & 0x3fff); -} - -/* - * Values for CP_EVENT_WRITE: - */ - -enum VGT_EVENT_TYPE { - VS_DEALLOC = 0, - PS_DEALLOC = 1, - VS_DONE_TS = 2, - PS_DONE_TS = 3, - CACHE_FLUSH_TS = 4, - CONTEXT_DONE = 5, - CACHE_FLUSH = 6, - VIZQUERY_START = 7, - VIZQUERY_END = 8, - SC_WAIT_WC = 9, - RST_PIX_CNT = 13, - RST_VTX_CNT = 14, - TILE_FLUSH = 15, - CACHE_FLUSH_AND_INV_TS_EVENT = 20, - ZPASS_DONE = 21, - CACHE_FLUSH_AND_INV_EVENT = 22, - PERFCOUNTER_START = 23, - PERFCOUNTER_STOP = 24, - VS_FETCH_DONE = 27, - FACENESS_FLUSH = 28, -}; - -/* - * Color/surface formats: - */ - -enum rb_colorformatx { - COLORX_4_4_4_4 = 0, - COLORX_1_5_5_5 = 1, - COLORX_5_6_5 = 2, - COLORX_8 = 3, - COLORX_8_8 = 4, - COLORX_8_8_8_8 = 5, - COLORX_S8_8_8_8 = 6, - COLORX_16_FLOAT = 7, - COLORX_16_16_FLOAT = 8, - COLORX_16_16_16_16_FLOAT = 9, - COLORX_32_FLOAT = 10, - COLORX_32_32_FLOAT = 11, - COLORX_32_32_32_32_FLOAT = 12, - COLORX_2_3_3 = 13, - COLORX_8_8_8 = 14, - COLORX_INVALID, -}; - -enum sq_surfaceformat { - FMT_1_REVERSE = 0, - FMT_1 = 1, - FMT_8 = 2, - FMT_1_5_5_5 = 3, - FMT_5_6_5 = 4, - FMT_6_5_5 = 5, - FMT_8_8_8_8 = 6, - FMT_2_10_10_10 = 7, - FMT_8_A = 8, - FMT_8_B = 9, - FMT_8_8 = 10, - FMT_Cr_Y1_Cb_Y0 = 11, - FMT_Y1_Cr_Y0_Cb = 12, - FMT_5_5_5_1 = 13, - FMT_8_8_8_8_A = 14, - FMT_4_4_4_4 = 15, - FMT_10_11_11 = 16, - FMT_11_11_10 = 17, - FMT_DXT1 = 18, - FMT_DXT2_3 = 19, - FMT_DXT4_5 = 20, - FMT_24_8 = 22, - FMT_24_8_FLOAT = 23, - FMT_16 = 24, - FMT_16_16 = 25, - FMT_16_16_16_16 = 26, - FMT_16_EXPAND = 27, - FMT_16_16_EXPAND = 28, - FMT_16_16_16_16_EXPAND = 29, - FMT_16_FLOAT = 30, - FMT_16_16_FLOAT = 31, - FMT_16_16_16_16_FLOAT = 32, - FMT_32 = 33, - FMT_32_32 = 34, - FMT_32_32_32_32 = 35, - FMT_32_FLOAT = 36, - FMT_32_32_FLOAT = 37, - FMT_32_32_32_32_FLOAT = 38, - FMT_32_AS_8 = 39, - FMT_32_AS_8_8 = 40, - FMT_16_MPEG = 41, - FMT_16_16_MPEG = 42, - FMT_8_INTERLACED = 43, - FMT_32_AS_8_INTERLACED = 44, - FMT_32_AS_8_8_INTERLACED = 45, - FMT_16_INTERLACED = 46, - FMT_16_MPEG_INTERLACED = 47, - FMT_16_16_MPEG_INTERLACED = 48, - FMT_DXN = 49, - FMT_8_8_8_8_AS_16_16_16_16 = 50, - FMT_DXT1_AS_16_16_16_16 = 51, - FMT_DXT2_3_AS_16_16_16_16 = 52, - FMT_DXT4_5_AS_16_16_16_16 = 53, - FMT_2_10_10_10_AS_16_16_16_16 = 54, - FMT_10_11_11_AS_16_16_16_16 = 55, - FMT_11_11_10_AS_16_16_16_16 = 56, - FMT_32_32_32_FLOAT = 57, - FMT_DXT3A = 58, - FMT_DXT5A = 59, - FMT_CTX1 = 60, - FMT_DXT3A_AS_1_1_1_1 = 61, - FMT_INVALID -}; - -/* - * Register addresses: - */ - -#define REG_COHER_BASE_PM4 0xa2a -#define REG_COHER_DEST_BASE_0 0x2006 -#define REG_COHER_SIZE_PM4 0xa29 -#define REG_COHER_STATUS_PM4 0xa2b -#define REG_CP_CSQ_IB1_STAT 0x01fe -#define REG_CP_CSQ_IB2_STAT 0x01ff -#define REG_CP_CSQ_RB_STAT 0x01fd -#define REG_CP_DEBUG 0x01fc -#define REG_CP_IB1_BASE 0x0458 -#define REG_CP_IB1_BUFSZ 0x0459 -#define REG_CP_IB2_BASE 0x045a -#define REG_CP_IB2_BUFSZ 0x045b -#define REG_CP_INT_ACK 0x01f4 -#define REG_CP_INT_CNTL 0x01f2 -#define REG_CP_INT_STATUS 0x01f3 -#define REG_CP_ME_CNTL 0x01f6 -#define REG_CP_ME_RAM_DATA 0x01fa -#define REG_CP_ME_RAM_RADDR 0x01f9 -#define REG_CP_ME_RAM_WADDR 0x01f8 -#define REG_CP_ME_STATUS 0x01f7 -#define REG_CP_PERFCOUNTER_HI 0x0447 -#define REG_CP_PERFCOUNTER_LO 0x0446 -#define REG_CP_PERFCOUNTER_SELECT 0x0445 -#define REG_CP_PERFMON_CNTL 0x0444 -#define REG_CP_PFP_UCODE_ADDR 0x00c0 -#define REG_CP_PFP_UCODE_DATA 0x00c1 -#define REG_CP_QUEUE_THRESHOLDS 0x01d5 -#define REG_CP_RB_BASE 0x01c0 -#define REG_CP_RB_CNTL 0x01c1 -#define REG_CP_RB_RPTR 0x01c4 -#define REG_CP_RB_RPTR_ADDR 0x01c3 -#define REG_CP_RB_RPTR_WR 0x01c7 -#define REG_CP_RB_WPTR 0x01c5 -#define REG_CP_RB_WPTR_BASE 0x01c8 -#define REG_CP_RB_WPTR_DELAY 0x01c6 -#define REG_CP_STAT 0x047f -#define REG_CP_STATE_DEBUG_DATA 0x01ed -#define REG_CP_STATE_DEBUG_INDEX 0x01ec -#define REG_CP_ST_BASE 0x044d -#define REG_CP_ST_BUFSZ 0x044e -#define REG_GRAS_DEBUG_CNTL 0x0c80 -#define REG_GRAS_DEBUG_DATA 0x0c81 -#define REG_MASTER_INT_SIGNAL 0x03b7 -#define REG_PA_CL_CLIP_CNTL 0x2204 -#define REG_PA_CL_GB_HORZ_CLIP_ADJ 0x2305 -#define REG_PA_CL_GB_HORZ_DISC_ADJ 0x2306 -#define REG_PA_CL_GB_VERT_CLIP_ADJ 0x2303 -#define REG_PA_CL_GB_VERT_DISC_ADJ 0x2304 -#define REG_PA_CL_VPORT_XOFFSET 0x2110 -#define REG_PA_CL_VPORT_XSCALE 0x210f -#define REG_PA_CL_VPORT_YOFFSET 0x2112 -#define REG_PA_CL_VPORT_YSCALE 0x2111 -#define REG_PA_CL_VPORT_ZOFFSET 0x2114 -#define REG_PA_CL_VPORT_ZSCALE 0x2113 -#define REG_PA_CL_VTE_CNTL 0x2206 -#define REG_PA_SC_AA_CONFIG 0x2301 -#define REG_PA_SC_AA_MASK 0x2312 -#define REG_PA_SC_LINE_CNTL 0x2300 -#define REG_PA_SC_LINE_STIPPLE 0x2283 -#define REG_PA_SC_SCREEN_SCISSOR_BR 0x200f -#define REG_PA_SC_SCREEN_SCISSOR_TL 0x200e -#define REG_PA_SC_VIZ_QUERY 0x2293 -#define REG_PA_SC_VIZ_QUERY_STATUS 0x0c44 -#define REG_PA_SC_WINDOW_OFFSET 0x2080 -#define REG_PA_SC_WINDOW_SCISSOR_BR 0x2082 -#define REG_PA_SC_WINDOW_SCISSOR_TL 0x2081 -#define REG_PA_SU_DEBUG_CNTL 0x0c80 -#define REG_PA_SU_DEBUG_DATA 0x0c81 -#define REG_PA_SU_FACE_DATA 0x0c86 -#define REG_PA_SU_LINE_CNTL 0x2282 -#define REG_PA_SU_POINT_MINMAX 0x2281 -#define REG_PA_SU_POINT_SIZE 0x2280 -#define REG_PA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 -#define REG_PA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 -#define REG_PA_SU_SC_MODE_CNTL 0x2205 -#define REG_PA_SU_VTX_CNTL 0x2302 -#define REG_PC_DEBUG_CNTL 0x0c38 -#define REG_PC_DEBUG_DATA 0x0c39 -#define REG_RB_ALPHA_REF 0x210e -#define REG_RB_BC_CONTROL 0x0f01 -#define REG_RB_BLEND_ALPHA 0x2108 -#define REG_RB_BLEND_BLUE 0x2107 -#define REG_RB_BLEND_CONTROL 0x2201 -#define REG_RB_BLEND_GREEN 0x2106 -#define REG_RB_BLEND_RED 0x2105 -#define REG_RBBM_CNTL 0x003b -#define REG_RBBM_DEBUG 0x039b -#define REG_RBBM_DEBUG_CNTL 0x03a1 -#define REG_RBBM_DEBUG_OUT 0x03a0 -#define REG_RBBM_INT_ACK 0x03b6 -#define REG_RBBM_INT_CNTL 0x03b4 -#define REG_RBBM_INT_STATUS 0x03b5 -#define REG_RBBM_PATCH_RELEASE 0x0001 -#define REG_RBBM_PERFCOUNTER1_HI 0x0398 -#define REG_RBBM_PERFCOUNTER1_LO 0x0397 -#define REG_RBBM_PERFCOUNTER1_SELECT 0x0395 -#define REG_RBBM_PERIPHID1 0x03f9 -#define REG_RBBM_PERIPHID2 0x03fa -#define REG_RBBM_PM_OVERRIDE1 0x039c -#define REG_RBBM_PM_OVERRIDE2 0x039d -#define REG_RBBM_READ_ERROR 0x03b3 -#define REG_RBBM_SOFT_RESET 0x003c -#define REG_RBBM_STATUS 0x05d0 -#define REG_RB_COLORCONTROL 0x2202 -#define REG_RB_COLOR_DEST_MASK 0x2326 -#define REG_RB_COLOR_INFO 0x2001 -#define REG_RB_COLOR_MASK 0x2104 -#define REG_RB_COPY_CONTROL 0x2318 -#define REG_RB_COPY_DEST_BASE 0x2319 -#define REG_RB_COPY_DEST_INFO 0x231b -#define REG_RB_COPY_DEST_OFFSET 0x231c -#define REG_RB_COPY_DEST_PITCH 0x231a -#define REG_RB_DEBUG_CNTL 0x0f26 -#define REG_RB_DEBUG_DATA 0x0f27 -#define REG_RB_DEPTH_CLEAR 0x231d -#define REG_RB_DEPTHCONTROL 0x2200 -#define REG_RB_DEPTH_INFO 0x2002 -#define REG_RB_EDRAM_INFO 0x0f02 -#define REG_RB_FOG_COLOR 0x2109 -#define REG_RB_MODECONTROL 0x2208 -#define REG_RB_SAMPLE_COUNT_CTL 0x2324 -#define REG_RB_SAMPLE_POS 0x220a -#define REG_RB_STENCILREFMASK 0x210d -#define REG_RB_STENCILREFMASK_BF 0x210c -#define REG_RB_SURFACE_INFO 0x2000 -#define REG_SCRATCH_ADDR 0x01dd -#define REG_SCRATCH_REG0 0x0578 -#define REG_SCRATCH_REG2 0x057a -#define REG_SCRATCH_UMSK 0x01dc -#define REG_SQ_CF_BOOLEANS 0x4900 -#define REG_SQ_CF_LOOP 0x4908 -#define REG_SQ_CONSTANT_0 0x4000 -#define REG_SQ_CONTEXT_MISC 0x2181 -#define REG_SQ_DEBUG_CONST_MGR_FSM 0x0daf -#define REG_SQ_DEBUG_EXP_ALLOC 0x0db3 -#define REG_SQ_DEBUG_FSM_ALU_0 0x0db1 -#define REG_SQ_DEBUG_FSM_ALU_1 0x0db2 -#define REG_SQ_DEBUG_GPR_PIX 0x0db6 -#define REG_SQ_DEBUG_GPR_VTX 0x0db5 -#define REG_SQ_DEBUG_INPUT_FSM 0x0dae -#define REG_SQ_DEBUG_MISC_0 0x2309 -#define REG_SQ_DEBUG_MISC 0x0d05 -#define REG_SQ_DEBUG_MISC_1 0x230a -#define REG_SQ_DEBUG_PIX_TB_0 0x0dbc -#define REG_SQ_DEBUG_PIX_TB_STATE_MEM 0x0dc1 -#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x0dbd -#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x0dbe -#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x0dbf -#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x0dc0 -#define REG_SQ_DEBUG_PTR_BUFF 0x0db4 -#define REG_SQ_DEBUG_TB_STATUS_SEL 0x0db7 -#define REG_SQ_DEBUG_TP_FSM 0x0db0 -#define REG_SQ_DEBUG_VTX_TB_0 0x0db8 -#define REG_SQ_DEBUG_VTX_TB_1 0x0db9 -#define REG_SQ_DEBUG_VTX_TB_STATE_MEM 0x0dbb -#define REG_SQ_DEBUG_VTX_TB_STATUS_REG 0x0dba -#define REG_SQ_FETCH_0 0x4800 -#define REG_SQ_FLOW_CONTROL 0x0d01 -#define REG_SQ_GPR_MANAGEMENT 0x0d00 -#define REG_SQ_INST_STORE_MANAGMENT 0x0d02 -#define REG_SQ_INT_ACK 0x0d36 -#define REG_SQ_INT_CNTL 0x0d34 -#define REG_SQ_INTERPOLATOR_CNTL 0x2182 -#define REG_SQ_INT_STATUS 0x0d35 -#define REG_SQ_PROGRAM_CNTL 0x2180 -#define REG_SQ_PS_CONST 0x2308 -#define REG_SQ_PS_PROGRAM 0x21f6 -#define REG_SQ_VS_CONST 0x2307 -#define REG_SQ_VS_PROGRAM 0x21f7 -#define REG_SQ_WRAPPING_0 0x2183 -#define REG_SQ_WRAPPING_1 0x2184 -#define REG_TC_CNTL_STATUS 0x0e00 -#define REG_TP0_CHICKEN 0x0e1e -#define REG_VGT_CURRENT_BIN_ID_MAX 0x2203 -#define REG_VGT_CURRENT_BIN_ID_MIN 0x2207 -#define REG_VGT_ENHANCE 0x2294 -#define REG_VGT_INDX_OFFSET 0x2102 -#define REG_VGT_MAX_VTX_INDX 0x2100 -#define REG_VGT_MIN_VTX_INDX 0x2101 -#define REG_VGT_OUT_DEALLOC_CNTL 0x2317 -#define REG_VGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 - -/* Added in a220: */ -#define REG_A220_RB_LRZ_VSC_CONTROL 0x2209 -#define REG_A220_GRAS_CONTROL 0x2210 -#define REG_A220_VSC_BIN_SIZE 0x0c01 -#define REG_A220_VSC_PIPE_DATA_LENGTH_7 0x0c1d -#define REG_VSC_PIPE_CONFIG_0 0x0c06 -#define REG_VSC_PIPE_DATA_ADDRESS_0 0x0c07 -#define REG_VSC_PIPE_DATA_LENGTH_0 0x0c08 -#define REG_VSC_PIPE_CONFIG_1 0x0c09 -#define REG_VSC_PIPE_DATA_ADDRESS_1 0x0c0a -#define REG_VSC_PIPE_DATA_LENGTH_1 0x0c0b -#define REG_VSC_PIPE_CONFIG_2 0x0c0c -#define REG_VSC_PIPE_DATA_ADDRESS_2 0x0c0d -#define REG_VSC_PIPE_DATA_LENGTH_2 0x0c0e -#define REG_VSC_PIPE_CONFIG_3 0x0c0f -#define REG_VSC_PIPE_DATA_ADDRESS_3 0x0c10 -#define REG_VSC_PIPE_DATA_LENGTH_3 0x0c11 -#define REG_VSC_PIPE_CONFIG_4 0x0c12 -#define REG_VSC_PIPE_DATA_ADDRESS_4 0x0c13 -#define REG_VSC_PIPE_DATA_LENGTH_4 0x0c14 -#define REG_VSC_PIPE_CONFIG_5 0x0c15 -#define REG_VSC_PIPE_DATA_ADDRESS_5 0x0c16 -#define REG_VSC_PIPE_DATA_LENGTH_5 0x0c17 -#define REG_VSC_PIPE_CONFIG_6 0x0c18 -#define REG_VSC_PIPE_DATA_ADDRESS_6 0x0c19 -#define REG_VSC_PIPE_DATA_LENGTH_6 0x0c1a -#define REG_VSC_PIPE_CONFIG_7 0x0c1b -#define REG_VSC_PIPE_DATA_ADDRESS_7 0x0c1c -#define REG_VSC_PIPE_DATA_LENGTH_7 0x0c1d - -/* Added in a225: */ -#define REG_A225_RB_COLOR_INFO3 0x2005 -#define REG_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x2103 -#define REG_A225_GRAS_UCP0X 0x2340 -#define REG_A225_GRAS_UCP5W 0x2357 -#define REG_A225_GRAS_UCP_ENABLED 0x2360 - -/* not sure, maybe RB_CLEAR_COLOR? */ -#define REG_CLEAR_COLOR 0x220b - -/* unnamed registers: */ -#define REG_0c02 0x0c02 -#define REG_0c04 0x0c04 -#define REG_0c06 0x0c06 -#define REG_2010 0x2010 - - -/* - * Format for 2nd dword in CP_DRAW_INDX and friends: - */ - -/* see VGT_PRIMITIVE_TYPE.PRIM_TYPE? */ -enum pc_di_primtype { - DI_PT_NONE = 0, - DI_PT_POINTLIST = 1, - DI_PT_LINELIST = 2, - DI_PT_LINESTRIP = 3, - DI_PT_TRILIST = 4, - DI_PT_TRIFAN = 5, - DI_PT_TRISTRIP = 6, - DI_PT_RECTLIST = 8, - DI_PT_QUADLIST = 13, - DI_PT_QUADSTRIP = 14, - DI_PT_POLYGON = 15, - DI_PT_2D_COPY_RECT_LIST_V0 = 16, - DI_PT_2D_COPY_RECT_LIST_V1 = 17, - DI_PT_2D_COPY_RECT_LIST_V2 = 18, - DI_PT_2D_COPY_RECT_LIST_V3 = 19, - DI_PT_2D_FILL_RECT_LIST = 20, - DI_PT_2D_LINE_STRIP = 21, - DI_PT_2D_TRI_STRIP = 22, -}; - -/* see VGT:VGT_DRAW_INITIATOR.SOURCE_SELECT? */ -enum pc_di_src_sel { - DI_SRC_SEL_DMA = 0, - DI_SRC_SEL_IMMEDIATE = 1, - DI_SRC_SEL_AUTO_INDEX = 2, - DI_SRC_SEL_RESERVED = 3, -}; - -/* see VGT_DMA_INDEX_TYPE.INDEX_TYPE? */ -enum pc_di_index_size { - INDEX_SIZE_IGN = 0, - INDEX_SIZE_16_BIT = 0, - INDEX_SIZE_32_BIT = 1, - INDEX_SIZE_8_BIT = 2, - INDEX_SIZE_INVALID -}; - -enum pc_di_vis_cull_mode { - IGNORE_VISIBILITY = 0, -}; - -static inline uint32_t DRAW(enum pc_di_primtype prim_type, - enum pc_di_src_sel source_select, enum pc_di_index_size index_size, - enum pc_di_vis_cull_mode vis_cull_mode) -{ - return (prim_type << 0) | - (source_select << 6) | - ((index_size & 1) << 11) | - ((index_size >> 1) << 13) | - (vis_cull_mode << 9) | - (1 << 14); -} - - -/* - * Bits for VGT_CURRENT_BIN_ID_MIN/MAX: - */ - -#define VGT_CURRENT_BIN_ID_MIN_COLUMN(val) (((val) & 0x7) << 0) -#define VGT_CURRENT_BIN_ID_MIN_ROW(val) (((val) & 0x7) << 3) -#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND(val) (((val) & 0x7) << 6) - - -/* - * Bits for PA_CL_VTE_CNTL: - */ - -#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 -#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 -#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 -#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 -#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 -#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 -#define PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 -#define PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 -#define PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 -#define PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 - - -/* - * Bits for PA_CL_CLIP_CNTL: - */ - -#define PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 -#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 -enum dx_clip_space { - DXCLIP_OPENGL = 0, - DXCLIP_DIRECTX = 1, -}; -static inline uint32_t PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum dx_clip_space val) -{ - return val << 19; -} -#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 -#define PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 -#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 -#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 -#define PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 - - -/* - * Bits for PA_SU_SC_MODE_CNTL: - */ - -#define PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 -#define PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 -#define PA_SU_SC_MODE_CNTL_FACE 0x00000004 -enum pa_su_sc_polymode { - POLY_DISABLED = 0, - POLY_DUALMODE = 1, -}; -static inline uint32_t PA_SU_SC_MODE_CNTL_POLYMODE(enum pa_su_sc_polymode val) -{ - return val << 3; -} -enum pa_su_sc_draw { - DRAW_POINTS = 0, - DRAW_LINES = 1, - DRAW_TRIANGLES = 2, -}; -static inline uint32_t PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(enum pa_su_sc_draw val) -{ - return val << 5; -} -static inline uint32_t PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(enum pa_su_sc_draw val) -{ - return val << 8; -} -#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 -#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 -#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 -#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 -#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 -#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 -#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 -#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 -#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 -#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 -#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 -#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 -#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 -#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 -#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 -#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 - - -/* - * Bits for PA_SC_LINE_STIPPLE: - */ - -#define PA_SC_LINE_STIPPLE_LINE_PATTERN(val) ((val) & 0x0000ffff) -#define PA_SC_LINE_STIPPLE_REPEAT_COUNT(val) (((val) << 16) & 0x00ff0000) -enum pa_sc_pattern_bit_order { - PATTERN_BIT_ORDER_LITTLE = 0, - PATTERN_BIT_ORDER_BIG = 1, -}; -static inline uint32_t PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum pa_sc_pattern_bit_order val) -{ - return val << 28; -} -enum pa_sc_auto_reset_cntl { - AUTO_RESET_NEVER = 0, - AUTO_RESET_EACH_PRIMITIVE = 1, - AUTO_RESET_EACH_PACKET = 2, -}; -static inline uint32_t PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum pa_sc_auto_reset_cntl val) -{ - return val << 29; -} - - -/* - * Bits for PA_SC_LINE_CNTL: - */ - -#define PA_SC_LINE_CNTL_BRES_CNTL_MASK(val) ((val) & 0x000000ff) -#define PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 -#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 -#define PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 - - -/* - * Bits for PA_SU_VTX_CNTL: - */ - -enum pa_pixcenter { - PIXCENTER_D3D = 0, - PIXCENTER_OGL = 1, -}; -static inline uint32_t PA_SU_VTX_CNTL_PIX_CENTER(enum pa_pixcenter val) -{ - return val; -} - -enum pa_roundmode { - TRUNCATE = 0, - ROUND = 1, - ROUNDTOEVEN = 2, - ROUNDTOODD = 3, -}; -static inline uint32_t PA_SU_VTX_CNTL_ROUND_MODE_MASK(enum pa_roundmode val) -{ - return val << 1; -} - -enum pa_quantmode { - ONE_SIXTEENTH = 0, - ONE_EIGHTH = 1, - ONE_QUARTER = 2, - ONE_HALF = 3, - ONE = 4, -}; -static inline uint32_t PA_SU_VTX_CNTL_QUANT_MODE(enum pa_quantmode val) -{ - return val << 3; -} - - -/* - * Bits for PA_SU_POINT_SIZE: - */ - -#define PA_SU_POINT_SIZE_HEIGHT(val) (f2d12_4(val) & 0xffff) -#define PA_SU_POINT_SIZE_WIDTH(val) ((f2d12_4(val) << 16) & 0xffff) - - -/* - * Bits for PA_SU_POINT_MINMAX: - */ - -#define PA_SU_POINT_MINMAX_MIN_SIZE(val) (f2d12_4(val) & 0xffff) -#define PA_SU_POINT_MINMAX_MAX_SIZE(val) ((f2d12_4(val) << 16) & 0xffff) - - -/* - * Bits for PA_SU_LINE_CNTL: - */ - -#define PA_SU_LINE_CNTL_WIDTH(val) (f2d12_4(val) & 0xffff) - - -/* - * Bits for PA_SC_WINDOW_OFFSET: - * (seems to be same as r600) - */ -#define PA_SC_WINDOW_OFFSET_X(val) ((val) & 0x7fff) -#define PA_SC_WINDOW_OFFSET_Y(val) (((val) & 0x7fff) << 16) - -#define PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 - - -/* - * Bits for SQ_CONTEXT_MISC: - */ - -#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 -#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 -enum sq_sample_cntl { - CENTROIDS_ONLY = 0, - CENTERS_ONLY = 1, - CENTROIDS_AND_CENTERS = 2, -}; -static inline uint32_t SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum sq_sample_cntl val) -{ - return (val & 0x3) << 2; -} -#define SQ_CONTEXT_MISC_PARAM_GEN_POS(val) (((val) & 0xff) << 8) -#define SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 -#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 -#define SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 - - -/* - * Bits for SQ_PROGRAM_CNTL: - */ -/* note: only 0x3f worth of valid register values, but high bit is - * set to indicate '0 registers used': - */ -#define SQ_PROGRAM_CNTL_VS_REGS(val) ((val) & 0xff) -#define SQ_PROGRAM_CNTL_PS_REGS(val) (((val) & 0xff) << 8) -#define SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 -#define SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 -#define SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 -#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 -#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(val) (((val) & 0xf) << 20) -#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE(val) (((val) & 0x7) << 24) -enum sq_ps_vtx_mode { - POSITION_1_VECTOR = 0, - POSITION_2_VECTORS_UNUSED = 1, - POSITION_2_VECTORS_SPRITE = 2, - POSITION_2_VECTORS_EDGE = 3, - POSITION_2_VECTORS_KILL = 4, - POSITION_2_VECTORS_SPRITE_KILL = 5, - POSITION_2_VECTORS_EDGE_KILL = 6, - MULTIPASS = 7, -}; -static inline uint32_t SQ_PROGRAM_CNTL_PS_EXPORT_MODE(enum sq_ps_vtx_mode val) -{ - return val << 27; -} -#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 - - -/* - * Bits for SQ_VS_CONST - */ - -#define SQ_VS_CONST_BASE(val) ((val) & 0x1ff) -#define SQ_VS_CONST_SIZE(val) (((val) & 0x1ff) << 12) - - -/* - * Bits for SQ_PS_CONST - */ - -#define SQ_PS_CONST_BASE(val) ((val) & 0x1ff) -#define SQ_PS_CONST_SIZE(val) (((val) & 0x1ff) << 12) - - -/* - * Bits for tex sampler: - */ - -/* dword0 */ -enum sq_tex_clamp { - SQ_TEX_WRAP = 0, /* GL_REPEAT */ - SQ_TEX_MIRROR = 1, /* GL_MIRRORED_REPEAT */ - SQ_TEX_CLAMP_LAST_TEXEL = 2, /* GL_CLAMP_TO_EDGE */ - /* TODO confirm these: */ - SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, - SQ_TEX_CLAMP_HALF_BORDER = 4, - SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, - SQ_TEX_CLAMP_BORDER = 6, - SQ_TEX_MIRROR_ONCE_BORDER = 7, -}; -static inline uint32_t SQ_TEX0_CLAMP_X(enum sq_tex_clamp val) -{ - return (val & 0x7) << 10; -} -static inline uint32_t SQ_TEX0_CLAMP_Y(enum sq_tex_clamp val) -{ - return (val & 0x7) << 13; -} -static inline uint32_t SQ_TEX0_CLAMP_Z(enum sq_tex_clamp val) -{ - return (val & 0x7) << 16; -} -#define SQ_TEX0_PITCH(val) (((val) >> 5) << 22) - -/* dword2 */ -#define SQ_TEX2_HEIGHT(val) (((val) - 1) << 13) -#define SQ_TEX2_WIDTH(val) ((val) - 1) - -/* dword3 */ -enum sq_tex_swiz { - SQ_TEX_X = 0, - SQ_TEX_Y = 1, - SQ_TEX_Z = 2, - SQ_TEX_W = 3, - SQ_TEX_ZERO = 4, - SQ_TEX_ONE = 5, -}; -static inline uint32_t SQ_TEX3_SWIZ_X(enum sq_tex_swiz val) -{ - return (val & 0x7) << 1; -} -static inline uint32_t SQ_TEX3_SWIZ_Y(enum sq_tex_swiz val) -{ - return (val & 0x7) << 4; -} -static inline uint32_t SQ_TEX3_SWIZ_Z(enum sq_tex_swiz val) -{ - return (val & 0x7) << 7; -} -static inline uint32_t SQ_TEX3_SWIZ_W(enum sq_tex_swiz val) -{ - return (val & 0x7) << 10; -} - -enum sq_tex_filter { - SQ_TEX_FILTER_POINT = 0, - SQ_TEX_FILTER_BILINEAR = 1, - SQ_TEX_FILTER_BICUBIC = 2, /* presumed */ -}; -static inline uint32_t SQ_TEX3_XY_MAG_FILTER(enum sq_tex_filter val) -{ - return (val & 0x3) << 19; -} -static inline uint32_t SQ_TEX3_XY_MIN_FILTER(enum sq_tex_filter val) -{ - return (val & 0x3) << 21; -} - - -/* - * Bits for RB_BLEND_CONTROL: - */ - -enum rb_blend_op { - RB_BLEND_ZERO = 0, - RB_BLEND_ONE = 1, - RB_BLEND_SRC_COLOR = 4, - RB_BLEND_ONE_MINUS_SRC_COLOR = 5, - RB_BLEND_SRC_ALPHA = 6, - RB_BLEND_ONE_MINUS_SRC_ALPHA = 7, - RB_BLEND_DST_COLOR = 8, - RB_BLEND_ONE_MINUS_DST_COLOR = 9, - RB_BLEND_DST_ALPHA = 10, - RB_BLEND_ONE_MINUS_DST_ALPHA = 11, - RB_BLEND_CONSTANT_COLOR = 12, - RB_BLEND_ONE_MINUS_CONSTANT_COLOR = 13, - RB_BLEND_CONSTANT_ALPHA = 14, - RB_BLEND_ONE_MINUS_CONSTANT_ALPHA = 15, - RB_BLEND_SRC_ALPHA_SATURATE = 16, -}; - -enum rb_comb_func { - COMB_DST_PLUS_SRC = 0, - COMB_SRC_MINUS_DST = 1, - COMB_MIN_DST_SRC = 2, - COMB_MAX_DST_SRC = 3, - COMB_DST_MINUS_SRC = 4, - COMB_DST_PLUS_SRC_BIAS = 5, -}; - -#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f -static inline uint32_t RB_BLENDCONTROL_COLOR_SRCBLEND(enum rb_blend_op val) -{ - return val & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK; -} -#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 -static inline uint32_t RB_BLENDCONTROL_COLOR_COMB_FCN(enum rb_comb_func val) -{ - return (val << 5) & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK; -} -#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 -static inline uint32_t RB_BLENDCONTROL_COLOR_DESTBLEND(enum rb_blend_op val) -{ - return (val << 8) & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK; -} -#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 -static inline uint32_t RB_BLENDCONTROL_ALPHA_SRCBLEND(enum rb_blend_op val) -{ - return (val << 16) & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK; -} -#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 -static inline uint32_t RB_BLENDCONTROL_ALPHA_COMB_FCN(enum rb_comb_func val) -{ - return (val << 21) & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK; -} -#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 -static inline uint32_t RB_BLENDCONTROL_ALPHA_DESTBLEND(enum rb_blend_op val) -{ - return (val << 24) & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK; -} -#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE 0x20000000 -#define RB_BLENDCONTROL_BLEND_FORCE 0x40000000 - - -/* - * Bits for RB_COLOR_MASK: - */ -#define RB_COLOR_MASK_WRITE_RED 0x00000001 -#define RB_COLOR_MASK_WRITE_GREEN 0x00000002 -#define RB_COLOR_MASK_WRITE_BLUE 0x00000004 -#define RB_COLOR_MASK_WRITE_ALPHA 0x00000008 - - -/* - * Bits for RB_COLOR_INFO: - */ - -#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f -static inline uint32_t RB_COLOR_INFO_COLOR_FORMAT(enum rb_colorformatx val) -{ - return val & RB_COLOR_INFO_COLOR_FORMAT_MASK; -} - -#define RB_COLOR_INFO_COLOR_ROUND_MODE(val) (((val) & 0x3) << 4) -#define RB_COLOR_INFO_COLOR_LINEAR 0x00000040 -#define RB_COLOR_INFO_COLOR_ENDIAN(val) (((val) & 0x3) << 7) -#define RB_COLOR_INFO_COLOR_SWAP(val) (((val) & 0x3) << 9) -#define RB_COLOR_INFO_COLOR_BASE(val) (((val) & 0xfffff) << 12) - - -/* - * Bits for RB_MODECONTROL: - */ - -enum rb_edram_mode { - EDRAM_NOP = 0, - COLOR_DEPTH = 4, - DEPTH_ONLY = 5, - EDRAM_COPY = 6, -}; -static inline uint32_t RB_MODECONTROL_EDRAM_MODE(enum rb_edram_mode val) -{ - return val & 0x7; -} - - -/* - * Bits for RB_DEPTHCONTROL: - */ - -#define RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 -#define RB_DEPTHCONTROL_Z_ENABLE 0x00000002 -#define RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 -#define RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 -#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 -#define RB_DEPTHCONTROL_ZFUNC(depth_func) \ - (((depth_func) << 4) & RB_DEPTHCONTROL_ZFUNC_MASK) -#define RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 -#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 -#define RB_DEPTHCONTROL_STENCILFUNC(depth_func) \ - (((depth_func) << 8) & RB_DEPTHCONTROL_STENCILFUNC_MASK) -enum rb_stencil_op { - STENCIL_KEEP = 0, - STENCIL_ZERO = 1, - STENCIL_REPLACE = 2, - STENCIL_INCR_CLAMP = 3, - STENCIL_DECR_CLAMP = 4, - STENCIL_INVERT = 5, - STENCIL_INCR_WRAP = 6, - STENCIL_DECR_WRAP = 7 -}; -#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 -static inline uint32_t RB_DEPTHCONTROL_STENCILFAIL(enum rb_stencil_op val) -{ - return (val << 11) & RB_DEPTHCONTROL_STENCILFAIL_MASK; -} -#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 -static inline uint32_t RB_DEPTHCONTROL_STENCILZPASS(enum rb_stencil_op val) -{ - return (val << 14) & RB_DEPTHCONTROL_STENCILZPASS_MASK; -} -#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 -static inline uint32_t RB_DEPTHCONTROL_STENCILZFAIL(enum rb_stencil_op val) -{ - return (val << 17) & RB_DEPTHCONTROL_STENCILZFAIL_MASK; -} -#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 -#define RB_DEPTHCONTROL_STENCILFUNC_BF(depth_func) \ - (((depth_func) << 20) & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) -#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 -static inline uint32_t RB_DEPTHCONTROL_STENCILFAIL_BF(enum rb_stencil_op val) -{ - return (val << 23) & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK; -} -#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 -static inline uint32_t RB_DEPTHCONTROL_STENCILZPASS_BF(enum rb_stencil_op val) -{ - return (val << 26) & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK; -} -#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 -static inline uint32_t RB_DEPTHCONTROL_STENCILZFAIL_BF(enum rb_stencil_op val) -{ - return (val << 29) & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK; -} - - -/* - * Bits for RB_COPY_DEST_INFO: - */ - -enum rb_surface_endian { - ENDIAN_NONE = 0, - ENDIAN_8IN16 = 1, - ENDIAN_8IN32 = 2, - ENDIAN_16IN32 = 3, - ENDIAN_8IN64 = 4, - ENDIAN_8IN128 = 5, -}; -static inline uint32_t RB_COPY_DEST_INFO_DEST_ENDIAN(enum rb_surface_endian val) -{ - return (val & 0x7) << 0; -} -#define RB_COPY_DEST_INFO_LINEAR 0x00000008 -static inline uint32_t RB_COPY_DEST_INFO_FORMAT(enum rb_colorformatx val) -{ - return val << 4; -} -#define RB_COPY_DEST_INFO_SWAP(val) (((val) & 0x3) << 8) /* maybe VGT_DMA_SWAP_MODE? */ -enum rb_dither_mode { - DITHER_DISABLE = 0, - DITHER_ALWAYS = 1, - DITHER_IF_ALPHA_OFF = 2, -}; -static inline uint32_t RB_COPY_DEST_INFO_DITHER_MODE(enum rb_dither_mode val) -{ - return val << 10; -} -enum rb_dither_type { - DITHER_PIXEL = 0, - DITHER_SUBPIXEL = 1, -}; -static inline uint32_t RB_COPY_DEST_INFO_DITHER_TYPE(enum rb_dither_type val) -{ - return val << 12; -} -#define RB_COPY_DEST_INFO_WRITE_RED 0x00004000 -#define RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 -#define RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 -#define RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 - - -/* - * Bits for RB_COPY_DEST_OFFSET: - */ - -#define RB_COPY_DEST_OFFSET_X(val) ((val) & 0x3fff) -#define RB_COPY_DEST_OFFSET_Y(val) (((val) & 0x3fff) << 13) - - -/* - * Bits for RB_COPY_CONTROL: - */ - -#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008L -#define RB_COPY_CONTROL_CLEAR_MASK(val) ((val & 0xf) << 4) - - -/* - * Bits for RB_COLORCONTROL: - */ - -#define RB_COLORCONTROL_ALPHA_FUNC(val) ((val) & 0x7) -#define RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 -#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 -#define RB_COLORCONTROL_BLEND_DISABLE 0x00000020 -#define RB_COLORCONTROL_FOG_ENABLE 0x00000040 -#define RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 -#define RB_COLORCONTROL_ROP_CODE(val) (((val) & 0xf) << 8) -static inline uint32_t RB_COLORCONTROL_DITHER_MODE(enum rb_dither_mode val) -{ - return (val & 0x3) << 12; -} -static inline uint32_t RB_COLORCONTROL_DITHER_TYPE(enum rb_dither_type val) -{ - return (val & 0x3) << 14; -} -#define RB_COLORCONTROL_PIXEL_FOG 0x00010000 -#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(val) (((val) & 0x3) << 24) -#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(val) (((val) & 0x3) << 26) -#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(val) (((val) & 0x3) << 28) -#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(val) (((val) & 0x3) << 30) - - -/* - * Bits for RB_DEPTH_INFO: - */ - -enum rb_depth_format { - DEPTHX_16 = 0, - DEPTHX_24_8 = 1, - DEPTHX_INVALID, -}; - -static inline uint32_t RB_DEPTH_INFO_DEPTH_FORMAT(enum rb_depth_format val) -{ - return val & 0x1; -} -#define RB_DEPTH_INFO_DEPTH_BASE(val) ((val) << 12) - - -/* - * Bits for RB_STENCILREFMASK (RB_STENCILREFMASK_BF is same): - */ - -#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff -#define RB_STENCILREFMASK_STENCILREF(val) ((val) & RB_STENCILREFMASK_STENCILREF_MASK) -#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 -#define RB_STENCILREFMASK_STENCILMASK(val) (((val) << 8) & RB_STENCILREFMASK_STENCILMASK_MASK) -#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 -#define RB_STENCILREFMASK_STENCILWRITEMASK(val) (((val) << 16) & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) - - -/* - * Bits for RB_BC_CONTROL: - */ - -#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 -#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(val) (((val) & 0x3) << 1) -#define RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 -#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 -#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 -#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 -#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 -#define RB_BC_CONTROL_AZ_THROTTLE_COUNT(val) (((val) & 0x1f) << 8) -#define RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 -#define RB_BC_CONTROL_CRC_MODE 0x00008000 -#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 -#define RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 -#define RB_BC_CONTROL_ACCUM_ALLOC_MASK(val) (((val) & 0xf) << 18) -#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 -#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(val) (((val) & 0xf) << 23) -#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(val) (((val) & 0x3) << 27) -#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 -#define RB_BC_CONTROL_CRC_SYSTEM 0x40000000 -#define RB_BC_CONTROL_RESERVED6 0x80000000 - - -/* - * Bits for RBBM_PM_OVERRIDE1: - */ - -#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 -#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 -#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 -#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 -#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 -#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 -#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 -#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 -#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 -#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 -#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 -#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 -#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 -#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 -#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 -#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 -#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 -#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 -#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 -#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 -#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 -#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 -#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 -#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 -#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 -#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 -#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 -#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 -#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 -#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 -#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 -#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 - - -/* - * Bits for RBBM_PM_OVERRIDE2: - */ - -#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE 0x00000001 -#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE 0x00000002 -#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE 0x00000004 -#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE 0x00000008 -#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010 -#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE 0x00000020 -#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040 -#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE 0x00000080 -#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE 0x00000100 -#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE 0x00000200 -#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE 0x00000400 -#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE 0x00000800 - - -/* - * Bits for TC_CNTL_STATUS: - */ - -#define TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 - - -#endif /* FREEDRENO_A2XX_REG_H_ */ diff --git a/src/gallium/drivers/freedreno/freedreno_blend.c b/src/gallium/drivers/freedreno/freedreno_blend.c index c965a73670..cd6e94503e 100644 --- a/src/gallium/drivers/freedreno/freedreno_blend.c +++ b/src/gallium/drivers/freedreno/freedreno_blend.c @@ -34,41 +34,41 @@ #include "freedreno_context.h" #include "freedreno_util.h" -static enum rb_blend_op +static enum adreno_rb_blend_factor blend_factor(unsigned factor) { switch (factor) { case PIPE_BLENDFACTOR_ONE: - return RB_BLEND_ONE; + return FACTOR_ONE; case PIPE_BLENDFACTOR_SRC_COLOR: - return RB_BLEND_SRC_COLOR; + return FACTOR_SRC_COLOR; case PIPE_BLENDFACTOR_SRC_ALPHA: - return RB_BLEND_SRC_ALPHA; + return FACTOR_SRC_ALPHA; case PIPE_BLENDFACTOR_DST_ALPHA: - return RB_BLEND_DST_ALPHA; + return FACTOR_DST_ALPHA; case PIPE_BLENDFACTOR_DST_COLOR: - return RB_BLEND_DST_COLOR; + return FACTOR_DST_COLOR; case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: - return RB_BLEND_SRC_ALPHA_SATURATE; + return FACTOR_SRC_ALPHA_SATURATE; case PIPE_BLENDFACTOR_CONST_COLOR: - return RB_BLEND_CONSTANT_COLOR; + return FACTOR_CONSTANT_COLOR; case PIPE_BLENDFACTOR_CONST_ALPHA: - return RB_BLEND_CONSTANT_ALPHA; + return FACTOR_CONSTANT_ALPHA; case PIPE_BLENDFACTOR_ZERO: case 0: - return RB_BLEND_ZERO; + return FACTOR_ZERO; case PIPE_BLENDFACTOR_INV_SRC_COLOR: - return RB_BLEND_ONE_MINUS_SRC_COLOR; + return FACTOR_ONE_MINUS_SRC_COLOR; case PIPE_BLENDFACTOR_INV_SRC_ALPHA: - return RB_BLEND_ONE_MINUS_SRC_ALPHA; + return FACTOR_ONE_MINUS_SRC_ALPHA; case PIPE_BLENDFACTOR_INV_DST_ALPHA: - return RB_BLEND_ONE_MINUS_DST_ALPHA; + return FACTOR_ONE_MINUS_DST_ALPHA; case PIPE_BLENDFACTOR_INV_DST_COLOR: - return RB_BLEND_ONE_MINUS_DST_COLOR; + return FACTOR_ONE_MINUS_DST_COLOR; case PIPE_BLENDFACTOR_INV_CONST_COLOR: - return RB_BLEND_ONE_MINUS_CONSTANT_COLOR; + return FACTOR_ONE_MINUS_CONSTANT_COLOR; case PIPE_BLENDFACTOR_INV_CONST_ALPHA: - return RB_BLEND_ONE_MINUS_CONSTANT_ALPHA; + return FACTOR_ONE_MINUS_CONSTANT_ALPHA; case PIPE_BLENDFACTOR_INV_SRC1_COLOR: case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: case PIPE_BLENDFACTOR_SRC1_COLOR: @@ -80,20 +80,20 @@ blend_factor(unsigned factor) } } -static enum rb_comb_func +static enum adreno_rb_blend_opcode blend_func(unsigned func) { switch (func) { case PIPE_BLEND_ADD: - return COMB_DST_PLUS_SRC; + return BLEND_DST_PLUS_SRC; case PIPE_BLEND_MIN: - return COMB_MIN_DST_SRC; + return BLEND_MIN_DST_SRC; case PIPE_BLEND_MAX: - return COMB_MAX_DST_SRC; + return BLEND_MAX_DST_SRC; case PIPE_BLEND_SUBTRACT: - return COMB_SRC_MINUS_DST; + return BLEND_SRC_MINUS_DST; case PIPE_BLEND_REVERSE_SUBTRACT: - return COMB_DST_MINUS_SRC; + return BLEND_DST_MINUS_SRC; default: DBG("invalid blend func: %x", func); return 0; @@ -123,30 +123,30 @@ fd_blend_state_create(struct pipe_context *pctx, so->base = *cso; - so->rb_colorcontrol = RB_COLORCONTROL_ROP_CODE(12); + so->rb_colorcontrol = A2XX_RB_COLORCONTROL_ROP_CODE(12); so->rb_blendcontrol = - RB_BLENDCONTROL_COLOR_SRCBLEND(blend_factor(rt->rgb_src_factor)) | - RB_BLENDCONTROL_COLOR_COMB_FCN(blend_func(rt->rgb_func)) | - RB_BLENDCONTROL_COLOR_DESTBLEND(blend_factor(rt->rgb_dst_factor)) | - RB_BLENDCONTROL_ALPHA_SRCBLEND(blend_factor(rt->alpha_src_factor)) | - RB_BLENDCONTROL_ALPHA_COMB_FCN(blend_func(rt->alpha_func)) | - RB_BLENDCONTROL_ALPHA_DESTBLEND(blend_factor(rt->alpha_dst_factor)); + A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(blend_factor(rt->rgb_src_factor)) | + A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(blend_func(rt->rgb_func)) | + A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(blend_factor(rt->rgb_dst_factor)) | + A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(blend_factor(rt->alpha_src_factor)) | + A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(blend_func(rt->alpha_func)) | + A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(blend_factor(rt->alpha_dst_factor)); if (rt->colormask & PIPE_MASK_R) - so->rb_colormask |= RB_COLOR_MASK_WRITE_RED; + so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_RED; if (rt->colormask & PIPE_MASK_G) - so->rb_colormask |= RB_COLOR_MASK_WRITE_GREEN; + so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_GREEN; if (rt->colormask & PIPE_MASK_B) - so->rb_colormask |= RB_COLOR_MASK_WRITE_BLUE; + so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_BLUE; if (rt->colormask & PIPE_MASK_A) - so->rb_colormask |= RB_COLOR_MASK_WRITE_ALPHA; + so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_ALPHA; if (!rt->blend_enable) - so->rb_colorcontrol |= RB_COLORCONTROL_BLEND_DISABLE; + so->rb_colorcontrol |= A2XX_RB_COLORCONTROL_BLEND_DISABLE; if (cso->dither) - so->rb_colorcontrol |= RB_COLORCONTROL_DITHER_MODE(DITHER_ALWAYS); + so->rb_colorcontrol |= A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_ALWAYS); return so; } diff --git a/src/gallium/drivers/freedreno/freedreno_clear.c b/src/gallium/drivers/freedreno/freedreno_clear.c index f3fd1a256d..149c023d6f 100644 --- a/src/gallium/drivers/freedreno/freedreno_clear.c +++ b/src/gallium/drivers/freedreno/freedreno_clear.c @@ -82,48 +82,48 @@ fd_clear(struct pipe_context *pctx, unsigned buffers, }, 1); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); OUT_RING(ring, 0); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); OUT_RING(ring, 0x0000028f); fd_program_emit(ring, &ctx->solid_prog); - OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1); - OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE); + OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1); + OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_CLEAR_COLOR)); + OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR)); OUT_RING(ring, colr); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_A220_RB_LRZ_VSC_CONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL)); OUT_RING(ring, 0x00000084); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL)); reg = 0; if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { - reg |= RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE; + reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE; switch (fd_pipe2depth(fb->zsbuf->format)) { case DEPTHX_24_8: if (buffers & PIPE_CLEAR_DEPTH) - reg |= RB_COPY_CONTROL_CLEAR_MASK(0xe); + reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe); if (buffers & PIPE_CLEAR_STENCIL) - reg |= RB_COPY_CONTROL_CLEAR_MASK(0x1); + reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1); break; case DEPTHX_16: if (buffers & PIPE_CLEAR_DEPTH) - reg |= RB_COPY_CONTROL_CLEAR_MASK(0xf); + reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf); break; } } OUT_RING(ring, reg); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_DEPTH_CLEAR)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR)); reg = 0; if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { switch (fd_pipe2depth(fb->zsbuf->format)) { @@ -139,45 +139,45 @@ fd_clear(struct pipe_context *pctx, unsigned buffers, OUT_RING(ring, reg); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); reg = 0; if (buffers & PIPE_CLEAR_DEPTH) { - reg |= RB_DEPTHCONTROL_ZFUNC(GL_ALWAYS) | - RB_DEPTHCONTROL_Z_ENABLE | - RB_DEPTHCONTROL_Z_WRITE_ENABLE | - RB_DEPTHCONTROL_EARLY_Z_ENABLE; + reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) | + A2XX_RB_DEPTHCONTROL_Z_ENABLE | + A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE | + A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE; } if (buffers & PIPE_CLEAR_STENCIL) { - reg |= RB_DEPTHCONTROL_STENCILFUNC(GL_ALWAYS) | - RB_DEPTHCONTROL_STENCIL_ENABLE | - RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE); + reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) | + A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE | + A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE); } OUT_RING(ring, reg); OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); OUT_RING(ring, 0x00000000); /* PA_CL_CLIP_CNTL */ - OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */ - PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) | - PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES)); + OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */ + A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) | + A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); OUT_RING(ring, 0x0000ffff); OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL)); OUT_RING(ring, xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */ OUT_RING(ring, xy2d(fb->width, /* PA_SC_WINDOW_SCISSOR_BR */ fb->height)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); if (buffers & PIPE_CLEAR_COLOR) { - OUT_RING(ring, RB_COLOR_MASK_WRITE_RED | - RB_COLOR_MASK_WRITE_GREEN | - RB_COLOR_MASK_WRITE_BLUE | - RB_COLOR_MASK_WRITE_ALPHA); + OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED | + A2XX_RB_COLOR_MASK_WRITE_GREEN | + A2XX_RB_COLOR_MASK_WRITE_BLUE | + A2XX_RB_COLOR_MASK_WRITE_ALPHA); } else { OUT_RING(ring, 0x0); } @@ -189,11 +189,11 @@ fd_clear(struct pipe_context *pctx, unsigned buffers, OUT_RING(ring, 3); /* NumIndices */ OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_A220_RB_LRZ_VSC_CONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL)); OUT_RING(ring, 0x00000000); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL)); OUT_RING(ring, 0x00000000); ctx->dirty |= FD_DIRTY_ZSA | diff --git a/src/gallium/drivers/freedreno/freedreno_compiler.c b/src/gallium/drivers/freedreno/freedreno_compiler.c index 0610902a89..7eed8fae3b 100644 --- a/src/gallium/drivers/freedreno/freedreno_compiler.c +++ b/src/gallium/drivers/freedreno/freedreno_compiler.c @@ -40,7 +40,7 @@ #include "freedreno_compiler.h" #include "freedreno_util.h" -#include "instr.h" +#include "instr-a2xx.h" #include "ir.h" struct fd_compile_context { @@ -875,10 +875,10 @@ translate_sge_slt(struct fd_compile_context *ctx, * in assembler/disassembler and what ir.c expects * is: MULADDv Rdst = Rsrc2 + Rsrc0 * Rscr1 */ - get_immediate(ctx, &tmp_const, f2d(c0)); + get_immediate(ctx, &tmp_const, fui(c0)); add_src_reg(ctx, instr, &tmp_const); add_src_reg(ctx, instr, &tmp_src); - get_immediate(ctx, &tmp_const, f2d(c1)); + get_immediate(ctx, &tmp_const, fui(c1)); add_src_reg(ctx, instr, &tmp_const); } @@ -896,7 +896,7 @@ translate_lrp(struct fd_compile_context *ctx, get_internal_temp(ctx, &inst->Dst[0].Register, &tmp_dst1, &tmp_src1); get_internal_temp(ctx, NULL, &tmp_dst2, &tmp_src2); - get_immediate(ctx, &tmp_const, f2d(1.0)); + get_immediate(ctx, &tmp_const, fui(1.0)); /* tmp1 = (a * b) */ instr = ir_instr_create_alu(next_exec_cf(ctx), MULv, ~0); @@ -957,10 +957,10 @@ translate_trig(struct fd_compile_context *ctx, */ instr = ir_instr_create_alu(next_exec_cf(ctx), MULADDv, ~0); add_dst_reg(ctx, instr, &tmp_dst); - get_immediate(ctx, &tmp_const, f2d(0.5)); + get_immediate(ctx, &tmp_const, fui(0.5)); add_src_reg(ctx, instr, &tmp_const); add_src_reg(ctx, instr, &inst->Src[0].Register); - get_immediate(ctx, &tmp_const, f2d(0.159155)); + get_immediate(ctx, &tmp_const, fui(0.159155)); add_src_reg(ctx, instr, &tmp_const); instr = ir_instr_create_alu(next_exec_cf(ctx), FRACv, ~0); @@ -970,10 +970,10 @@ translate_trig(struct fd_compile_context *ctx, instr = ir_instr_create_alu(next_exec_cf(ctx), MULADDv, ~0); add_dst_reg(ctx, instr, &tmp_dst); - get_immediate(ctx, &tmp_const, f2d(-3.141593)); + get_immediate(ctx, &tmp_const, fui(-3.141593)); add_src_reg(ctx, instr, &tmp_const); add_src_reg(ctx, instr, &tmp_src); - get_immediate(ctx, &tmp_const, f2d(6.283185)); + get_immediate(ctx, &tmp_const, fui(6.283185)); add_src_reg(ctx, instr, &tmp_const); instr = ir_instr_create_alu(next_exec_cf(ctx), ~0, op); diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c index 896e434a92..60374cc984 100644 --- a/src/gallium/drivers/freedreno/freedreno_gmem.c +++ b/src/gallium/drivers/freedreno/freedreno_gmem.c @@ -78,23 +78,24 @@ emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base, struct fd_resource *rsc = fd_resource(psurf->texture); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO)); - OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) | - RB_COLOR_INFO_COLOR_BASE(base / 1024) | - RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format))); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO)); + OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) | + A2XX_RB_COLOR_INFO_BASE(base / 1024) | + A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format))); OUT_PKT3(ring, CP_SET_CONSTANT, 5); - OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL)); OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */ OUT_RELOC(ring, rsc->bo, 0, 0); /* RB_COPY_DEST_BASE */ OUT_RING(ring, rsc->pitch >> 5); /* RB_COPY_DEST_PITCH */ - OUT_RING(ring, RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) | - RB_COPY_DEST_INFO_LINEAR | /* RB_COPY_DEST_INFO */ - RB_COPY_DEST_INFO_SWAP(swap) | - RB_COPY_DEST_INFO_WRITE_RED | - RB_COPY_DEST_INFO_WRITE_GREEN | - RB_COPY_DEST_INFO_WRITE_BLUE | - RB_COPY_DEST_INFO_WRITE_ALPHA); + OUT_RING(ring, /* RB_COPY_DEST_INFO */ + A2XX_RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) | + A2XX_RB_COPY_DEST_INFO_LINEAR | + A2XX_RB_COPY_DEST_INFO_SWAP(swap) | + A2XX_RB_COPY_DEST_INFO_WRITE_RED | + A2XX_RB_COPY_DEST_INFO_WRITE_GREEN | + A2XX_RB_COPY_DEST_INFO_WRITE_BLUE | + A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA); OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); OUT_RING(ring, 0x0000000); @@ -117,53 +118,54 @@ emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring, }, 1); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); OUT_RING(ring, 0); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); OUT_RING(ring, 0x0000028f); fd_program_emit(ring, &ctx->solid_prog); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); OUT_RING(ring, 0x0000ffff); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL)); - OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE); + OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); + OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL)); - OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */ - PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) | - PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL)); + OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */ + A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) | + A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES)); OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL)); OUT_RING(ring, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */ OUT_RING(ring, xy2d(pfb->width, pfb->height)); /* PA_SC_WINDOW_SCISSOR_BR */ OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL)); - OUT_RING(ring, PA_CL_VTE_CNTL_VTX_W0_FMT | - PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | - PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL)); + OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT | + A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); OUT_RING(ring, 0x00000000); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_MODECONTROL)); - OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL)); + OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COPY_DEST_OFFSET)); - OUT_RING(ring, RB_COPY_DEST_OFFSET_X(xoff) | RB_COPY_DEST_OFFSET_Y(yoff)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET)); + OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(xoff) | + A2XX_RB_COPY_DEST_OFFSET_Y(yoff)); if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) emit_gmem2mem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf); @@ -172,8 +174,8 @@ emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring, emit_gmem2mem_surf(ring, 1, 0, pfb->cbufs[0]); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_MODECONTROL)); - OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL)); + OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH)); } /* transfer from system memory to gmem */ @@ -186,10 +188,10 @@ emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base, uint32_t swiz; OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO)); - OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) | - RB_COLOR_INFO_COLOR_BASE(base / 1024) | - RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format))); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO)); + OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) | + A2XX_RB_COLOR_INFO_BASE(base) | + A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format))); swiz = fd_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN, PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA); @@ -197,18 +199,18 @@ emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base, /* emit fb as a texture: */ OUT_PKT3(ring, CP_SET_CONSTANT, 7); OUT_RING(ring, 0x00010000); - OUT_RING(ring, SQ_TEX0_CLAMP_X(SQ_TEX_WRAP) | - SQ_TEX0_CLAMP_Y(SQ_TEX_WRAP) | - SQ_TEX0_CLAMP_Z(SQ_TEX_WRAP) | - SQ_TEX0_PITCH(rsc->pitch)); + OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) | + A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) | + A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) | + A2XX_SQ_TEX_0_PITCH(rsc->pitch)); OUT_RELOC(ring, rsc->bo, 0, fd_pipe2surface(psurf->format) | 0x800); - OUT_RING(ring, SQ_TEX2_WIDTH(psurf->width) | - SQ_TEX2_HEIGHT(psurf->height)); + OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) | + A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1)); OUT_RING(ring, 0x01000000 | // XXX swiz | - SQ_TEX3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) | - SQ_TEX3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT)); + A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) | + A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT)); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000200); @@ -238,83 +240,83 @@ emit_mem2gmem(struct fd_context *ctx, struct fd_ringbuffer *ring, y1 = ((float)yoff + bin_h) / ((float)pfb->height); OUT_PKT3(ring, CP_MEM_WRITE, 9); OUT_RELOC(ring, fd_resource(ctx->solid_vertexbuf)->bo, 0x60, 0); - OUT_RING(ring, f2d(x0)); - OUT_RING(ring, f2d(y0)); - OUT_RING(ring, f2d(x1)); - OUT_RING(ring, f2d(y0)); - OUT_RING(ring, f2d(x0)); - OUT_RING(ring, f2d(y1)); - OUT_RING(ring, f2d(x1)); - OUT_RING(ring, f2d(y1)); + OUT_RING(ring, fui(x0)); + OUT_RING(ring, fui(y0)); + OUT_RING(ring, fui(x1)); + OUT_RING(ring, fui(y0)); + OUT_RING(ring, fui(x0)); + OUT_RING(ring, fui(y1)); + OUT_RING(ring, fui(x1)); + OUT_RING(ring, fui(y1)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); OUT_RING(ring, 0); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); OUT_RING(ring, 0x0000003b); fd_program_emit(ring, &ctx->blit_prog); - OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1); - OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE); + OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1); + OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL)); - OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE); + OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); + OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL)); - OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | - PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) | - PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL)); + OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | + A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) | + A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); OUT_RING(ring, 0x0000ffff); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLORCONTROL)); - OUT_RING(ring, RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) | - RB_COLORCONTROL_BLEND_DISABLE | - RB_COLORCONTROL_ROP_CODE(12) | - RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) | - RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL)); + OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) | + A2XX_RB_COLORCONTROL_BLEND_DISABLE | + A2XX_RB_COLORCONTROL_ROP_CODE(12) | + A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) | + A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_BLEND_CONTROL)); - OUT_RING(ring, RB_BLENDCONTROL_COLOR_SRCBLEND(RB_BLEND_ONE) | - RB_BLENDCONTROL_COLOR_COMB_FCN(COMB_DST_PLUS_SRC) | - RB_BLENDCONTROL_COLOR_DESTBLEND(RB_BLEND_ZERO) | - RB_BLENDCONTROL_ALPHA_SRCBLEND(RB_BLEND_ONE) | - RB_BLENDCONTROL_ALPHA_COMB_FCN(COMB_DST_PLUS_SRC) | - RB_BLENDCONTROL_ALPHA_DESTBLEND(RB_BLEND_ZERO)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); + OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) | + A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) | + A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) | + A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) | + A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) | + A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO)); OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL)); - OUT_RING(ring, PA_SC_WINDOW_OFFSET_DISABLE | + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL)); + OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE | xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */ OUT_RING(ring, xy2d(bin_w, bin_h)); /* PA_SC_WINDOW_SCISSOR_BR */ OUT_PKT3(ring, CP_SET_CONSTANT, 5); - OUT_RING(ring, CP_REG(REG_PA_CL_VPORT_XSCALE)); - OUT_RING(ring, f2d((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */ - OUT_RING(ring, f2d((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */ - OUT_RING(ring, f2d(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */ - OUT_RING(ring, f2d((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */ + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE)); + OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */ + OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */ + OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */ + OUT_RING(ring, fui((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */ OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL)); - OUT_RING(ring, PA_CL_VTE_CNTL_VTX_XY_FMT | - PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this??? - PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | - PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL)); + OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT | + A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this??? + A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); OUT_RING(ring, 0x00000000); if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) @@ -395,18 +397,12 @@ fd_gmem_render_tiles(struct pipe_context *pctx) struct pipe_framebuffer_state *pfb = &ctx->framebuffer; struct fd_gmem_stateobj *gmem = &ctx->gmem; struct fd_ringbuffer *ring = ctx->ring; - enum rb_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format); + enum a2xx_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format); uint32_t i, timestamp, yoff = 0; - uint32_t base, reg; + uint32_t reg; calculate_tiles(ctx); - /* this should be true because bin_w/bin_h should be multiples of 32: */ - assert(((gmem->bin_w * gmem->bin_h) % 1024) == 0); - - /* depth/stencil starts after color buffer in GMEM: */ - base = (gmem->bin_w * gmem->bin_h) / 1024; - DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y, util_format_name(pfb->cbufs[0]->format), pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none"); @@ -419,13 +415,13 @@ fd_gmem_render_tiles(struct pipe_context *pctx) * needs to be emitted for each tile: */ OUT_PKT3(ring, CP_SET_CONSTANT, 4); - OUT_RING(ring, CP_REG(REG_RB_SURFACE_INFO)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO)); OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */ - OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(1) | /* RB_COLOR_INFO */ - RB_COLOR_INFO_COLOR_FORMAT(colorformatx)); - reg = RB_DEPTH_INFO_DEPTH_BASE(ALIGN(base, 4)); + OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */ + A2XX_RB_COLOR_INFO_FORMAT(colorformatx)); + reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem->bin_w * gmem->bin_h, 4)); if (pfb->zsbuf) - reg |= RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format)); + reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format)); OUT_RING(ring, reg); /* RB_DEPTH_INFO */ yoff= gmem->miny; @@ -445,17 +441,9 @@ fd_gmem_render_tiles(struct pipe_context *pctx) DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d", bh, yoff, bw, xoff); - if ((i == 0) && (j == 0)) { - uint32_t reg; - - - } else { - - } - /* setup screen scissor for current tile (same for mem2gmem): */ OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL)); OUT_RING(ring, xy2d(0,0)); /* PA_SC_SCREEN_SCISSOR_TL */ OUT_RING(ring, xy2d(bw, bh)); /* PA_SC_SCREEN_SCISSOR_BR */ @@ -463,23 +451,23 @@ fd_gmem_render_tiles(struct pipe_context *pctx) emit_mem2gmem(ctx, ring, xoff, yoff, bw, bh); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO)); - OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(1) | /* RB_COLOR_INFO */ - RB_COLOR_INFO_COLOR_FORMAT(colorformatx)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO)); + OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */ + A2XX_RB_COLOR_INFO_FORMAT(colorformatx)); /* setup window scissor and offset for current tile (different * from mem2gmem): */ OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET)); - OUT_RING(ring, PA_SC_WINDOW_OFFSET_X(-xoff) | - PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */ + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET)); + OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff) | + A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */ /* emit IB to drawcmds: */ OUT_IB (ring, ctx->draw_start, ctx->draw_end); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET)); OUT_RING(ring, 0x00000000); /* PA_SC_WINDOW_OFFSET */ /* emit gmem2mem to transfer tile back to system memory: */ diff --git a/src/gallium/drivers/freedreno/freedreno_pm4.h b/src/gallium/drivers/freedreno/freedreno_pm4.h deleted file mode 100644 index a536f9c2b4..0000000000 --- a/src/gallium/drivers/freedreno/freedreno_pm4.h +++ /dev/null @@ -1,86 +0,0 @@ -/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ - -/* - * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Rob Clark <robclark@freedesktop.org> - */ - -#ifndef FREEDRENO_PM4_H_ -#define FREEDRENO_PM4_H_ - -#define CP_TYPE0_PKT (0 << 30) -#define CP_TYPE1_PKT (1 << 30) -#define CP_TYPE2_PKT (2 << 30) -#define CP_TYPE3_PKT (3 << 30) - - -#define CP_ME_INIT 0x48 -#define CP_NOP 0x10 -#define CP_INDIRECT_BUFFER 0x3f -#define CP_INDIRECT_BUFFER_PFD 0x37 -#define CP_WAIT_FOR_IDLE 0x26 -#define CP_WAIT_REG_MEM 0x3c -#define CP_WAIT_REG_EQ 0x52 -#define CP_WAT_REG_GTE 0x53 -#define CP_WAIT_UNTIL_READ 0x5c -#define CP_WAIT_IB_PFD_COMPLETE 0x5d -#define CP_REG_RMW 0x21 -#define CP_REG_TO_MEM 0x3e -#define CP_MEM_WRITE 0x3d -#define CP_MEM_WRITE_CNTR 0x4f -#define CP_COND_EXEC 0x44 -#define CP_COND_WRITE 0x45 -#define CP_EVENT_WRITE 0x46 -#define CP_EVENT_WRITE_SHD 0x58 -#define CP_EVENT_WRITE_CFL 0x59 -#define CP_EVENT_WRITE_ZPD 0x5b -#define CP_DRAW_INDX 0x22 -#define CP_DRAW_INDX_2 0x36 -#define CP_DRAW_INDX_BIN 0x34 -#define CP_DRAW_INDX_2_BIN 0x35 -#define CP_VIZ_QUERY 0x23 -#define CP_SET_STATE 0x25 -#define CP_SET_CONSTANT 0x2d -#define CP_IM_LOAD 0x27 -#define CP_IM_LOAD_IMMEDIATE 0x2b -#define CP_LOAD_CONSTANT_CONTEXT 0x2e -#define CP_INVALIDATE_STATE 0x3b -#define CP_SET_SHADER_BASES 0x4a -#define CP_SET_BIN_MASK 0x50 -#define CP_SET_BIN_SELECT 0x51 -#define CP_CONTEXT_UPDATE 0x5e -#define CP_INTERRUPT 0x40 -#define CP_IM_STORE 0x2c -#define CP_SET_BIN_BASE_OFFSET 0x4b /* for a20x */ -#define CP_SET_DRAW_INIT_FLAGS 0x4b /* for a22x */ -#define CP_SET_PROTECTED_MODE 0x5f -#define CP_LOAD_STATE 0x30 -#define CP_COND_INDIRECT_BUFFER_PFE 0x3a -#define CP_COND_INDIRECT_BUFFER_PFD 0x32 - - -#define CP_REG(reg) ((0x4 << 16) | ((reg) - 0x2000)) - - -#endif /* FREEDRENO_PM4_H_ */ diff --git a/src/gallium/drivers/freedreno/freedreno_program.c b/src/gallium/drivers/freedreno/freedreno_program.c index b7fec6d7dc..ffd257203e 100644 --- a/src/gallium/drivers/freedreno/freedreno_program.c +++ b/src/gallium/drivers/freedreno/freedreno_program.c @@ -301,13 +301,13 @@ fd_program_emit(struct fd_ringbuffer *ring, vs_export = max(1, prog->num_exports) - 1; OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_SQ_PROGRAM_CNTL)); - OUT_RING(ring, SQ_PROGRAM_CNTL_PS_EXPORT_MODE(POSITION_2_VECTORS_SPRITE) | - SQ_PROGRAM_CNTL_VS_RESOURCE | - SQ_PROGRAM_CNTL_PS_RESOURCE | - SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(vs_export) | - SQ_PROGRAM_CNTL_PS_REGS(fs_gprs) | - SQ_PROGRAM_CNTL_VS_REGS(vs_gprs)); + OUT_RING(ring, CP_REG(REG_A2XX_SQ_PROGRAM_CNTL)); + OUT_RING(ring, A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(POSITION_2_VECTORS_SPRITE) | + A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE | + A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE | + A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(vs_export) | + A2XX_SQ_PROGRAM_CNTL_PS_REGS(fs_gprs) | + A2XX_SQ_PROGRAM_CNTL_VS_REGS(vs_gprs)); } /* Creates shader: diff --git a/src/gallium/drivers/freedreno/freedreno_rasterizer.c b/src/gallium/drivers/freedreno/freedreno_rasterizer.c index 2d69133830..32618568c0 100644 --- a/src/gallium/drivers/freedreno/freedreno_rasterizer.c +++ b/src/gallium/drivers/freedreno/freedreno_rasterizer.c @@ -36,16 +36,16 @@ #include "freedreno_util.h" -static enum pa_su_sc_draw +static enum adreno_pa_su_sc_draw polygon_mode(unsigned mode) { switch (mode) { case PIPE_POLYGON_MODE_POINT: - return DRAW_POINTS; + return PC_DRAW_POINTS; case PIPE_POLYGON_MODE_LINE: - return DRAW_LINES; + return PC_DRAW_LINES; case PIPE_POLYGON_MODE_FILL: - return DRAW_TRIANGLES; + return PC_DRAW_TRIANGLES; default: DBG("invalid polygon mode: %u", mode); return 0; @@ -75,55 +75,55 @@ fd_rasterizer_state_create(struct pipe_context *pctx, so->base = *cso; so->pa_sc_line_stipple = cso->line_stipple_enable ? - PA_SC_LINE_STIPPLE_LINE_PATTERN(cso->line_stipple_pattern) | - PA_SC_LINE_STIPPLE_REPEAT_COUNT(cso->line_stipple_factor) : 0; + A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(cso->line_stipple_pattern) | + A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(cso->line_stipple_factor) : 0; so->pa_cl_clip_cntl = 0; // TODO so->pa_su_vtx_cntl = - PA_SU_VTX_CNTL_PIX_CENTER(cso->gl_rasterization_rules ? PIXCENTER_OGL : PIXCENTER_D3D) | - PA_SU_VTX_CNTL_QUANT_MODE(ONE_SIXTEENTH); + A2XX_PA_SU_VTX_CNTL_PIX_CENTER(cso->gl_rasterization_rules ? PIXCENTER_OGL : PIXCENTER_D3D) | + A2XX_PA_SU_VTX_CNTL_QUANT_MODE(ONE_SIXTEENTH); so->pa_su_point_size = - PA_SU_POINT_SIZE_HEIGHT(cso->point_size/2) | - PA_SU_POINT_SIZE_WIDTH(cso->point_size/2); + A2XX_PA_SU_POINT_SIZE_HEIGHT(cso->point_size/2) | + A2XX_PA_SU_POINT_SIZE_WIDTH(cso->point_size/2); so->pa_su_point_minmax = - PA_SU_POINT_MINMAX_MIN_SIZE(psize_min/2) | - PA_SU_POINT_MINMAX_MAX_SIZE(psize_max/2); + A2XX_PA_SU_POINT_MINMAX_MIN(psize_min/2) | + A2XX_PA_SU_POINT_MINMAX_MAX(psize_max/2); so->pa_su_line_cntl = - PA_SU_LINE_CNTL_WIDTH(cso->line_width/2); + A2XX_PA_SU_LINE_CNTL_WIDTH(cso->line_width/2); so->pa_su_sc_mode_cntl = - PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE | - PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(polygon_mode(cso->fill_front)) | - PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(polygon_mode(cso->fill_back)); + A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE | + A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(polygon_mode(cso->fill_front)) | + A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(polygon_mode(cso->fill_back)); if (cso->cull_face & PIPE_FACE_FRONT) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_CULL_FRONT; + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT; if (cso->cull_face & PIPE_FACE_BACK) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_CULL_BACK; + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK; if (!cso->flatshade_first) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST; + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST; if (!cso->front_ccw) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_FACE; + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_FACE; if (cso->line_stipple_enable) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE; + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE; if (cso->multisample) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_MSAA_ENABLE; + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE; if (cso->fill_front != PIPE_POLYGON_MODE_FILL || cso->fill_back != PIPE_POLYGON_MODE_FILL) - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DUALMODE); + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DUALMODE); else - so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DISABLED); + so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DISABLED); if (cso->offset_tri) so->pa_su_sc_mode_cntl |= - PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE | - PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE | - PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE; + A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE | + A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE | + A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE; return so; } diff --git a/src/gallium/drivers/freedreno/freedreno_state.c b/src/gallium/drivers/freedreno/freedreno_state.c index fcb04daabc..c8b5240afa 100644 --- a/src/gallium/drivers/freedreno/freedreno_state.c +++ b/src/gallium/drivers/freedreno/freedreno_state.c @@ -366,7 +366,7 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty) if (dirty & FD_DIRTY_SAMPLE_MASK) { OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); OUT_RING(ring, ctx->sample_mask); } @@ -374,44 +374,44 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty) struct pipe_stencil_ref *sr = &ctx->stencil_ref; OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); OUT_RING(ring, ctx->zsa->rb_depthcontrol); OUT_PKT3(ring, CP_SET_CONSTANT, 4); - OUT_RING(ring, CP_REG(REG_RB_STENCILREFMASK_BF)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF)); OUT_RING(ring, ctx->zsa->rb_stencilrefmask_bf | - RB_STENCILREFMASK_STENCILREF(sr->ref_value[1])); + A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1])); OUT_RING(ring, ctx->zsa->rb_stencilrefmask | - RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); + A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); OUT_RING(ring, ctx->zsa->rb_alpha_ref); } if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) { OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); OUT_RING(ring, ctx->rasterizer->pa_cl_clip_cntl); OUT_RING(ring, ctx->rasterizer->pa_su_sc_mode_cntl | - PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE); + A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE); OUT_PKT3(ring, CP_SET_CONSTANT, 5); - OUT_RING(ring, CP_REG(REG_PA_SU_POINT_SIZE)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE)); OUT_RING(ring, ctx->rasterizer->pa_su_point_size); OUT_RING(ring, ctx->rasterizer->pa_su_point_minmax); OUT_RING(ring, ctx->rasterizer->pa_su_line_cntl); OUT_RING(ring, ctx->rasterizer->pa_sc_line_stipple); OUT_PKT3(ring, CP_SET_CONSTANT, 6); - OUT_RING(ring, CP_REG(REG_PA_SU_VTX_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL)); OUT_RING(ring, ctx->rasterizer->pa_su_vtx_cntl); - OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */ - OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */ - OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */ - OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */ + OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */ + OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */ + OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */ + OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */ } if (dirty & FD_DIRTY_SCISSOR) { OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL)); OUT_RING(ring, xy2d(ctx->scissor.minx, /* PA_SC_WINDOW_SCISSOR_TL */ ctx->scissor.miny)); OUT_RING(ring, xy2d(ctx->scissor.maxx, /* PA_SC_WINDOW_SCISSOR_BR */ @@ -425,23 +425,23 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty) if (dirty & FD_DIRTY_VIEWPORT) { OUT_PKT3(ring, CP_SET_CONSTANT, 7); - OUT_RING(ring, CP_REG(REG_PA_CL_VPORT_XSCALE)); - OUT_RING(ring, f2d(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */ - OUT_RING(ring, f2d(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */ - OUT_RING(ring, f2d(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */ - OUT_RING(ring, f2d(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */ - OUT_RING(ring, f2d(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */ - OUT_RING(ring, f2d(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */ + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE)); + OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */ + OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */ + OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */ + OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */ + OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */ + OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */ OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL)); - OUT_RING(ring, PA_CL_VTE_CNTL_VTX_W0_FMT | - PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | - PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA | - PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA | - PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA); + OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL)); + OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT | + A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA | + A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA); } if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTX | FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX)) { @@ -460,17 +460,17 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty) if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) { OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLORCONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL)); OUT_RING(ring, ctx->zsa->rb_colorcontrol | ctx->blend->rb_colorcontrol); } if (dirty & FD_DIRTY_BLEND) { OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_BLEND_CONTROL)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); OUT_RING(ring, ctx->blend->rb_blendcontrol); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); OUT_RING(ring, ctx->blend->rb_colormask); } @@ -488,78 +488,78 @@ fd_state_emit_setup(struct pipe_context *pctx) struct fd_context *ctx = fd_context(pctx); struct fd_ringbuffer *ring = ctx->ring; - OUT_PKT0(ring, REG_TP0_CHICKEN, 1); + OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1); OUT_RING(ring, 0x00000002); OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); OUT_RING(ring, 0x00007fff); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_SQ_VS_CONST)); - OUT_RING(ring, SQ_VS_CONST_BASE(VS_CONST_BASE) | - SQ_VS_CONST_SIZE(0x100)); + OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST)); + OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) | + A2XX_SQ_VS_CONST_SIZE(0x100)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_SQ_PS_CONST)); - OUT_RING(ring, SQ_PS_CONST_BASE(PS_CONST_BASE) | - SQ_PS_CONST_SIZE(0xe0)); + OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST)); + OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) | + A2XX_SQ_PS_CONST_SIZE(0xe0)); OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_VGT_MAX_VTX_INDX)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX)); OUT_RING(ring, 0xffffffff); /* VGT_MAX_VTX_INDX */ OUT_RING(ring, 0x00000000); /* VGT_MIN_VTX_INDX */ OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); OUT_RING(ring, 0x00000000); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); OUT_RING(ring, 0x0000003b); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_SQ_CONTEXT_MISC)); - OUT_RING(ring, SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY)); + OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC)); + OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_SQ_INTERPOLATOR_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL)); OUT_RING(ring, 0xffffffff); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_AA_CONFIG)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG)); OUT_RING(ring, 0x00000000); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_LINE_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL)); OUT_RING(ring, 0x00000000); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET)); OUT_RING(ring, 0x00000000); // XXX we change this dynamically for draw/clear.. vs gmem<->mem.. OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_MODECONTROL)); - OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL)); + OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH)); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_SAMPLE_POS)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS)); OUT_RING(ring, 0x88888888); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_DEST_MASK)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK)); OUT_RING(ring, 0xffffffff); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COPY_DEST_INFO)); - OUT_RING(ring, RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) | - RB_COPY_DEST_INFO_WRITE_RED | - RB_COPY_DEST_INFO_WRITE_GREEN | - RB_COPY_DEST_INFO_WRITE_BLUE | - RB_COPY_DEST_INFO_WRITE_ALPHA); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO)); + OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) | + A2XX_RB_COPY_DEST_INFO_WRITE_RED | + A2XX_RB_COPY_DEST_INFO_WRITE_GREEN | + A2XX_RB_COPY_DEST_INFO_WRITE_BLUE | + A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA); OUT_PKT3(ring, CP_SET_CONSTANT, 3); - OUT_RING(ring, CP_REG(REG_SQ_WRAPPING_0)); + OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0)); OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_0 */ OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_1 */ @@ -572,7 +572,7 @@ fd_state_emit_setup(struct pipe_context *pctx) OUT_RING(ring, 0x5f601000); OUT_RING(ring, 0x00000001); - OUT_PKT0(ring, REG_SQ_INST_STORE_MANAGMENT, 1); + OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1); OUT_RING(ring, 0x00000180); OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); @@ -598,14 +598,14 @@ fd_state_emit_setup(struct pipe_context *pctx) OUT_RING(ring, 0x3e800000); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK)); - OUT_RING(ring, RB_COLOR_MASK_WRITE_RED | - RB_COLOR_MASK_WRITE_GREEN | - RB_COLOR_MASK_WRITE_BLUE | - RB_COLOR_MASK_WRITE_ALPHA); + OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); + OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED | + A2XX_RB_COLOR_MASK_WRITE_GREEN | + A2XX_RB_COLOR_MASK_WRITE_BLUE | + A2XX_RB_COLOR_MASK_WRITE_ALPHA); OUT_PKT3(ring, CP_SET_CONSTANT, 5); - OUT_RING(ring, CP_REG(REG_RB_BLEND_RED)); + OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED)); OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */ OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */ OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */ diff --git a/src/gallium/drivers/freedreno/freedreno_texture.c b/src/gallium/drivers/freedreno/freedreno_texture.c index 07bfbd3ce3..9584dd3f3e 100644 --- a/src/gallium/drivers/freedreno/freedreno_texture.c +++ b/src/gallium/drivers/freedreno/freedreno_texture.c @@ -87,13 +87,13 @@ fd_sampler_state_create(struct pipe_context *pctx, /* SQ_TEX0_PITCH() must be OR'd in later when we know the bound texture: */ so->tex0 = - SQ_TEX0_CLAMP_X(tex_clamp(cso->wrap_s)) | - SQ_TEX0_CLAMP_Y(tex_clamp(cso->wrap_t)) | - SQ_TEX0_CLAMP_Z(tex_clamp(cso->wrap_r)); + A2XX_SQ_TEX_0_CLAMP_X(tex_clamp(cso->wrap_s)) | + A2XX_SQ_TEX_0_CLAMP_Y(tex_clamp(cso->wrap_t)) | + A2XX_SQ_TEX_0_CLAMP_Z(tex_clamp(cso->wrap_r)); so->tex3 = - SQ_TEX3_XY_MAG_FILTER(tex_filter(cso->mag_img_filter)) | - SQ_TEX3_XY_MIN_FILTER(tex_filter(cso->min_img_filter)); + A2XX_SQ_TEX_3_XY_MAG_FILTER(tex_filter(cso->mag_img_filter)) | + A2XX_SQ_TEX_3_XY_MIN_FILTER(tex_filter(cso->min_img_filter)); so->tex4 = 0x00000000; /* ??? */ so->tex5 = 0x00000200; /* ??? */ @@ -126,10 +126,10 @@ fd_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc, so->tex_resource = rsc; so->fmt = fd_pipe2surface(cso->format); - so->tex0 = SQ_TEX0_PITCH(rsc->pitch); + so->tex0 = A2XX_SQ_TEX_0_PITCH(rsc->pitch); so->tex2 = - SQ_TEX2_HEIGHT(prsc->height0) | - SQ_TEX2_WIDTH(prsc->width0); + A2XX_SQ_TEX_2_HEIGHT(prsc->height0 - 1) | + A2XX_SQ_TEX_2_WIDTH(prsc->width0 - 1); so->tex3 = fd_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g, cso->swizzle_b, cso->swizzle_a); diff --git a/src/gallium/drivers/freedreno/freedreno_texture.h b/src/gallium/drivers/freedreno/freedreno_texture.h index 32bdb031ae..94eb755ffb 100644 --- a/src/gallium/drivers/freedreno/freedreno_texture.h +++ b/src/gallium/drivers/freedreno/freedreno_texture.h @@ -43,7 +43,7 @@ struct fd_sampler_stateobj { struct fd_pipe_sampler_view { struct pipe_sampler_view base; struct fd_resource *tex_resource; - enum sq_surfaceformat fmt; + enum a2xx_sq_surfaceformat fmt; uint32_t tex0, tex2, tex3; }; diff --git a/src/gallium/drivers/freedreno/freedreno_util.c b/src/gallium/drivers/freedreno/freedreno_util.c index 3bc3e798e3..7d458d594c 100644 --- a/src/gallium/drivers/freedreno/freedreno_util.c +++ b/src/gallium/drivers/freedreno/freedreno_util.c @@ -31,7 +31,7 @@ #include "freedreno_util.h" -enum sq_surfaceformat +enum a2xx_sq_surfaceformat fd_pipe2surface(enum pipe_format format) { switch (format) { @@ -194,7 +194,7 @@ fd_pipe2surface(enum pipe_format format) } } -enum rb_colorformatx +enum a2xx_colorformatx fd_pipe2color(enum pipe_format format) { switch (format) { @@ -289,7 +289,7 @@ fd_pipe2color(enum pipe_format format) } } -enum rb_depth_format +enum a2xx_rb_depth_format fd_pipe2depth(enum pipe_format format) { switch (format) { @@ -344,8 +344,8 @@ fd_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g, PIPE_SWIZZLE_ONE, PIPE_SWIZZLE_ONE, }; - return SQ_TEX3_SWIZ_X(tex_swiz(swiz[desc->swizzle[0]])) | - SQ_TEX3_SWIZ_Y(tex_swiz(swiz[desc->swizzle[1]])) | - SQ_TEX3_SWIZ_Z(tex_swiz(swiz[desc->swizzle[2]])) | - SQ_TEX3_SWIZ_W(tex_swiz(swiz[desc->swizzle[3]])); + return A2XX_SQ_TEX_3_SWIZ_X(tex_swiz(swiz[desc->swizzle[0]])) | + A2XX_SQ_TEX_3_SWIZ_Y(tex_swiz(swiz[desc->swizzle[1]])) | + A2XX_SQ_TEX_3_SWIZ_Z(tex_swiz(swiz[desc->swizzle[2]])) | + A2XX_SQ_TEX_3_SWIZ_W(tex_swiz(swiz[desc->swizzle[3]])); } diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h index fb1e392bc1..45f5d2fc48 100644 --- a/src/gallium/drivers/freedreno/freedreno_util.h +++ b/src/gallium/drivers/freedreno/freedreno_util.h @@ -34,13 +34,15 @@ #include "pipe/p_format.h" #include "util/u_debug.h" +#include "util/u_math.h" -#include "freedreno_pm4.h" -#include "freedreno_a2xx_reg.h" +#include "adreno_common.xml.h" +#include "adreno_pm4.xml.h" +#include "a2xx.xml.h" -enum sq_surfaceformat fd_pipe2surface(enum pipe_format format); -enum rb_colorformatx fd_pipe2color(enum pipe_format format); -enum rb_depth_format fd_pipe2depth(enum pipe_format format); +enum a2xx_sq_surfaceformat fd_pipe2surface(enum pipe_format format); +enum a2xx_colorformatx fd_pipe2color(enum pipe_format format); +enum a2xx_rb_depth_format fd_pipe2depth(enum pipe_format format); enum pc_di_index_size fd_pipe2index(enum pipe_format format); uint32_t fd_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a); @@ -63,6 +65,26 @@ extern int fd_mesa_debug; #define max(a, b) (((a) > (b)) ? (a) : (b)) +#define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000)))) + +static inline uint32_t DRAW(enum pc_di_primtype prim_type, + enum pc_di_src_sel source_select, enum pc_di_index_size index_size, + enum pc_di_vis_cull_mode vis_cull_mode) +{ + return (prim_type << 0) | + (source_select << 6) | + ((index_size & 1) << 11) | + ((index_size >> 1) << 13) | + (vis_cull_mode << 9) | + (1 << 14); +} + +/* convert x,y to dword */ +static inline uint32_t xy2d(uint16_t x, uint16_t y) +{ + return ((y & 0x3fff) << 16) | (x & 0x3fff); +} + #define LOG_DWORDS 0 diff --git a/src/gallium/drivers/freedreno/freedreno_vbo.c b/src/gallium/drivers/freedreno/freedreno_vbo.c index e992b8cf45..763171dc24 100644 --- a/src/gallium/drivers/freedreno/freedreno_vbo.c +++ b/src/gallium/drivers/freedreno/freedreno_vbo.c @@ -198,15 +198,15 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) emit_vertexbufs(ctx, info->count); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); OUT_RING(ring, info->start); OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL)); + OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); OUT_RING(ring, 0x0000003b); - OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1); - OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE); + OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1); + OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE); OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); OUT_RING(ring, 0x0000000); @@ -222,7 +222,7 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) } OUT_PKT3(ring, CP_SET_CONSTANT, 2); - OUT_RING(ring, CP_REG(REG_2010)); + OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010)); OUT_RING(ring, 0x00000000); emit_cacheflush(ring); diff --git a/src/gallium/drivers/freedreno/freedreno_zsa.c b/src/gallium/drivers/freedreno/freedreno_zsa.c index e8daa37a35..2ca9977027 100644 --- a/src/gallium/drivers/freedreno/freedreno_zsa.c +++ b/src/gallium/drivers/freedreno/freedreno_zsa.c @@ -35,7 +35,7 @@ #include "freedreno_context.h" #include "freedreno_util.h" -static enum rb_stencil_op +static enum adreno_stencil_op stencil_op(unsigned op) { switch (op) { @@ -74,48 +74,48 @@ fd_zsa_state_create(struct pipe_context *pctx, so->base = *cso; so->rb_depthcontrol |= - RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */ + A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */ if (cso->depth.enabled) - so->rb_depthcontrol |= RB_DEPTHCONTROL_Z_ENABLE; + so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_ENABLE; if (cso->depth.writemask) - so->rb_depthcontrol |= RB_DEPTHCONTROL_Z_WRITE_ENABLE; + so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE; if (cso->stencil[0].enabled) { const struct pipe_stencil_state *s = &cso->stencil[0]; so->rb_depthcontrol |= - RB_DEPTHCONTROL_STENCIL_ENABLE | - RB_DEPTHCONTROL_STENCILFUNC(s->func) | /* maps 1:1 */ - RB_DEPTHCONTROL_STENCILFAIL(stencil_op(s->fail_op)) | - RB_DEPTHCONTROL_STENCILZPASS(stencil_op(s->zpass_op)) | - RB_DEPTHCONTROL_STENCILZFAIL(stencil_op(s->zfail_op)); + A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE | + A2XX_RB_DEPTHCONTROL_STENCILFUNC(s->func) | /* maps 1:1 */ + A2XX_RB_DEPTHCONTROL_STENCILFAIL(stencil_op(s->fail_op)) | + A2XX_RB_DEPTHCONTROL_STENCILZPASS(stencil_op(s->zpass_op)) | + A2XX_RB_DEPTHCONTROL_STENCILZFAIL(stencil_op(s->zfail_op)); so->rb_stencilrefmask |= 0xff000000 | /* ??? */ - RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) | - RB_STENCILREFMASK_STENCILMASK(s->valuemask); + A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) | + A2XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask); if (cso->stencil[1].enabled) { const struct pipe_stencil_state *bs = &cso->stencil[1]; so->rb_depthcontrol |= - RB_DEPTHCONTROL_BACKFACE_ENABLE | - RB_DEPTHCONTROL_STENCILFUNC_BF(bs->func) | /* maps 1:1 */ - RB_DEPTHCONTROL_STENCILFAIL_BF(stencil_op(bs->fail_op)) | - RB_DEPTHCONTROL_STENCILZPASS_BF(stencil_op(bs->zpass_op)) | - RB_DEPTHCONTROL_STENCILZFAIL_BF(stencil_op(bs->zfail_op)); + A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE | + A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(bs->func) | /* maps 1:1 */ + A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(stencil_op(bs->fail_op)) | + A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(stencil_op(bs->zpass_op)) | + A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(stencil_op(bs->zfail_op)); so->rb_stencilrefmask_bf |= 0xff000000 | /* ??? */ - RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) | - RB_STENCILREFMASK_STENCILMASK(bs->valuemask); + A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) | + A2XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask); } } if (cso->alpha.enabled) { so->rb_colorcontrol = - RB_COLORCONTROL_ALPHA_FUNC(cso->alpha.func) | - RB_COLORCONTROL_ALPHA_TEST_ENABLE; - so->rb_alpha_ref = f2d(cso->alpha.ref_value); + A2XX_RB_COLORCONTROL_ALPHA_FUNC(cso->alpha.func) | + A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE; + so->rb_alpha_ref = fui(cso->alpha.ref_value); } return so; diff --git a/src/gallium/drivers/freedreno/freedreno_zsa.h b/src/gallium/drivers/freedreno/freedreno_zsa.h index d1112f1572..6f5c5f07e9 100644 --- a/src/gallium/drivers/freedreno/freedreno_zsa.h +++ b/src/gallium/drivers/freedreno/freedreno_zsa.h @@ -48,13 +48,12 @@ void fd_zsa_init(struct pipe_context *pctx); static inline bool fd_depth_enabled(struct fd_zsa_stateobj *zsa) { - return !!(zsa->rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE); + return zsa->base.depth.enabled; } static inline bool fd_stencil_enabled(struct fd_zsa_stateobj *zsa) { - //RB_DEPTHCONTROL_STENCIL_ENABLE - return !!(zsa->rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE); + return zsa->base.stencil[0].enabled; } #endif /* FREEDRENO_ZSA_H_ */ diff --git a/src/gallium/drivers/freedreno/instr.h b/src/gallium/drivers/freedreno/instr-a2xx.h index fd192342c9..cecc7a98b8 100644 --- a/src/gallium/drivers/freedreno/instr.h +++ b/src/gallium/drivers/freedreno/instr-a2xx.h @@ -21,13 +21,16 @@ * SOFTWARE. */ -#ifndef INSTR_H_ -#define INSTR_H_ - -#include "freedreno_a2xx_reg.h" +#ifndef INSTR_A2XX_H_ +#define INSTR_A2XX_H_ #define PACKED __attribute__((__packed__)) +#include "util/u_math.h" +#include "adreno_common.xml.h" +#include "a2xx.xml.h" + + /* * ALU instructions: */ @@ -301,7 +304,7 @@ typedef enum { SAMPLE_CENTER = 1, } instr_sample_loc_t; -typedef enum sq_surfaceformat instr_surf_fmt_t; +typedef enum a2xx_sq_surfaceformat instr_surf_fmt_t; typedef struct PACKED { /* dword0: */ diff --git a/src/gallium/drivers/freedreno/ir.c b/src/gallium/drivers/freedreno/ir.c index cbc1230fa7..4c605de946 100644 --- a/src/gallium/drivers/freedreno/ir.c +++ b/src/gallium/drivers/freedreno/ir.c @@ -29,7 +29,7 @@ #include <assert.h> #include "freedreno_util.h" -#include "instr.h" +#include "instr-a2xx.h" #define DEBUG_MSG(f, ...) do { if (0) DBG(f, ##__VA_ARGS__); } while (0) #define WARN_MSG(f, ...) DBG("WARN: "f, ##__VA_ARGS__) diff --git a/src/gallium/drivers/freedreno/ir.h b/src/gallium/drivers/freedreno/ir.h index e8025446b3..9e4722c9c9 100644 --- a/src/gallium/drivers/freedreno/ir.h +++ b/src/gallium/drivers/freedreno/ir.h @@ -27,7 +27,7 @@ #include <stdint.h> #include <stdbool.h> -#include "instr.h" +#include "instr-a2xx.h" /* low level intermediate representation of an adreno shader program */ @@ -76,7 +76,7 @@ struct ir_instruction { unsigned const_idx; /* maybe vertex fetch specific: */ unsigned const_idx_sel; - enum sq_surfaceformat fmt; + enum a2xx_sq_surfaceformat fmt; bool is_signed : 1; bool is_normalized : 1; uint32_t stride; @@ -219,7 +219,7 @@ ir_instr_create_alu(struct ir_cf *cf, instr_vector_opc_t vop, instr_scalar_opc_t } static inline struct ir_instruction * ir_instr_create_vtx_fetch(struct ir_cf *cf, int ci, int cis, - enum sq_surfaceformat fmt, bool is_signed, int stride) + enum a2xx_sq_surfaceformat fmt, bool is_signed, int stride) { struct ir_instruction *instr = instr = ir_instr_create(cf, IR_FETCH); instr->fetch.opc = VTX_FETCH; |