cherry-ignore: Ignore candidates for the 9.1 branch.

1 files changed, 77 insertions, 0 deletions

diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 80156fcd7a..3bfea20e64 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -39,3 +39,80 @@ b4db34cc4c047427a21efb9bde03d7e125f70e55 glsl: Rename uniform_field_visitor to p
 83e4407f443fb6baeccf9aefee291c82adcaa58b radeonsi: add support for Oland chips
 af0af75881ea99452086afd6907780de77af6e96 radeonsi: default PA_SC_RASTER_CONFIG to 0
 4161d70bba567e6e73d5e9e993a74d81930d0e72 radeonsi: add Oland pci ids
+29aef6cce8114410ef3e82e46de6938d412a5fde mesa: Put extern "C" guards in renderbuffer.h.
+0b3bebbaacf42ae07f712b5693f7b00fad3ff35e i965: Implement CopyTexSubImage2D via BLORP (and use it by default).
+c0554141a9b831b4e614747104dcbbe0fe489b9d i965/blorp: Support overriding destination alpha to 1.0.
+7d467f3c1583c94daffb58610d12eece1fddd9c2 i965/blorp: Support blits between ARGB and XRGB formats.
+496928a442cec980b534bc5da2523b3632b21b61 CopyTexImage: Don't check sRGB vs LINEAR for desktop GL
+8cabe26f5dc4c66ae59649cfd7b25f761cda250b i965: Use derived state for Haswell's 3DSTATE_VF packet.
+c840270ebe588a62f22cae34c02ceeb95345f1f4 radeonsi: Handle TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
+dd599188d2868838541859a76800a8420958d358 i965: Fix leak in blorp CopyTexSubImage2D
+f9adf7987601197641cd0d851e47b45c5c416f00 radeonsi: properly implement S8Z24 depth-stencil format
+8356962853727136f3316ed227fb7bfe98e2f2bd radeonsi: Use stencil surface level information for stencil texturing
+9c1107b3e1a4f9f932728d53a8a7961ac948521e radeonsi: Fix PIPE_FORMAT_X32_S8X24_UINT sampler hardware format
+5da967aff5adb3e27954488206fb885ea1ede0fd draw: fix non-perspective interpolation in interp()
+49bdebad3857bb9ebac53f593d08f0057f5a20d3 i965/fs: Fix copy propagation with smearing.
+aebd3f46e305829ebfcc817cafa8592edc2f80ab i965/fs: Delay setup of uniform loads until after pre-regalloc scheduling.
+c2a6e529c3bc9e62ad93beb1f5ae427dbbba8a38 i965/fs: Only do CSE when the dst types match.
+c4faab63c45aad579ef324fcc076c88a7cebbef6 radeonsi: use u_box_origin_2d helper function
+a84c4edeede12a1275a37a61408f578481bd4355 radeonsi: add assertions to prevent creation of invalid surfaces
+72f4490b551d118c726a516359b804ae7425333e radeonsi: implement 3D transfers
+95bced59293bc3dffad955b714c142455aa05aa8 radeonsi: Fix blending using destination alpha factor but non-alpha destination
+8b586322e71d5ad0ce95d0fbcbfeb4df13f65040 mesa: Don't install glEvalMesh in the beginend dispatch table
+18272c9b1b530ad6d2091b647c062793f94b5351 radeonsi: Fix up and enable flat shading.
+954bc4ac34b821cdc4ecb3ea8e394a66bcc2dda0 radeonsi: Fix w component of TGSI_SEMANTIC_POSITION fragment shader inputs.
+c1f2c3a80fa555287fd756832a05587fab8b79bd llvmpipe/build: add DLOPEN_LIBS and PTHREAD_LIBS to the lp_test_* targets
+c1eb585f3d62670782d9cc73637b7e3bcab46d66 targets/xa-vmwgfx: Force c++ linker to fix undefined symbols
+aac81387447152b5bda99150414d636a003adc56 r600g: fix random corruption with CP DMA in TF2
+7ae6864f0dbec33270c83c4181a8182139662d0f i965: Enable OpenGL ES 3.0 on Sandy Bridge
+7ebf83f109db9dde89830d5844107c936cf42e4d r600g: add PS_PARTIAL_FLUSH flag
+8442b67f5f3aedbfdb4446164dd09d4eaeda4888 r600g: r6xx deadlock workaround (v6)
+8b5acad0e985215b46fc1cfc8ad87c8771a11a3a r600g: fixup PS_PARTIAL_FLUSH flag handling for cayman
+68a147e9a9e8f171d9aacdc7d78d2107009c4741 egl: Allow 24-bit visuals for 32-bit RGBA8888 configs
+89e2898e9ecfcf93c337b99542b06892a8e30cbe r600g: always map uninitialized buffer range as unsynchronized
+44f37261fc34763003314245a811cfd21ce6fc87 gallium/util: add helper code for 1D integer range
+c77917d35fdf64d9f194fbecc4748213621eefc8 r600g: pad the DMA CS to a multiple of 8 dwords
+9dd18f43a4db73be73dfbf2e9950ae4dfaf6322e r600g: use async DMA with a non-zero src offset
+e5a250fdf9487bae8d88fd7362ddb86e35978f1e r600g: flush and invalidate htile cache when appropriate
+35189d768bf80fdedbb6e70f49215cc8b734f343 configure.ac: Don't check for X11 unconditionally.
+523b07e32060f11cee6bb2c8a9b9477c85fe1e9a configure.ac: Remove stale comment about --x-* arguments.
+1323772543083dec23baf5a50222bdfc88ff6c3a i965/fs: Fix broken rendering in large shaders with UBO loads.
+4dca602521c51a4cb03855bda9c22b5ccc4829c7 radeonsi: Fix off-by-one for maximum vertex element index in some cases
+a2d08f170ab0d4ac7ba8d4c74db3a410f6cafa19 i965: Add definitions for gen7+ data cache messages.
+f27a220cadd1326e6293a2c3fb945b7765a85da4 i965: Fix INTEL_DEBUG=shader_time for Haswell.
+125b34cffbd377a3b27967b37767692796542250 i965: Specialize SURFACE_STATE creation for shader time.
+91df4d746bd50b328b9f4b55126c95c046087a4d i965: Make INTEL_DEBUG=shader_time use the RAW surface format.
+f70c3853513637fa6ed38e75f73d472a9fa61213 gallium/build: Fix visibility CFLAGS in automake
+4409758a046a47b09cdd339f97afd22107c68f0c r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
+36320bfa54b758b34df732250365b91ff1ab858c radeon/llvm: Link against libgallium.la to fix an undefined symbol
+182895c4e691e9e783278f1448772e855ade7b33 gallium/egl: fix out-of-tree build
+7c3d8301afed46cf932bf23431085de490a1f83a radeon/llvm: Do not link against libgallium when building statically.
+49c1fc7044eaaa5c2dca05ff4a709be8e3636871 r600g: don't emit SQ_DYN_GPR_RESOURCE_LIMIT_1 on cayman
+d86efc075ed84a8c45bfb71cee56dcd18858f727 i965: Don't use texture swizzling to force alpha to 1.0 if unnecessary.
+032e5548b3d4b5efa52359218725cb8e31b622ad radeonsi: Emit pixel shader state even when only the vertex shader changed
+12dc4be8a66c92ce04637abc54ed85ac7ff9aa13 mesa: Implement TEXTURE_IMMUTABLE_LEVELS for ES 3.0.
+92855bcc95207252045314b658eb10c6305020bc r600g: Use virtual address for PIPE_QUERY_SO* in r600_emit_query_end
+dbf94d105a48b7aafb2c8cf64d8b4392d87efea1 glsl: Replace constant-index vector array accesses with swizzles
+0967c362bf378b7415c30ca6d9523d3b2a3a7f5d i965: Fix an inconsistency inb the VUE map with gl_ClipVertex on gen4/5.
+bc0cc2944ff13549df8276b856acc79254c5db07 ACTIVE_UNIFORM_MAX_LENGTH should include 3 extra characters for arrays.
+59e858861caad2649f4c282eb277a7fc6202ab65 i965/fs: Remove creation of a MOV instruction that's never used.
+8c694dfe6478ce9355c866ae70db45e49e499de3 i965/fs: Move varying uniform offset compuation into the helper func.
+2f41a601455e6e0366e28b6b84871842cb4bd341 i965: Make the constant surface interface take a normal byte size.
+740350c982bd2735b9eb9063c2b91856b6f1ad31 i965: Make the fragment shader pull constants index by dwords, not vec4s.
+bc0e1591f64b8b3f2693fceaaa8bba9198e26171 i965/fs: Avoid inappropriate optimization with regs_written > 1.
+dca5fc14358a8b267b3854c39c976a822885898f i965/fs: Improve performance of varying-index uniform loads on IVB.
+9f43b8492818bab47ef9cc489b91c2618446a3e9 i965/fs: Do CSE on gen7's varying-index pull constant loads.
+8edc7cbe645b650bcb4e7fa190c9322c289ec177 i965/fs: Clean up the setup of gen4 simd16 message destinations.
+3cf69b228404791cf15231321b6a18b5701be0a6 i965/fs: Bake regs_written into the IR instead of recomputing it later.
+70b27e0e4b5d15e575ea477d63c0f6cb19d645c2 i965/fs: Use LD messages for pre-gen7 varying-index uniform loads
+62501c3af85089b423218a41a2e2433ac849c2d3 i965/fs: Allow CSE on pre-gen7 varying-index uniform loads
+c6efb4870b7c735e4dc1907dfdfd1be3159dc451 radeonsi: Handle arbitrary 2-byte formats in resource_copy_region
+ff01e0db0e45b47b6012e7c28f331a4a8e518df9 radeonsi: add more cases for copying unsupported formats to resource_copy_region
+aa391976dfa12479185d9eeed1f2a0b4dce6c49b intel: Allocate hiz in intel_renderbuffer_move_to_temp()
+7862bde8af1f63cfe921977ecb112f88885c92a9 glsl/linker: fix varying packing for non-flat integer varyings.
+5306af211372c10bb05a3f8d09e6986a76677524 glsl/linker: Reduce scope of non-flat integer varying fix.
+62a18da34153dd0e167a2944fc00812c1471c0fb i965/gen7: Skip resetting SOL offsets at batch start with HW contexts.
+007a88ed24e783d38839e69ae07aa19ceabb6c93 i965/gen6: Reduce updates of transform feedback offsets with HW contexts.
+3998f8c6b5da1a223926249755e54d8f701f81ab egl/x11: Fix initialisation of swap_interval
+cb12bf7606116e473bf19aee84582b4cee7f895d st/mesa: fix UBO offsets.
+4c3ed795662974a1c2ad2326fc74bef608a34f31 r600g: Workaround for a harware bug with nested loops on Cayman