diff options
| author | Egbert Eich <eich@suse.de> | 2005-01-21 12:17:19 +0000 |
|---|---|---|
| committer | Egbert Eich <eich@suse.de> | 2005-01-21 12:17:19 +0000 |
| commit | 447cb9ac1433d9dee68e8f1fc9171a0ef3cc0512 (patch) | |
| tree | a75468fc160fdf58f50026229b4ff3080b689eb6 /src/ct_driver.c | |
| parent | c832080b84cc58826a39cf9d18fa2e83f5f8c9df (diff) | |
Comparing the C&T driver code with the original BE support patch by RobXORG-6_8_99_3XORG-6_8_99_2XORG-6_8_99_1
Taylor and Jean-Laurent Gazelle it looks like the handling of the
availability of a dual endian fb aperture and the byte swapping control
bit appears to be slightly wrong. This patch attempts to fix it
(Bugzilla #2346).
Diffstat (limited to 'src/ct_driver.c')
| -rw-r--r-- | src/ct_driver.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/ct_driver.c b/src/ct_driver.c index aa4006a..2b852df 100644 --- a/src/ct_driver.c +++ b/src/ct_driver.c @@ -1532,7 +1532,7 @@ chipsPreInitHiQV(ScrnInfoPtr pScrn, int flags) if (cPtr->pEnt->location.type == BUS_PCI) { /* Tack on 0x800000 to access the big-endian aperture? */ #if X_BYTE_ORDER == X_BIG_ENDIAN - if (!BE_SWAP_APRETURE(pScrn,cPtr)) + if (BE_SWAP_APRETURE(pScrn,cPtr)) cPtr->FbAddress = (cPtr->PciInfo->memBase[0] & 0xff800000) + 0x800000L; else #endif @@ -1849,9 +1849,9 @@ chipsPreInitHiQV(ScrnInfoPtr pScrn, int flags) } #if X_BYTE_ORDER == X_BIG_ENDIAN - if (cPtr->pEnt->chipset == CHIPS_CT69030 && (cPtr->readXR(cPtr, 0x71) & 0x2)) + if (cPtr->pEnt->chipset == CHIPS_CT69030 && ((cPtr->readXR(cPtr, 0x71) & 0x2)) == 0) /* CFG9: Pipeline variable ByteSwap mapping */ cPtr->dualEndianAp = TRUE; - else + else /* CFG9: Pipeline A/B mapping */ cPtr->dualEndianAp = FALSE; #endif @@ -5506,8 +5506,7 @@ chipsModeInitHiQV(ScrnInfoPtr pScrn, DisplayModePtr mode) #if X_BYTE_ORDER == X_BIG_ENDIAN ChipsNew->XR[0x0A] &= 0xCF; if (pScrn->bitsPerPixel == 16) { - ChipsNew->XR[0x0A] &= 0xCF; - if (cPtr->dualEndianAp) + if (!cPtr->dualEndianAp) ChipsNew->XR[0x0A] |= 0x10; } #endif |