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Until now the list of error injectable functions was determined at
runtime by reading debugfs. This was convenient as a new function
added in KMD would automatically be tested in a separate test. This
worked well as long as all error injectable functions were meant to
only be tested during probe time, which is a specific scenario. As we
want to use error injection in other situations, we will not be able
to automatically determine if this is a case for probe time, so we
need to make it explicit.
v2: Order function names alphabetically (Rodrigo Vivi)
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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The EDID for the 1920x1200 at 59.950 Hz mode is already included.
It will be swapped with the EDID for the 2560x1600 at 59.972 Hz mode
to ensure full coverage of all EDIDs.
v2: Update subject (Swati)
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
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of edid
This test iterates on all the available edids of HDMI.
Due to CI test timeut limitation, we are reducing the
number of edids to execute to avoid result as timeout.
Using extended flag to achieve this. The test will execute
only 25 edids when this flag is not used as CI doesnt uses
this flag.
In local execution to execute on all edids, we have to give
this flag at the runtime.
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Reviewed-by: Kunal Joshi <kunal1.joshi@intel.com>
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Having some logs for test failures and skips would
make debugging much easier.
v2: Remove CRTC log for fail/skip (Bhanu)
v3: Add check for connector connection
v4: Remove check for connector connection (Bhanu)
v5: Rebasing and sending other version
v6: Remove igt_info for connector support (Bhanu)
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Reviewed-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
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Debugging would be easier if we had logs available for
test failures and skips. This patch rephrases the skip
message for better understanding.
v2:
- Remove .c extension in the filename (Swati)
v3:
- Add version history (Swati)
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Reviewed-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
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Synch with kernel commit that uses common PCI ID macros:
3c1d5ced18db ("drm/i915/gsc: ARL-H and ARL-U need a newer GSC FW.")
Refactor lib to use new macro definitions and pciids.h header file.
Signed-off-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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Add test which validates exec_queue_placement uAPI. It requires
ccs_mode, which is present only on platforms with multiple ccs engines.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Acked-by: Christoph Manszewski <christoph.manszewski@intel.com>
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Add definition and support for DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE_PLACEMENTS,
which is sent during exec_queue creation/discovery.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
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addition
Exec queue placement event has been added in logical order, due to that
there is a shift in event numbering. Sync uapi to match kernel changes.
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
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This reverts commit 4f79f059766c ("tests/intel/xe_drm_fdinfo: Half the
execution time") and goes in the opposite direction, doubling it.
Although in some machines we pass consistently, others like LNL
show sporadic failures.
Even after changes in the kernel to improve it, it still shows those
failures. Also, the failures can be much more frequent by stressing all
the CPUs. Raise the period to reduce the error introduced due to
additional scheduling delays. This shows a good improvement on LNL that
doesn't fail anymore without CPU load and fails once every ~200
iterations with 100% CPU load (vs once every ~3 iterations).
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Link: https://lore.kernel.org/r/20241108054350.3484532-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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In INVALIDATE cases the test purposely remap the data buffer to a
different physical location in the midle of execution to exercise the
page fault handling flow. After the remapping we lose access to the old
physical location, and that would cause a problem for comparing ufence
value at the end of the execution. To fix this the exec_sync data needs
to be separated from the batch buffer for instructions, and during the
execution we don't remap the exec_sync data.
v2: Separate only exec_sync. Keep data field together with the batch
buffer (Matt Roper)
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
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In test_compute_mode, there is an one second sleep waiting for all the
submissions to complete, but a hardcode wait is not reliable for test
that could have thousands of xe_execs submissions. Instead we should
wait for the ufence to make sure the GPU is inactive before unbinding
the BO.
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
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The for-loop for REBIND case accidentally wait twice for the execs of
0x20*n interations. Copyi paste the code from INVALIDATE case which is
correct.
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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In INVALIDATE cases the test purposely remap the data buffer to a
different physical location in the midle of execution to exercise the
page fault handling flow. After the remapping we lose access to the old
physical location, and that would cause a problem for comparing ufence
value at the end of the execution. To fix this the exec_sync data needs
to be separated from the batch buffer for instructions, and during the
execution we don't remap the exec_sync data.
v2: Separate only exec_sync. Keep data field together with the batch
buffer (Matt Roper)
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
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Add crc testing for suspend/resume while compressed framebuffer is on screen.
Test use only XR24 and P016 formats for testing. After resume is checked
framebuffer did stay compressed with exception on bmg.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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Check sysfs reset mask before enabling certain subtests.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
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Check sysfs reset mask before enabling certain subtests.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
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Replace the original ASIC filter with the sysfs reset mask. Check
if a specific reset type is supported before running the subtest.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
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GPU reset types include full adapter reset, soft reset,
queue reset and pipeline reset. It is possible to check
whether a specific reset is supported via the sysfs interface
and run special cases for testing.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
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The abm tests only need to run on one output per pipe, instead of all
pipes. Additionally, fixed the monotonic_abm not changing the abm level.
v2: Made change for more tests
Signed-off-by: George Zhang <george.zhang@amd.com>
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
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with tile4
On Intel display version 20 Tile4 no longer can be used with horizontal
flip.
Bspec: 69853
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
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move plane rotation requirement block into helper function.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
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Because drm schedule no longer uses the parameter ring_id for scheduling.
Instead, it selects the ring with less load to schedule the job. See the kernel
function drm_sched_job_arm. Therefore, in order to verify each available ring on
a certain IP, it can use the schedule debugfs interface.
v2: fix the gfx high priority context issue
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
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This script uses objcopy in order to dump a section. Objcopy is meant
for copying and expects a second argument. Failing that, it uses the
input file as output. Even though there's no intented change to the
file, this operation still re-writes the file completely.
In most cases, this re-writes the file as it was before. But in
cross-compilation cases, the "objcopy" program in the PATH used here
might be different than the toolchain which generated the ELF file.
In all cases, this causes a racy re-build of the .a, and in the worst
case, the objcopy re-written .o and .a files are actually incompatible
with the cross-linker used downstream in the ninja build causing failure
to find all symbols from the libs passed to this script.
```
../lib/intel_batchbuffer.c:763: undefined reference to
`gen8_gpgpu_fillfunc'
../lib/intel_batchbuffer.c:762: undefined reference to
`xehp_gpgpu_fillfunc'
[...]
```
The intent of the command was just to extract info from the LIBS, not
modify them. Using /dev/null as output file ensures the input files will
not be modified.
Signed-off-by: Jeff Dagenais <jeff.dagenais@gmail.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
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igt_sysfs_set() already supports setting a 0-length value since commit
1c0b492a0b5c ("lib/igt_sysfs: make sure to write empty strings").
Remove workaround in kunit_set_filtering() and simplify.
Reviewed-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Link: https://lore.kernel.org/r/20241031003142.863437-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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So it can be used directly by tests and other libs.
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://lore.kernel.org/r/20241023050502.3049664-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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Setting the power/control to "auto" is not needed and will fail if
kernel is configured without CONFIG_PM. Just stop setting it and it
should still work as before.
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://lore.kernel.org/r/20241030234838.857880-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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This commit addresses a bug in the buffer object (BO) mapping to the CPU by adding
the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag.
After an AMDGPU PCI unplug, we now handle expected failures in the DRM_AMDGPU_GEM_VA
ioctl call.
Additionally, amd_pci_unplug.c has been reformatted to comply with kernel code
formatting standards.
Cc: Jesse Zhang <jesse.zhang@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
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[Why]
New panel replay driver behavior skip some atomic commits before
enable the panel replay.
This is because a kms client needs to submit fb updates via kms
in order for amdgpu to flush updates to the panel.
If a client updates the fb without going through kms (by directly
blitting to it, for example), then any panel self-refresh feature
needs to be disabled. Therefore, the driver vets the client by
counting an adequate amount of atomic updates before enabling
self-refresh features.
[How]
Add some page flips before test to let the panel replay can be
enabled first.
(This change can be backward compatible with old driver)
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com
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With HDMI dummies we may end up testing a mode that doesn't really
resemble real life scenario like 4k mode with 17Hz refresh rate, which
can lead issues when executing a test. Therefore, the patch proposes
for intel-max-src-size to be tested with with real life refresh rate
such as 30 Hz or higher.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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lobf subtest is using data->switch_modes[LOW_RR_MODE] but not initializing
it. Fix this in output_constraint.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Jeevan B <jeevan.b@intel.com>
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Using gt_id as exec queue for binding is wrong and it works by accident
because bcs engine used in the subtest reside on tile 0. But trying
to run the test on engine which resides on different tile just fails.
Lets use default binding engine for this.
Cc: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Link: https://lore.kernel.org/r/20241031073604.35976-1-zbigniew.kempczynski@intel.com
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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Checking sink PSR status seems to be causing problems as it is performed
by reading dcpd status registers over AUX channel.
Generally having still possibility to check also sink status is a good idea
-> disable them by default and enabled if environment variable
IGT_PSR_SINK_STATUS_CHECKS is set.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
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Verify OA syncs signal correctly in open and change config code
paths. Verify with different types of sync objects as well as by both
waiting and skipping the wait for syncs to signal.
v2: Significantly expand oa syncs testing as described above
v3: Always wait in userptr/ufence cases to avoid -EFAULT errors
v4: Document intel_xe_oa_prop_to_ext function (Kamil)
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Align with kernel commit c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA
sync properties") which adds OA syncs uapi.
v2: Fix #ifdef identifier change (Kamil)
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Add helpers to do bitwise rotate operatios.
igt_rol(): bitwise rotate left
igt_ror(): bitwise rotate right
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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gen2/3 render engine has a max surface size 2kx2k. That is
pretty easy to hit accidentally. Rather than exploding with
an assert it seems better to just gracefully skip the test.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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XY_FAST_COLOR_BLT supports 64bpp natively. Simply enable it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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Handle 8bpp pixels formats correcly in the mmap/pwrite
methods.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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Handle 64bpp pixels formats correcly in the mmap/pwrite
methods.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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Pass the color as uint64_t to igt_draw in preparation
for supporting 64bpp pixel formats.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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Use void* instead of uint32_t* when we don't care about the
element size.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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The current coed is populating buf->ccs[] and buf->surface[]
in a rather inconsistent way.
It looks like for flat CCS platforms:
- we populate buf->ccs[] with some nonsense even though
we shouldn't since the AUX stuff is completely hidden by
the hardware
- we seem to stick data about the clear color into both
both buf->ccs[] and buf->surfaces[] when it should be in neither
For non-flat CCS platforms the code seems more reasonable,
except it only manages to skip the clear color fumble by
the fact that num_planes is always odd with clear color
and thus the /2 will truncate it away.
Anyways, let's make the code make actual sense for all platforms
by properly calculating how many main surfaces and ccs surfaces
there should be.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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[WHY]
Displaying test pattern only exits by user manually pressing enter.
[HOW]
Add option -e to exit with timeout and still allows pressing enter.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
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[WHY]
Atomic commits without active planes are now invalid commits.
[HOW]
Activate primary plane while setting 'max bpc' property.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
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It needs different timings, pixel format and color depth combination
to pass CTS under different HDMI versions. As the result, we extend
this to:
- Add additional timings and info. Especially aspect ratio which
will impact the VIC code.
- Can specify the connector to display the test pattern.
- Set connector property "max bpc" to force bpc.
- Set connector debugfs entry "force_yuv420_output" to enable
using yuv420 pixel format.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
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clear-media-scratch-regs subchecks
Add tests to verify clearing of scratch and media scratch registers in
Virtual Functions (VFs) after a Functional Level Reset (FLR).
This code is based on prior work of Lukasz Laguna.
v2: Adjust mmio to align VF index with array index (Lukasz)
Use helpers for setting skip/fail reasons to improve readability
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Narasimha C V <narasimha.c.v@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
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Add the clear-lmem subcheck to validate the isolation and clearing of a
Virtual Function's (VF) local memory (LMEM) after a Functional Level
Reset (FLR).
The test maps the VF's LMEM, writes specific patterns to the memory,
and checks whether the content is reset for the FLRed VF or retained
for other VFs.
v2: Adjust vf_lmem_size to align VF index with array index,
add TODO to get_vf_lmem_size (Lukasz).
Use helpers for setting skip/fail reasons to improve readability.
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Narasimha C V <narasimha.c.v@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
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Introduce the implementation of the clear-ggtt subcheck, which
provides functionality to verify Functional Level Reset (FLR)
across Virtual Functions (VFs) through GGTT (Global Graphics
Translation Table) testing.
This patch sets up the basic structures for manipulating GGTT
PTEs (Page Table Entries), finds the GGTT ranges assigned to each VF,
and verifies address resets after FLR.
v2: Adjust pte_offsets to align VF index with array index (Lukasz)
Use helpers for setting skip/fail reasons to improve readability
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Narasimha C V <narasimha.c.v@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
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Introduce a skeleton with basic structures for subchecks execution and
a `verify_flr` template method to orchestrate the verification of
Functional Level Reset (FLR) across multiple Virtual Functions (VFs).
The goal is to reduce runtime by limiting the total number of FLRs. Instead
of repeating the FLR process for each subcheck (clear-lmem, clear-ggtt,
clear-scratch-regs, clear-media-scratch-regs), a single FLR is issued.
Afterward, all subchecks verify if any failures occurred and report the
results accordingly. The proposed skeleton ensures that while one subcheck
may stop due to failure or a skip condition, other subchecks can continue
execution.
Concrete subcheck implementations (clear-lmem, clear-ggtt,
clear-scratch-regs, clear-media-scratch-regs) will be introduced
in subsequent patches.
Proposed IGT tests (will report each subcheck's status):
flr-vf1-clear
Verifies that LMEM, GGTT, and SCRATCH_REGS are properly cleared on VF1
(with only VF1 enabled) following a Function Level Reset (FLR). This
test can be included in the BAT (Basic Acceptance Test) suite.
flr-each-isolation
Sequentially performs FLR on each VF to verify isolation and
clearing of LMEM, GGTT, and SCRATCH_REGS on the reset VF only.
This test is better suited for FULL runs.
v2: Correct subtest run type, use uppercase for GT (Lukasz)
Add set_skip_reason, set_fail_reason helpers for readability
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: C V Narasimha <narasimha.c.v@intel.com>
Cc: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Cc: K V P Satyanarayana <satyanarayana.k.v.p@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
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