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authorMarcelo Tosatti <mtosatti@redhat.com>2008-12-08 23:12:49 -0200
committerAvi Kivity <avi@redhat.com>2008-12-28 11:31:57 +0200
commit89313757eba60cf76d2284ba9a7e1a11d42db39c (patch)
tree520c35f5560d26b6488b6dc6bce2ef5019f81e02 /bios
parentf937ff7296edb04cd49e3aa888d164332e5b33b9 (diff)
kvm: bios: revert TSC zeroing
The TSC is zeroed at RESET, and not at SMP initialization. This avoids the TSC from going out of sync between vcpu's on SMP guests. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'bios')
-rwxr-xr-xbios/rombios32.c6
-rw-r--r--bios/rombios32start.S4
2 files changed, 0 insertions, 10 deletions
diff --git a/bios/rombios32.c b/bios/rombios32.c
index 321563da..fd6ff713 100755
--- a/bios/rombios32.c
+++ b/bios/rombios32.c
@@ -623,12 +623,6 @@ void smp_probe(void)
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
sipi_vector = AP_BOOT_ADDR >> 12;
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
- asm volatile(
- "xor %%eax, %%eax \n\t"
- "xor %%edx, %%edx \n\t"
- "mov $0x10, %%ecx \n\t"
- "wrmsr"
- : : : "eax", "ecx", "edx");
#ifndef BX_QEMU
delay_ms(10);
diff --git a/bios/rombios32start.S b/bios/rombios32start.S
index 335e3efd..c9bc045b 100644
--- a/bios/rombios32start.S
+++ b/bios/rombios32start.S
@@ -50,10 +50,6 @@ smp_ap_boot_code_start:
cli
xor %ax, %ax
mov %ax, %ds
- xor %eax, %eax
- xor %edx, %edx
- mov $0x10, %ecx
- wrmsr
mov $SMP_MSR_ADDR, %ebx
11: