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2019-01-11avoid TABs in files that only contain a fewPaolo Bonzini1-2/+2
2019-01-11qemu/queue.h: simplify reverse access to QTAILQPaolo Bonzini2-4/+4
2019-01-11qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini1-1/+1
2018-12-26tcg: Improve call argument loadingRichard Henderson1-1/+2
2018-12-26tcg: Record register preferences during livenessRichard Henderson1-32/+165
2018-12-26tcg: Add TCG_OPF_BB_EXITRichard Henderson3-10/+16
2018-12-26tcg: Split out more subroutines from liveness_pass_1Richard Henderson1-12/+23
2018-12-26tcg: Rename and adjust liveness_pass_1 helpersRichard Henderson1-8/+5
2018-12-26tcg: Reindent parts of liveness_pass_1Richard Henderson1-67/+70
2018-12-26tcg: Dump register preference info with livenessRichard Henderson2-10/+37
2018-12-26tcg: Improve register allocation for matching constraintsRichard Henderson1-12/+24
2018-12-26tcg: Add output_pref to TCGOpRichard Henderson2-7/+14
2018-12-26tcg: Add preferred_reg argument to tcg_reg_alloc_do_moviRichard Henderson1-4/+5
2018-12-26tcg: Add preferred_reg argument to temp_syncRichard Henderson1-8/+8
2018-12-26tcg: Add preferred_reg argument to temp_loadRichard Henderson1-9/+9
2018-12-26tcg: Add preferred_reg argument to tcg_reg_allocRichard Henderson1-22/+81
2018-12-26tcg: Add reachable_code_passRichard Henderson1-0/+76
2018-12-26tcg: Reference count labelsRichard Henderson4-1/+25
2018-12-26tcg: Add TCG_CALL_NO_RETURNRichard Henderson1-0/+2
2018-12-26tcg: Renumber TCG_CALL_* flagsRichard Henderson1-3/+3
2018-12-26tcg/riscv: Add the target init codeAlistair Francis1-0/+31
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis1-0/+111
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis1-0/+496
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis1-0/+158
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis1-0/+256
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis1-0/+145
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis1-0/+55
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis1-0/+65
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis1-0/+34
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis1-0/+86
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis1-0/+88
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis1-0/+48
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis1-0/+90
2018-12-26tcg/riscv: Add support for the constraintsAlistair Francis1-0/+168
2018-12-26tcg/riscv: Add the tcg target registersAlistair Francis1-0/+118
2018-12-26tcg/riscv: Add the tcg-target.h fileAlistair Francis1-0/+177
2018-12-17tcg: Drop nargs from tcg_op_insert_{before,after}Emilio G. Cota3-10/+8
2018-12-17tcg/mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITSAlistair Francis1-1/+1
2018-12-17tcg: Add TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson9-2/+126
2018-12-17tcg/optimize: Optimize bswapRichard Henderson1-0/+12
2018-12-17tcg: Clean up generic bswap64Richard Henderson1-27/+20
2018-12-17tcg: Clean up generic bswap32Richard Henderson1-27/+27
2018-12-17tcg/i386: Add setup_guest_base_seg for FreeBSDRichard Henderson1-0/+9
2018-12-17tcg/i386: Precompute all guest_base parametersRichard Henderson1-61/+40
2018-12-17tcg/i386: Assume 32-bit values are zero-extendedRichard Henderson1-63/+40
2018-12-17tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guestsRichard Henderson2-2/+9
2018-12-17tcg/i386: Propagate is64 to tcg_out_qemu_ld_slow_pathRichard Henderson1-5/+8
2018-12-17tcg/i386: Propagate is64 to tcg_out_qemu_ld_directRichard Henderson1-6/+7
2018-12-17tcg/s390x: Return false on failure from patch_relocRichard Henderson1-11/+23
2018-12-17tcg/ppc: Return false on failure from patch_relocRichard Henderson1-11/+21