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2018-03-28tcg: Mark muluh_i64 and mulsh_i64 as 64-bit opsRichard Henderson1-2/+2
Failure to do so results in the tcg optimizer sign-extending any constant fold from 32-bits. This turns out to be visible in the RISC-V testsuite using a host that emits these opcodes (e.g. any non-x86_64). Reported-by: Michael Clark <mjc@sifive.com> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector ops for multiplicationRichard Henderson1-0/+1
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector ops for comparisonsRichard Henderson1-0/+2
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector ops for constant shiftsRichard Henderson1-0/+12
Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector expandersRichard Henderson1-0/+6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add types and basic operations for host vectorsRichard Henderson1-0/+25
Nothing uses or enables them yet. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-06-05tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptrEmilio G. Cota1-0/+1
Instead of exporting goto_ptr directly to TCG frontends, export tcg_gen_lookup_and_goto_ptr(), which calls goto_ptr with the pointer returned by the lookup_tb_ptr() helper. This is the only use case we have for goto_ptr and lookup_tb_ptr, so having this function is very convenient. Furthermore, it trivially allows us to avoid calling the lookup helper if goto_ptr is not implemented by the backend. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-2-git-send-email-cota@braap.org> Message-Id: <1493263764-18657-3-git-send-email-cota@braap.org> Message-Id: <1493263764-18657-4-git-send-email-cota@braap.org> Message-Id: <1493263764-18657-5-git-send-email-cota@braap.org> [rth: Squashed 4 related commits.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10tcg: Add opcode for ctpopRichard Henderson1-0/+2
The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10tcg: Add clz and ctz opcodesRichard Henderson1-0/+4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10tcg: Add field extraction primitivesRichard Henderson1-0/+4
Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-09-16Introduce TCGOpcode for memory barrierPranith Kumar1-0/+2
This commit introduces the TCGOpcode for memory barrier instruction. This opcode takes an argument which is the type of memory barrier which should be generated. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-2-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-19tcg-opc.h: Simplify insn_start defJames Hogan1-8/+5
We already have a TLADDR_ARGS definition, so rearrange the order slightly and use it in the definition of insn_start, instead of having an #ifdef. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1443788657-14537-2-git-send-email-james.hogan@imgtec.com>
2015-10-07tcg: Allow extra data to be attached to insn_startRichard Henderson1-2/+2
With an eye toward having this data replace the gen_opc_* arrays that each target collects in order to enable restore_state_from_tb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-2/+2
With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson1-2/+5
Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-24tcg: implement real ext_i32_i64 and extu_i32_i64 opsAurelien Jarno1-0/+3
Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a 32-bit value is always converted to a 64-bit value and not propagated through the register allocator or the optimizer. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-24tcg: rename trunc_shr_i32 into trunc_shr_i64_i32Aurelien Jarno1-2/+2
The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends. Always use the long name to make it clear it is a size changing op. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-05-14tcg: Merge memop and mmu_idx parameters to qemu_ld/stRichard Henderson1-4/+4
At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-12tcg: Remove unused opcodesRichard Henderson1-9/+0
We no longer need INDEX_op_end to terminate the list, nor do we need 5 forms of nop, since we just remove the TCGOp instead. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-06-04tcg: Remove TCG_TARGET_HAS_new_ldstRichard Henderson1-100/+14
Since all backends have been converted, remove the compatibility code. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson1-5/+5
The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Make call address a constant parameterRichard Henderson1-1/+1
Avoid allocating a tcg temporary to hold the constant address, and instead place it directly into the op_call arguments. At the same time, convert to the newly introduced tcg_out_call backend function, rather than invoking tcg_out_op for the call. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg: Add INDEX_op_trunc_shr_i32Richard Henderson1-0/+4
Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-34/+62
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+4
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Simplify logic using TCG_OPF_NOT_PRESENTRichard Henderson1-11/+15
Expand the definition of "not present" to include "should not be present". This means we can simplify the logic surrounding the generic tcg opcodes for which the host backend ought not be providing definitions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Allow non-constant control macrosRichard Henderson1-1/+1
This allows TCG_TARGET_HAS_* to be a variable rather than a constant, which allows easier support for differing ISA levels for the host. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-4/+4
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson1-0/+4
Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson1-3/+3
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-28tcg: forbid ld/st function to modify globalsAurelien Jarno1-7/+7
Mapping a memory address using a global and accessing it through ld/st operations is currently broken. As it doesn't make any sense to do that performance wise, let's forbid that. Update the TCG documentation, and remove partial support for that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-28tcg: fix some op flagsAurelien Jarno1-8/+7
Some branch related ops are marked with TCG_OPF_SIDE_EFFECTS, some other not. In practice they don't need to, as they are all marked with TCG_OPF_BB_END, which is handled specifically in all the code. The call op is marked as TCG_OPF_SIDE_EFFECTS, which might be not true as there is are specific flags (TCG_CALL_CONST and TCG_CALL_PURE) for specifying that. On the other hand it always clobber arguments, so mark it as such even if the call op is handled in a different code path. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: remove obsolete jmp opAurelien Jarno1-1/+0
The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+2
Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19tcg: mark set_label with TCG_OPF_BB_END flagAurelien Jarno1-1/+1
set_label is effectively the end of a basic block, as no optimization can be made accross it. It was treated as such in the liveness analysis code, but as a special case. Mark it with TCG_OPF_BB_END flag so that this information can be used by other parts of the TCG code, and remove the special case in the liveness analysis code. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-154/+88
By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg: Add and use TCG_OPF_64BIT.Richard Henderson1-49/+49
This allows the simplification of the op_bits function from tcg/optimize.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-20tcg: Define "deposit" as an optional operation.Richard Henderson1-0/+6
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-06-09tcg: get rid of DEF2 in tcg-opc.hAurelien Jarno1-146/+147
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 in tcg-opc.h. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: get rid of copy_size in TCGOpDefAurelien Jarno1-1/+1
copy_size is a left-over from the dyngen era, remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-2/+3
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+6
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+6
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+6
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg: protect div2 in tcg/tcg-opc.hAurelien Jarno1-2/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-20tcg: fix assertion with --enable-debugJay Foad1-5/+0
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the following assertion failure: qemu-alpha: tcg/tcg.c:1055: tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ORC.Richard Henderson1-0/+6
Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ANDC.Richard Henderson1-0/+6
Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-06tcg: generic support for conditional setRichard Henderson1-0/+3
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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