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2018-03-02Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2018-03-0...Peter Maydell5-18/+53
2018-03-02target/arm: Enable ARM_FEATURE_V8_FCMARichard Henderson2-0/+2
2018-03-02target/arm: Decode t32 simd 3reg and 2reg_scalar extensionRichard Henderson1-1/+13
2018-03-02target/arm: Decode aa32 armv8.3 2-reg-indexRichard Henderson1-0/+61
2018-03-02target/arm: Decode aa32 armv8.3 3-sameRichard Henderson1-0/+68
2018-03-02target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson3-8/+246
2018-03-02target/arm: Decode aa64 armv8.3 fcaddRichard Henderson3-1/+151
2018-03-02target/arm: Add ARM_FEATURE_V8_FCMARichard Henderson1-0/+1
2018-03-02target/arm: Enable ARM_FEATURE_V8_RDMRichard Henderson2-0/+2
2018-03-02target/arm: Decode aa32 armv8.1 two reg and a scalarRichard Henderson1-2/+40
2018-03-02target/arm: Decode aa32 armv8.1 three sameRichard Henderson1-19/+67
2018-03-02target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson1-0/+29
2018-03-02target/arm: Decode aa64 armv8.1 three same extraRichard Henderson3-0/+166
2018-03-02target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson4-1/+198
2018-03-02target/arm: Refactor disas_simd_indexed size checksRichard Henderson1-31/+30
2018-03-02target/arm: Refactor disas_simd_indexed decodeRichard Henderson1-66/+59
2018-03-02target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson1-0/+1
2018-03-02target/arm: Add Cortex-M33Peter Maydell1-0/+31
2018-03-02target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell2-4/+17
2018-03-02target/arm: Define an IDAU interfacePeter Maydell4-3/+104
2018-03-02tricore: renamed masking of PIEDavid Brenken2-9/+10
2018-03-02tricore: renamed masking of IEDavid Brenken3-11/+13
2018-03-02tricore: added CORE_IDDavid Brenken2-0/+2
2018-03-02tricore: added some missing cpu instructionsDavid Brenken2-0/+30
2018-03-01Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180301-v2' into sta...Peter Maydell13-90/+194
2018-03-01s390x/tcg: fix loading 31bit PSWs with the highest bit setDavid Hildenbrand1-0/+4
2018-03-01target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPUPeter Maydell1-0/+1
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée1-0/+71
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée1-0/+99
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée1-26/+54
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée1-10/+25
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée1-0/+7
2018-03-01arm/helper.c: re-factor rsqrte and add rsqrte_f16Alex Bennée2-118/+104
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée3-0/+19
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée3-0/+34
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée1-0/+8
2018-03-01arm/helper.c: re-factor recpe and add recepe_f16Alex Bennée2-97/+128
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée1-1/+15
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée3-24/+104
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée1-23/+57
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée3-1/+118
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée3-5/+142
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée1-0/+40
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée3-6/+76
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée1-16/+66
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée1-75/+133
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée3-0/+42
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée3-0/+41
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée3-0/+69
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée3-0/+36
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