spice/qemu - Qemu (mirrored from https://gitlab.freedesktop.org/spice/qemu)

Age	Commit message (Expand)	Author	Files	Lines
2018-03-02	qapi: Empty out qapi-schema.json	Markus Armbruster	1	-1/+2
2018-03-02	target/arm: Enable ARM_FEATURE_V8_FCMA	Richard Henderson	2	-0/+2
2018-03-02	target/arm: Decode t32 simd 3reg and 2reg_scalar extension	Richard Henderson	1	-1/+13
2018-03-02	target/arm: Decode aa32 armv8.3 2-reg-index	Richard Henderson	1	-0/+61
2018-03-02	target/arm: Decode aa32 armv8.3 3-same	Richard Henderson	1	-0/+68
2018-03-02	target/arm: Decode aa64 armv8.3 fcmla	Richard Henderson	3	-8/+246
2018-03-02	target/arm: Decode aa64 armv8.3 fcadd	Richard Henderson	3	-1/+151
2018-03-02	target/arm: Add ARM_FEATURE_V8_FCMA	Richard Henderson	1	-0/+1
2018-03-02	target/arm: Enable ARM_FEATURE_V8_RDM	Richard Henderson	2	-0/+2
2018-03-02	target/arm: Decode aa32 armv8.1 two reg and a scalar	Richard Henderson	1	-2/+40
2018-03-02	target/arm: Decode aa32 armv8.1 three same	Richard Henderson	1	-19/+67
2018-03-02	target/arm: Decode aa64 armv8.1 scalar/vector x indexed element	Richard Henderson	1	-0/+29
2018-03-02	target/arm: Decode aa64 armv8.1 three same extra	Richard Henderson	3	-0/+166
2018-03-02	target/arm: Decode aa64 armv8.1 scalar three same extra	Richard Henderson	4	-1/+198
2018-03-02	target/arm: Refactor disas_simd_indexed size checks	Richard Henderson	1	-31/+30
2018-03-02	target/arm: Refactor disas_simd_indexed decode	Richard Henderson	1	-66/+59
2018-03-02	target/arm: Add ARM_FEATURE_V8_RDM	Richard Henderson	1	-0/+1
2018-03-02	target/arm: Add Cortex-M33	Peter Maydell	1	-0/+31
2018-03-02	target/arm: Define init-svtor property for the reset secure VTOR value	Peter Maydell	2	-4/+17
2018-03-02	target/arm: Define an IDAU interface	Peter Maydell	4	-3/+104
2018-03-01	target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU	Peter Maydell	1	-0/+1
2018-03-01	arm/translate-a64: add all single op FP16 to handle_fp_1src_half	Alex Bennée	1	-0/+71
2018-03-01	arm/translate-a64: implement simd_scalar_three_reg_same_fp16	Alex Bennée	1	-0/+99
2018-03-01	arm/translate-a64: add all FP16 ops in simd_scalar_pairwise	Alex Bennée	1	-26/+54
2018-03-01	arm/translate-a64: add FP16 FMOV to simd_mod_imm	Alex Bennée	1	-10/+25
2018-03-01	arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16	Alex Bennée	1	-0/+7
2018-03-01	arm/helper.c: re-factor rsqrte and add rsqrte_f16	Alex Bennée	2	-118/+104
2018-03-01	arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16	Alex Bennée	3	-0/+19
2018-03-01	arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16	Alex Bennée	3	-0/+34
2018-03-01	arm/translate-a64: add FP16 FRECPE	Alex Bennée	1	-0/+8
2018-03-01	arm/helper.c: re-factor recpe and add recepe_f16	Alex Bennée	2	-97/+128
2018-03-01	arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16	Alex Bennée	1	-1/+15
2018-03-01	arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16	Alex Bennée	3	-24/+104
2018-03-01	arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16	Alex Bennée	1	-23/+57
2018-03-01	arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16	Alex Bennée	3	-1/+118
2018-03-01	arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16	Alex Bennée	3	-5/+142
2018-03-01	arm/translate-a64: initial decode for simd_two_reg_misc_fp16	Alex Bennée	1	-0/+40
2018-03-01	arm/translate-a64: add FP16 x2 ops for simd_indexed	Alex Bennée	3	-6/+76
2018-03-01	arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed	Alex Bennée	1	-16/+66
2018-03-01	arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16	Alex Bennée	1	-75/+133
2018-03-01	arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16	Alex Bennée	3	-0/+42
2018-03-01	arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16	Alex Bennée	3	-0/+41
2018-03-01	arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16	Alex Bennée	3	-0/+69
2018-03-01	arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16	Alex Bennée	3	-0/+36
2018-03-01	arm/translate-a64: initial decode for simd_three_reg_same_fp16	Alex Bennée	1	-0/+73
2018-03-01	arm/translate-a64: handle_3same_64 comment fix	Alex Bennée	1	-2/+1
2018-03-01	arm/translate-a64: implement half-precision F(MIN\|MAX)(V\|NMV)	Alex Bennée	3	-54/+110
2018-03-01	target/arm/helper: pass explicit fpst to set_rmode	Alex Bennée	4	-22/+22
2018-03-01	target/arm/cpu.h: add additional float_status flags	Alex Bennée	3	-36/+75
2018-03-01	target/arm/cpu.h: update comment for half-precision values	Alex Bennée	1	-0/+1