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path: root/target-arm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2014-02-26target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell1-0/+8
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell1-11/+12
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell1-4/+25
2014-02-20target-arm: Remove unused ARMCPUState sr substructPeter Maydell1-5/+0
2014-02-20target-arm: Define names for SCTLR bitsPeter Maydell1-0/+52
2014-01-31target-arm: Move arm_rmode_to_sf to a shared location.Will Newton1-0/+2
2014-01-12arm: fix compile on bigendian hostAlexey Kardashevskiy1-1/+1
2014-01-08target-arm: Give the FPSCR rounding modes namesAlexander Graf1-0/+9
2014-01-08target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell1-4/+4
2014-01-07target-arm: Widen thread-local register state fields to 64 bitsPeter Maydell1-3/+15
2014-01-07target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell1-1/+2
2014-01-07target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell1-3/+3
2014-01-04target-arm: Update generic cpreg code for AArch64Peter Maydell1-5/+73
2013-12-17target-arm: A64: provide functions for accessing FPCR and FPSRPeter Maydell1-0/+28
2013-12-17target-arm: Clean up handling of AArch64 PSTATEPeter Maydell1-11/+59
2013-12-17target-arm: Define and use ARM_FEATURE_CBARPeter Crosthwaite1-0/+1
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel1-0/+1
2013-12-10target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVMPeter Maydell1-11/+2
2013-10-31target-arm: Add CP15 VBAR supportNathan Rossi1-0/+1
2013-09-10target-arm: Prepare translation for AArch64 codeAlexander Graf1-25/+109
2013-09-10target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf1-2/+2
2013-09-10target-arm: Avoid "1 << 31" undefined behaviourPeter Maydell1-16/+16
2013-08-20target-arm: Implement the generic timerPeter Maydell1-0/+18
2013-08-20target-arm: Support coprocessor registers which do I/OPeter Maydell1-1/+5
2013-08-20target-arm: Make IRQ and FIQ gpio lines on the CPU objectPeter Maydell1-0/+3
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
2013-07-15target-arm: add feature flag for ARMv8Mans Rullgard1-0/+1
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-14/+0
2013-06-25target-arm: Convert TCG to using (index,value) list for cp migrationPeter Maydell1-0/+69
2013-06-25target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfoPeter Maydell1-1/+17
2013-06-25target-arm: Allow special cpregs to have flags setPeter Maydell1-1/+1
2013-04-19target-arm: port ARM CPU save/load to use VMStateJuan Quintela1-2/+0
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-1/+0
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-3/+1
2013-03-05ARM: KVM: Add support for KVM on ARM architectureChristoffer Dall1-0/+1
2013-02-16target-arm: Update ARMCPU to QOM realizefnAndreas Färber1-0/+1
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-3/+3
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-10-05target-arm: Drop unused DECODE_CPREG_CRN macroPeter Maydell1-2/+0
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl1-4/+6
2012-08-10target-arm: Fix typos in commentsPeter Maydell1-1/+1
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell1-2/+5
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell1-3/+3
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell1-0/+2
2012-07-12ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell1-1/+1
2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell1-27/+0
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell1-2/+1
2012-06-20target-arm: Convert MPIDRPeter Maydell1-0/+1
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell1-2/+0
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