diff options
| -rw-r--r-- | target-microblaze/cpu.c | 51 | ||||
| -rw-r--r-- | target-microblaze/translate.c | 51 |
2 files changed, 52 insertions, 50 deletions
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 21b62c62c9..6f00b0d13a 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -1,6 +1,8 @@ /* * QEMU MicroBlaze CPU * + * Copyright (c) 2009 Edgar E. Iglesias + * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. * Copyright (c) 2012 SUSE LINUX Products GmbH * * This library is free software; you can redistribute it and/or @@ -29,9 +31,56 @@ static void mb_cpu_reset(CPUState *s) MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); CPUMBState *env = &cpu->env; + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + mcc->parent_reset(s); - cpu_state_reset(env); + memset(env, 0, offsetof(CPUMBState, breakpoints)); + tlb_flush(env, 1); + + /* Disable stack protector. */ + env->shr = ~0; + + env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ + | PVR0_USE_BARREL_MASK \ + | PVR0_USE_DIV_MASK \ + | PVR0_USE_HW_MUL_MASK \ + | PVR0_USE_EXC_MASK \ + | PVR0_USE_ICACHE_MASK \ + | PVR0_USE_DCACHE_MASK \ + | PVR0_USE_MMU \ + | (0xb << 8); + env->pvr.regs[2] = PVR2_D_OPB_MASK \ + | PVR2_D_LMB_MASK \ + | PVR2_I_OPB_MASK \ + | PVR2_I_LMB_MASK \ + | PVR2_USE_MSR_INSTR \ + | PVR2_USE_PCMP_INSTR \ + | PVR2_USE_BARREL_MASK \ + | PVR2_USE_DIV_MASK \ + | PVR2_USE_HW_MUL_MASK \ + | PVR2_USE_MUL64_MASK \ + | PVR2_USE_FPU_MASK \ + | PVR2_USE_FPU2_MASK \ + | PVR2_FPU_EXC_MASK \ + | 0; + env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ + env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); + +#if defined(CONFIG_USER_ONLY) + /* start in user mode with interrupts enabled. */ + env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ +#else + env->sregs[SR_MSR] = 0; + mmu_init(&env->mmu); + env->mmu.c_mmu = 3; + env->mmu.c_mmu_tlb_access = 3; + env->mmu.c_mmu_zones = 16; +#endif } static void mb_cpu_class_init(ObjectClass *oc, void *data) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index f4d32c8fbb..e730c3261c 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1900,7 +1900,7 @@ CPUMBState *cpu_mb_init (const char *cpu_model) env = &cpu->env; cpu_exec_init(env); - cpu_state_reset(env); + cpu_reset(CPU(cpu)); qemu_init_vcpu(env); set_float_rounding_mode(float_round_nearest_even, &env->fp_status); @@ -1944,54 +1944,7 @@ CPUMBState *cpu_mb_init (const char *cpu_model) void cpu_state_reset(CPUMBState *env) { - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); - log_cpu_state(env, 0); - } - - memset(env, 0, offsetof(CPUMBState, breakpoints)); - tlb_flush(env, 1); - - /* Disable stack protector. */ - env->shr = ~0; - - env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ - | PVR0_USE_BARREL_MASK \ - | PVR0_USE_DIV_MASK \ - | PVR0_USE_HW_MUL_MASK \ - | PVR0_USE_EXC_MASK \ - | PVR0_USE_ICACHE_MASK \ - | PVR0_USE_DCACHE_MASK \ - | PVR0_USE_MMU \ - | (0xb << 8); - env->pvr.regs[2] = PVR2_D_OPB_MASK \ - | PVR2_D_LMB_MASK \ - | PVR2_I_OPB_MASK \ - | PVR2_I_LMB_MASK \ - | PVR2_USE_MSR_INSTR \ - | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_BARREL_MASK \ - | PVR2_USE_DIV_MASK \ - | PVR2_USE_HW_MUL_MASK \ - | PVR2_USE_MUL64_MASK \ - | PVR2_USE_FPU_MASK \ - | PVR2_USE_FPU2_MASK \ - | PVR2_FPU_EXC_MASK \ - | 0; - env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ - env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); - -#if defined(CONFIG_USER_ONLY) - /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; - env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ -#else - env->sregs[SR_MSR] = 0; - mmu_init(&env->mmu); - env->mmu.c_mmu = 3; - env->mmu.c_mmu_tlb_access = 3; - env->mmu.c_mmu_zones = 16; -#endif + cpu_reset(ENV_GET_CPU(env)); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) |