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authorAurelien Jarno <aurelien@aurel32.net>2011-01-06 15:38:19 +0100
committerAurelien Jarno <aurelien@aurel32.net>2011-01-06 16:29:17 +0100
commit93ae1c6fea6433bca732c907d7c3ee9be4f8a2ab (patch)
tree863cf98e15ae32df999aad885365c01ef965a712 /fpu
parentd735d695e7b547272412f63433e023496c4d36ed (diff)
softfloat: fix float{32,64}_maybe_silence_nan() for MIPS
On targets that define sNaN with the sNaN bit as one, simply clearing this bit may correspond to an infinite value. Convert it to a default NaN if SNAN_BIT_IS_ONE, as it corresponds to the MIPS implementation, the only emulated CPU with SNAN_BIT_IS_ONE. When other CPU of this type are added, this might be updated to include more cases. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'fpu')
-rw-r--r--fpu/softfloat-specialize.h20
1 files changed, 14 insertions, 6 deletions
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 33930f99ed..bc6f0c1e5b 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -107,13 +107,17 @@ int float32_is_signaling_nan( float32 a_ )
float32 float32_maybe_silence_nan( float32 a_ )
{
if (float32_is_signaling_nan(a_)) {
- uint32_t a = float32_val(a_);
#if SNAN_BIT_IS_ONE
- a &= ~(1 << 22);
+# if defined(TARGET_MIPS)
+ return float32_default_nan;
+# else
+# error Rules for silencing a signaling NaN are target-specific
+# endif
#else
+ bits32 a = float32_val(a_);
a |= (1 << 22);
-#endif
return make_float32(a);
+#endif
}
return a_;
}
@@ -322,13 +326,17 @@ int float64_is_signaling_nan( float64 a_ )
float64 float64_maybe_silence_nan( float64 a_ )
{
if (float64_is_signaling_nan(a_)) {
- bits64 a = float64_val(a_);
#if SNAN_BIT_IS_ONE
- a &= ~LIT64( 0x0008000000000000 );
+# if defined(TARGET_MIPS)
+ return float64_default_nan;
+# else
+# error Rules for silencing a signaling NaN are target-specific
+# endif
#else
+ bits64 a = float64_val(a_);
a |= LIT64( 0x0008000000000000 );
-#endif
return make_float64(a);
+#endif
}
return a_;
}