Clean up the way we use ralloc contexts so that we can more easiliy clean up memory as we optimize. This may involve changing the way we allocate things or it may mean that we just write a mark-and-sweep memory clean-up pass. Figure out how to represent/validate non-32-bit instructions. This will be needed for ARB_gpu_shader_fp64 as well as fp16 and the variably sized integer extensions. Add support for scalar vertex shaders. Add support for scalar geometry shaders. Add support for Gen 4/5 hardware. This is mostly a matter of adding the code to properly resolve booleans. Add a vec4 backend for i965. Add support for ARB fragment programs. Add support for ARB vertex programs. Add support for indirect local variable accesses to the i965 FS back-end. We already do this in vec4 by using our spill scratch-space. We could do the same for the FS back-end. Add an analysis pass to sort uniforms by "cost" and add proper push constant support in the i965 NIR backend. Implement a Global Code Motion pass. Implement a Global Value Numbering pass. Implement a uniform analysis pass. Implement a dead/constant control-flow pass. Implement a control-flow and range analysis pass. Port the indirect local variable lowering pass to NIR. We have a pass right now that lowers indirect local variable accesses to binary-search if-ladders. It would be nice to be able to do that in NIR so that NIR's superior alias analysis can be put to good use. Add phi nodes to the CSE pass. Implement a pass that removes pointless phi nodes. After copy propagation and other optimization passes happen, it's easy to end up with phi nodes with all sources the same. In this case, we can just remove the phi node entirely and replace every use of its definition with the common source. Convert the i965 FS backend to use SSA