diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/Makefile.am | 6 | ||||
| -rw-r--r-- | tests/amdgpu/Makefile.am | 26 | ||||
| -rw-r--r-- | tests/amdgpu/amdgpu_test.c | 220 | ||||
| -rw-r--r-- | tests/amdgpu/amdgpu_test.h | 119 | ||||
| -rw-r--r-- | tests/amdgpu/basic_tests.c | 669 | ||||
| -rw-r--r-- | tests/amdgpu/bo_tests.c | 151 | ||||
| -rw-r--r-- | tests/amdgpu/cs_tests.c | 319 | ||||
| -rw-r--r-- | tests/amdgpu/uvd_messages.h | 813 | ||||
| -rw-r--r-- | tests/kmstest/main.c | 1 |
9 files changed, 2324 insertions, 0 deletions
diff --git a/tests/Makefile.am b/tests/Makefile.am index c5edec86..9a2d9328 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -8,6 +8,12 @@ if HAVE_RADEON SUBDIRS += radeon endif +if HAVE_AMDGPU +if HAVE_CUNIT +SUBDIRS += amdgpu +endif +endif + if HAVE_EXYNOS SUBDIRS += exynos endif diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am new file mode 100644 index 00000000..68401310 --- /dev/null +++ b/tests/amdgpu/Makefile.am @@ -0,0 +1,26 @@ +AM_CFLAGS = \ + -I $(top_srcdir)/include/drm \ + -I $(top_srcdir)/amdgpu \ + -I $(top_srcdir) + +LDADD = $(top_builddir)/libdrm.la \ + $(top_builddir)/amdgpu/libdrm_amdgpu.la \ + $(CUNIT_LIBS) + +if HAVE_INSTALL_TESTS +bin_PROGRAMS = \ + amdgpu_test +else +noinst_PROGRAMS = \ + amdgpu_test +endif + +amdgpu_test_CPPFLAGS = $(CUNIT_CFLAGS) + +amdgpu_test_SOURCES = \ + amdgpu_test.c \ + amdgpu_test.h \ + basic_tests.c \ + bo_tests.c \ + cs_tests.c \ + uvd_messages.h diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c new file mode 100644 index 00000000..c8432fa9 --- /dev/null +++ b/tests/amdgpu/amdgpu_test.c @@ -0,0 +1,220 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <string.h> +#include <ctype.h> +#include <fcntl.h> +#include <errno.h> +#include <signal.h> +#include <time.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/ioctl.h> +#include <sys/time.h> +#include <stdarg.h> +#include <stdint.h> + +#include "drm.h" +#include "xf86drmMode.h" +#include "xf86drm.h" + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" + +/** + * Open handles for amdgpu devices + * + */ +int drm_amdgpu[MAX_CARDS_SUPPORTED]; + +/** The table of all known test suites to run */ +static CU_SuiteInfo suites[] = { + { "Basic Tests", suite_basic_tests_init, + suite_basic_tests_clean, basic_tests }, + { "BO Tests", suite_bo_tests_init, + suite_bo_tests_clean, bo_tests }, + { "CS Tests", suite_cs_tests_init, + suite_cs_tests_clean, cs_tests }, + CU_SUITE_INFO_NULL, +}; + + +/** Display information about all suites and their tests */ +static void display_test_suites(void) +{ + int iSuite; + int iTest; + + printf("Suites\n"); + + for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) { + printf("Suite id = %d: Name '%s'\n", + iSuite + 1, suites[iSuite].pName); + + for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL; + iTest++) { + printf(" Test id %d: Name: '%s'\n", iTest + 1, + suites[iSuite].pTests[iTest].pName); + } + } +} + + +/** Help string for command line parameters */ +static const char usage[] = "Usage: %s [-hl] [<-s <suite id>> [-t <test id>]]\n" + "where:\n" + " l - Display all suites and their tests\n" + " h - Display this help\n"; +/** Specified options strings for getopt */ +static const char options[] = "hls:t:"; + +/* The main() function for setting up and running the tests. + * Returns a CUE_SUCCESS on successful running, another + * CUnit error code on failure. + */ +int main(int argc, char **argv) +{ + int c; /* Character received from getopt */ + int i = 0; + int suite_id = -1; /* By default run everything */ + int test_id = -1; /* By default run all tests in the suite */ + CU_pSuite pSuite = NULL; + CU_pTest pTest = NULL; + + int aval = drmAvailable(); + + if (aval == 0) { + fprintf(stderr, "DRM driver is not available\n"); + exit(EXIT_FAILURE); + } + + + for (i = 0; i < MAX_CARDS_SUPPORTED; i++) + drm_amdgpu[i] = -1; + + + /* Parse command line string */ + opterr = 0; /* Do not print error messages from getopt */ + while ((c = getopt(argc, argv, options)) != -1) { + switch (c) { + case 'l': + display_test_suites(); + exit(EXIT_SUCCESS); + case 's': + suite_id = atoi(optarg); + break; + case 't': + test_id = atoi(optarg); + break; + case '?': + case 'h': + fprintf(stderr, usage, argv[0]); + exit(EXIT_SUCCESS); + default: + fprintf(stderr, usage, argv[0]); + exit(EXIT_FAILURE); + } + } + + /* Try to open all possible radeon connections + * Right now: Open only the 0. + */ + printf("Try to open the card 0..\n"); + drm_amdgpu[0] = open("/dev/dri/card0", O_RDWR | O_CLOEXEC); + + if (drm_amdgpu[0] < 0) { + perror("Cannot open /dev/dri/card0\n"); + exit(EXIT_FAILURE); + } + + /** Display version of DRM driver */ + drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); + + if (retval == NULL) { + perror("Could not get information about DRM driver"); + exit(EXIT_FAILURE); + } + + printf("DRM Driver: Name: [%s] : Date [%s] : Description [%s]\n", + retval->name, retval->date, retval->desc); + + drmFreeVersion(retval); + + /* Initialize test suites to run */ + + /* initialize the CUnit test registry */ + if (CUE_SUCCESS != CU_initialize_registry()) { + close(drm_amdgpu[0]); + return CU_get_error(); + } + + /* Register suites. */ + if (CU_register_suites(suites) != CUE_SUCCESS) { + fprintf(stderr, "suite registration failed - %s\n", + CU_get_error_msg()); + CU_cleanup_registry(); + close(drm_amdgpu[0]); + exit(EXIT_FAILURE); + } + + /* Run tests using the CUnit Basic interface */ + CU_basic_set_mode(CU_BRM_VERBOSE); + + if (suite_id != -1) { /* If user specify particular suite? */ + pSuite = CU_get_suite_by_index((unsigned int) suite_id, + CU_get_registry()); + + if (pSuite) { + if (test_id != -1) { /* If user specify test id */ + pTest = CU_get_test_by_index( + (unsigned int) test_id, + pSuite); + if (pTest) + CU_basic_run_test(pSuite, pTest); + else { + fprintf(stderr, "Invalid test id: %d\n", + test_id); + CU_cleanup_registry(); + close(drm_amdgpu[0]); + exit(EXIT_FAILURE); + } + } else + CU_basic_run_suite(pSuite); + } else { + fprintf(stderr, "Invalid suite id : %d\n", + suite_id); + CU_cleanup_registry(); + close(drm_amdgpu[0]); + exit(EXIT_FAILURE); + } + } else + CU_basic_run_tests(); + + CU_cleanup_registry(); + close(drm_amdgpu[0]); + return CU_get_error(); +} diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h new file mode 100644 index 00000000..80073d27 --- /dev/null +++ b/tests/amdgpu/amdgpu_test.h @@ -0,0 +1,119 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#ifndef _AMDGPU_TEST_H_ +#define _AMDGPU_TEST_H_ + +#include "amdgpu.h" + +/** + * Define max. number of card in system which we are able to handle + */ +#define MAX_CARDS_SUPPORTED 4 + +/* Forward reference for array to keep "drm" handles */ +extern int drm_amdgpu[MAX_CARDS_SUPPORTED]; + +/************************* Basic test suite ********************************/ + +/* + * Define basic test suite to serve as the starting point for future testing +*/ + +/** + * Initialize basic test suite + */ +int suite_basic_tests_init(); + +/** + * Deinitialize basic test suite + */ +int suite_basic_tests_clean(); + +/** + * Tests in basic test suite + */ +extern CU_TestInfo basic_tests[]; + +/** + * Initialize bo test suite + */ +int suite_bo_tests_init(); + +/** + * Deinitialize bo test suite + */ +int suite_bo_tests_clean(); + +/** + * Tests in bo test suite + */ +extern CU_TestInfo bo_tests[]; + +/** + * Initialize cs test suite + */ +int suite_cs_tests_init(); + +/** + * Deinitialize cs test suite + */ +int suite_cs_tests_clean(); + +/** + * Tests in cs test suite + */ +extern CU_TestInfo cs_tests[]; + +/** + * Helper functions + */ +static inline amdgpu_bo_handle gpu_mem_alloc( + amdgpu_device_handle device_handle, + uint64_t size, + uint64_t alignment, + uint32_t type, + uint64_t flags, + uint64_t *vmc_addr) +{ + struct amdgpu_bo_alloc_request req = {0}; + struct amdgpu_bo_alloc_result res = {0}; + int r; + + CU_ASSERT_NOT_EQUAL(vmc_addr, NULL); + + req.alloc_size = size; + req.phys_alignment = alignment; + req.preferred_heap = type; + req.flags = flags; + + r = amdgpu_bo_alloc(device_handle, &req, &res); + CU_ASSERT_EQUAL(r, 0); + + CU_ASSERT_NOT_EQUAL(res.virtual_mc_base_address, 0); + CU_ASSERT_NOT_EQUAL(res.buf_handle, NULL); + *vmc_addr = res.virtual_mc_base_address; + return res.buf_handle; +} + +#endif /* #ifdef _AMDGPU_TEST_H_ */ diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c new file mode 100644 index 00000000..d04b1517 --- /dev/null +++ b/tests/amdgpu/basic_tests.c @@ -0,0 +1,669 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; + +static void amdgpu_query_info_test(void); +static void amdgpu_memory_alloc(void); +static void amdgpu_command_submission_gfx(void); +static void amdgpu_command_submission_compute(void); +static void amdgpu_command_submission_sdma(void); +static void amdgpu_userptr_test(void); + +CU_TestInfo basic_tests[] = { + { "Query Info Test", amdgpu_query_info_test }, + { "Memory alloc Test", amdgpu_memory_alloc }, + { "Userptr Test", amdgpu_userptr_test }, + { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, + { "Command submission Test (Compute)", amdgpu_command_submission_compute }, + { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, + CU_TEST_INFO_NULL, +}; +#define BUFFER_SIZE (8 * 1024) +#define SDMA_PKT_HEADER_op_offset 0 +#define SDMA_PKT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_HEADER_op_shift 0 +#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) +#define SDMA_OPCODE_CONSTANT_FILL 11 +# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) + /* 0 = byte fill + * 2 = DW fill + */ +#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ + (((sub_op) & 0xFF) << 8) | \ + (((op) & 0xFF) << 0)) +#define SDMA_OPCODE_WRITE 2 +# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 +# define SDMA_WRTIE_SUB_OPCODE_TILED 1 + +#define SDMA_OPCODE_COPY 1 +# define SDMA_COPY_SUB_OPCODE_LINEAR 0 + +int suite_basic_tests_init(void) +{ + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + + if (r == 0) + return CUE_SUCCESS; + else + return CUE_SINIT_FAILED; +} + +int suite_basic_tests_clean(void) +{ + int r = amdgpu_device_deinitialize(device_handle); + + if (r == 0) + return CUE_SUCCESS; + else + return CUE_SCLEAN_FAILED; +} + +static void amdgpu_query_info_test(void) +{ + struct amdgpu_gpu_info gpu_info = {0}; + uint32_t version, feature; + int r; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, + 0, &version, &feature); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_memory_alloc(void) +{ + amdgpu_bo_handle bo; + uint64_t bo_mc; + int r; + + /* Test visible VRAM */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + &bo_mc); + + r = amdgpu_bo_free(bo); + CU_ASSERT_EQUAL(r, 0); + + /* Test invisible VRAM */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_NO_CPU_ACCESS, + &bo_mc); + + r = amdgpu_bo_free(bo); + CU_ASSERT_EQUAL(r, 0); + + /* Test GART Cacheable */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, + 0, + &bo_mc); + + r = amdgpu_bo_free(bo); + CU_ASSERT_EQUAL(r, 0); + + /* Test GART USWC */ + bo = gpu_mem_alloc(device_handle, + 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_CPU_GTT_WC, + &bo_mc); + + r = amdgpu_bo_free(bo); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_command_submission_gfx(void) +{ + amdgpu_context_handle context_handle; + struct amdgpu_cs_ib_alloc_result ib_result = {0}; + struct amdgpu_cs_ib_alloc_result ib_result_ce = {0}; + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info[2]; + struct amdgpu_cs_query_fence fence_status = {0}; + uint32_t *ptr; + uint32_t expired; + int r; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_alloc_ib(device_handle, context_handle, + amdgpu_cs_ib_size_4K, &ib_result); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_alloc_ib(device_handle, context_handle, + amdgpu_cs_ib_size_4K, &ib_result_ce); + CU_ASSERT_EQUAL(r, 0); + + memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); + + /* IT_SET_CE_DE_COUNTERS */ + ptr = ib_result_ce.cpu; + ptr[0] = 0xc0008900; + ptr[1] = 0; + ptr[2] = 0xc0008400; + ptr[3] = 1; + ib_info[0].ib_handle = ib_result_ce.handle; + ib_info[0].size = 4; + ib_info[0].flags = AMDGPU_CS_GFX_IB_CE; + + /* IT_WAIT_ON_CE_COUNTER */ + ptr = ib_result.cpu; + ptr[0] = 0xc0008600; + ptr[1] = 0x00000001; + ib_info[1].ib_handle = ib_result.handle; + ib_info[1].size = 2; + + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.number_of_ibs = 2; + ibs_request.ibs = ib_info; + + r = amdgpu_cs_submit(device_handle, context_handle, 0, + &ibs_request, 1, &fence_status.fence); + CU_ASSERT_EQUAL(r, 0); + + fence_status.context = context_handle; + fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + + r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(device_handle, context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_command_submission_compute(void) +{ + amdgpu_context_handle context_handle; + struct amdgpu_cs_ib_alloc_result ib_result; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + struct amdgpu_cs_query_fence fence_status; + uint32_t *ptr; + uint32_t expired; + int i, r, instance; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + for (instance = 0; instance < 8; instance++) { + memset(&ib_result, 0, sizeof(struct amdgpu_cs_ib_alloc_result)); + r = amdgpu_cs_alloc_ib(device_handle, context_handle, + amdgpu_cs_ib_size_4K, &ib_result); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result.cpu; + for (i = 0; i < 16; ++i) + ptr[i] = 0xffff1000; + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_handle = ib_result.handle; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE; + ibs_request.ring = instance; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + + memset(&fence_status, 0, sizeof(struct amdgpu_cs_query_fence)); + r = amdgpu_cs_submit(device_handle, context_handle, 0, + &ibs_request, 1, &fence_status.fence); + CU_ASSERT_EQUAL(r, 0); + + fence_status.context = context_handle; + fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE; + fence_status.ip_type = AMDGPU_HW_IP_COMPUTE; + fence_status.ring = instance; + + r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired); + CU_ASSERT_EQUAL(r, 0); + } + + r = amdgpu_cs_ctx_free(device_handle, context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +/* + * caller need create/release: + * pm4_src, resources, ib_info, and ibs_request + * submit command stream described in ibs_request and wait for this IB accomplished + */ +static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle, + int instance, int pm4_dw, uint32_t *pm4_src, + int res_cnt, amdgpu_bo_handle *resources, + struct amdgpu_cs_ib_info *ib_info, + struct amdgpu_cs_request *ibs_request) +{ + int r, i, j; + uint32_t expired; + uint32_t *ring_ptr; + struct amdgpu_cs_ib_alloc_result ib_result = {0}; + struct amdgpu_cs_query_fence fence_status = {0}; + + /* prepare CS */ + CU_ASSERT_NOT_EQUAL(pm4_src, NULL); + CU_ASSERT_NOT_EQUAL(resources, NULL); + CU_ASSERT_NOT_EQUAL(ib_info, NULL); + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + CU_ASSERT_TRUE(pm4_dw <= 1024); + + /* allocate IB */ + r = amdgpu_cs_alloc_ib(device_handle, context_handle, + amdgpu_cs_ib_size_4K, &ib_result); + CU_ASSERT_EQUAL(r, 0); + + /* copy PM4 packet to ring from caller */ + ring_ptr = ib_result.cpu; + memcpy(ring_ptr, pm4_src, pm4_dw * sizeof(*pm4_src)); + + ib_info->ib_handle = ib_result.handle; + ib_info->size = pm4_dw; + + ibs_request->ip_type = AMDGPU_HW_IP_DMA; + ibs_request->ring = instance; + ibs_request->number_of_ibs = 1; + ibs_request->ibs = ib_info; + ibs_request->number_of_resources = res_cnt; + ibs_request->resources = resources; + + + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + + /* submit CS */ + r = amdgpu_cs_submit(device_handle, context_handle, 0, + ibs_request, 1, &fence_status.fence); + CU_ASSERT_EQUAL(r, 0); + + fence_status.ip_type = AMDGPU_HW_IP_DMA; + fence_status.ring = ibs_request->ring; + fence_status.context = context_handle; + fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE; + + /* wait for IB accomplished */ + r = amdgpu_cs_query_fence_status(device_handle, &fence_status, + &expired); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); +} + +static void amdgpu_command_submission_sdma_write_linear(void) +{ + const int sdma_write_length = 128; + const int pm4_dw = 256; + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo; + amdgpu_bo_handle *resources; + uint32_t *pm4; + struct amdgpu_cs_ib_info *ib_info; + struct amdgpu_cs_request *ibs_request; + uint64_t bo_mc; + volatile uint32_t *bo_cpu; + int i, j, r, loop; + uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC, + AMDGPU_GEM_CREATE_CPU_GTT_WC}; + + pm4 = calloc(pm4_dw, sizeof(*pm4)); + CU_ASSERT_NOT_EQUAL(pm4, NULL); + + ib_info = calloc(1, sizeof(*ib_info)); + CU_ASSERT_NOT_EQUAL(ib_info, NULL); + + ibs_request = calloc(1, sizeof(*ibs_request)); + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + /* prepare resource */ + resources = calloc(1, sizeof(amdgpu_bo_handle)); + CU_ASSERT_NOT_EQUAL(resources, NULL); + + loop = 0; + while(loop < 3) { + /* allocate UC bo for sDMA use */ + bo = gpu_mem_alloc(device_handle, + sdma_write_length * sizeof(uint32_t), + 4096, AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop], &bo_mc); + + CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo, (void **)&bo_cpu), 0); + CU_ASSERT_NOT_EQUAL(bo_cpu, NULL); + + /* clear bo */ + memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); + + + resources[0] = bo; + + /* fullfill PM4: test DMA write-linear */ + i = j = 0; + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + + amdgpu_sdma_test_exec_cs(context_handle, 0, + i, pm4, + 1, resources, + ib_info, ibs_request); + + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } + amdgpu_bo_free(bo); + loop++; + } + /* clean resources */ + free(resources); + free(ibs_request); + free(ib_info); + free(pm4); + + /* end of test */ + r = amdgpu_cs_ctx_free(device_handle, context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_command_submission_sdma_const_fill(void) +{ + const int sdma_write_length = 1024 * 1024; + const int pm4_dw = 256; + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo; + amdgpu_bo_handle *resources; + uint32_t *pm4; + struct amdgpu_cs_ib_info *ib_info; + struct amdgpu_cs_request *ibs_request; + uint64_t bo_mc; + volatile uint32_t *bo_cpu; + int i, j, r, loop; + uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC, + AMDGPU_GEM_CREATE_CPU_GTT_WC}; + + pm4 = calloc(pm4_dw, sizeof(*pm4)); + CU_ASSERT_NOT_EQUAL(pm4, NULL); + + ib_info = calloc(1, sizeof(*ib_info)); + CU_ASSERT_NOT_EQUAL(ib_info, NULL); + + ibs_request = calloc(1, sizeof(*ibs_request)); + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + /* prepare resource */ + resources = calloc(1, sizeof(amdgpu_bo_handle)); + CU_ASSERT_NOT_EQUAL(resources, NULL); + + loop = 0; + while(loop < 3) { + /* allocate UC bo for sDMA use */ + bo = gpu_mem_alloc(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop], &bo_mc); + + CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo, (void **)&bo_cpu), 0); + CU_ASSERT_NOT_EQUAL(bo_cpu, NULL); + + /* clear bo */ + memset((void*)bo_cpu, 0, sdma_write_length); + + resources[0] = bo; + + /* fullfill PM4: test DMA const fill */ + i = j = 0; + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, + SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = sdma_write_length; + + amdgpu_sdma_test_exec_cs(context_handle, 0, + i, pm4, + 1, resources, + ib_info, ibs_request); + + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < (sdma_write_length / 4)) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } + amdgpu_bo_free(bo); + loop++; + } + /* clean resources */ + free(resources); + free(ibs_request); + free(ib_info); + free(pm4); + + /* end of test */ + r = amdgpu_cs_ctx_free(device_handle, context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_command_submission_sdma_copy_linear(void) +{ + const int sdma_write_length = 1024; + const int pm4_dw = 256; + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo1, bo2; + amdgpu_bo_handle *resources; + uint32_t *pm4; + struct amdgpu_cs_ib_info *ib_info; + struct amdgpu_cs_request *ibs_request; + uint64_t bo1_mc, bo2_mc; + volatile unsigned char *bo1_cpu, *bo2_cpu; + int i, j, r, loop1, loop2; + uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC, + AMDGPU_GEM_CREATE_CPU_GTT_WC}; + + pm4 = calloc(pm4_dw, sizeof(*pm4)); + CU_ASSERT_NOT_EQUAL(pm4, NULL); + + ib_info = calloc(1, sizeof(*ib_info)); + CU_ASSERT_NOT_EQUAL(ib_info, NULL); + + ibs_request = calloc(1, sizeof(*ibs_request)); + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + /* prepare resource */ + resources = calloc(2, sizeof(amdgpu_bo_handle)); + CU_ASSERT_NOT_EQUAL(resources, NULL); + + loop1 = loop2 = 0; + /* run 9 circle to test all mapping combination */ + while(loop1 < 3) { + while(loop2 < 3) { + /* allocate UC bo1for sDMA use */ + bo1 = gpu_mem_alloc(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop1], &bo1_mc); + + CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo1, (void **)&bo1_cpu), 0); + CU_ASSERT_NOT_EQUAL(bo1_cpu, NULL); + + /* set bo1 */ + memset((void*)bo1_cpu, 0xaa, sdma_write_length); + + /* allocate UC bo2 for sDMA use */ + bo2 = gpu_mem_alloc(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop2], &bo2_mc); + + CU_ASSERT_EQUAL(amdgpu_bo_cpu_map(bo2, (void **)&bo2_cpu), 0); + CU_ASSERT_NOT_EQUAL(bo2_cpu, NULL); + + /* clear bo2 */ + memset((void*)bo2_cpu, 0, sdma_write_length); + + resources[0] = bo1; + resources[1] = bo2; + + /* fullfill PM4: test DMA copy linear */ + i = j = 0; + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); + pm4[i++] = sdma_write_length; + pm4[i++] = 0; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + + + amdgpu_sdma_test_exec_cs(context_handle, 0, + i, pm4, + 2, resources, + ib_info, ibs_request); + + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); + } + amdgpu_bo_free(bo1); + amdgpu_bo_free(bo2); + loop2++; + } + loop1++; + } + /* clean resources */ + free(resources); + free(ibs_request); + free(ib_info); + free(pm4); + + /* end of test */ + r = amdgpu_cs_ctx_free(device_handle, context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_command_submission_sdma(void) +{ + amdgpu_command_submission_sdma_write_linear(); + amdgpu_command_submission_sdma_const_fill(); + amdgpu_command_submission_sdma_copy_linear(); +} + +static void amdgpu_userptr_test(void) +{ + int i, r, j; + uint32_t *pm4 = NULL; + uint64_t bo_mc; + void *ptr = NULL; + int pm4_dw = 256; + int sdma_write_length = 4; + amdgpu_bo_handle handle; + amdgpu_context_handle context_handle; + struct amdgpu_cs_ib_info *ib_info; + struct amdgpu_cs_request *ibs_request; + struct amdgpu_bo_alloc_result res; + + memset(&res, 0, sizeof(res)); + + pm4 = calloc(pm4_dw, sizeof(*pm4)); + CU_ASSERT_NOT_EQUAL(pm4, NULL); + + ib_info = calloc(1, sizeof(*ib_info)); + CU_ASSERT_NOT_EQUAL(ib_info, NULL); + + ibs_request = calloc(1, sizeof(*ibs_request)); + CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + posix_memalign(&ptr, sysconf(_SC_PAGE_SIZE), BUFFER_SIZE); + CU_ASSERT_NOT_EQUAL(ptr, NULL); + memset(ptr, 0, BUFFER_SIZE); + + r = amdgpu_create_bo_from_user_mem(device_handle, + ptr, BUFFER_SIZE, &res); + CU_ASSERT_EQUAL(r, 0); + bo_mc = res.virtual_mc_base_address; + handle = res.buf_handle; + + j = i = 0; + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + + while (j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + + amdgpu_sdma_test_exec_cs(context_handle, 0, + i, pm4, + 1, &handle, + ib_info, ibs_request); + i = 0; + while (i < sdma_write_length) { + CU_ASSERT_EQUAL(((int*)ptr)[i++], 0xdeadbeaf); + } + free(ibs_request); + free(ib_info); + free(pm4); + r = amdgpu_bo_free(res.buf_handle); + CU_ASSERT_EQUAL(r, 0); + free(ptr); + + r = amdgpu_cs_ctx_free(device_handle, context_handle); + CU_ASSERT_EQUAL(r, 0); +} diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c new file mode 100644 index 00000000..73701b74 --- /dev/null +++ b/tests/amdgpu/bo_tests.c @@ -0,0 +1,151 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ +#include <stdio.h> + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" + +#define BUFFER_SIZE (4*1024) +#define BUFFER_ALIGN (4*1024) + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; + +static amdgpu_bo_handle buffer_handle; +static uint64_t virtual_mc_base_address; + +static void amdgpu_bo_export_import(void); +static void amdgpu_bo_metadata(void); +static void amdgpu_bo_map_unmap(void); + +CU_TestInfo bo_tests[] = { + { "Export/Import", amdgpu_bo_export_import }, +#if 0 + { "Metadata", amdgpu_bo_metadata }, +#endif + { "CPU map/unmap", amdgpu_bo_map_unmap }, + CU_TEST_INFO_NULL, +}; + +int suite_bo_tests_init(void) +{ + struct amdgpu_bo_alloc_request req = {0}; + struct amdgpu_bo_alloc_result res = {0}; + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + if (r) + return CUE_SINIT_FAILED; + + req.alloc_size = BUFFER_SIZE; + req.phys_alignment = BUFFER_ALIGN; + req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; + + r = amdgpu_bo_alloc(device_handle, &req, &res); + if (r) + return CUE_SINIT_FAILED; + + buffer_handle = res.buf_handle; + virtual_mc_base_address = res.virtual_mc_base_address; + + return CUE_SUCCESS; +} + +int suite_bo_tests_clean(void) +{ + int r; + + r = amdgpu_bo_free(buffer_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + + return CUE_SUCCESS; +} + +static void amdgpu_bo_export_import_do_type(enum amdgpu_bo_handle_type type) +{ + struct amdgpu_bo_import_result res = {0}; + uint32_t shared_handle; + int r; + + r = amdgpu_bo_export(buffer_handle, type, &shared_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_import(device_handle, type, shared_handle, &res); + CU_ASSERT_EQUAL(r, 0); + + CU_ASSERT_EQUAL(res.buf_handle, buffer_handle); + CU_ASSERT_EQUAL(res.alloc_size, BUFFER_SIZE); + + r = amdgpu_bo_free(res.buf_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_bo_export_import(void) +{ + amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_gem_flink_name); + amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_dma_buf_fd); +} + +static void amdgpu_bo_metadata(void) +{ + struct amdgpu_bo_metadata meta = {0}; + struct amdgpu_bo_info info = {0}; + int r; + + meta.size_metadata = 1; + meta.umd_metadata[0] = 0xdeadbeef; + + r = amdgpu_bo_set_metadata(buffer_handle, &meta); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_query_info(buffer_handle, &info); + CU_ASSERT_EQUAL(r, 0); + + CU_ASSERT_EQUAL(info.metadata.size_metadata, 1); + CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef); +} + +static void amdgpu_bo_map_unmap(void) +{ + uint32_t *ptr; + int i, r; + + r = amdgpu_bo_cpu_map(buffer_handle, (void **)&ptr); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_NOT_EQUAL(ptr, NULL); + + for (i = 0; i < (BUFFER_SIZE / 4); ++i) + ptr[i] = 0xdeadbeef; + + r = amdgpu_bo_cpu_unmap(buffer_handle); + CU_ASSERT_EQUAL(r, 0); +} diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c new file mode 100644 index 00000000..ca63ae25 --- /dev/null +++ b/tests/amdgpu/cs_tests.c @@ -0,0 +1,319 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ +#include <stdio.h> + +#include "CUnit/Basic.h" + +#include "util_math.h" + +#include "amdgpu_test.h" +#include "uvd_messages.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" + +#define IB_SIZE amdgpu_cs_ib_size_4K +#define MAX_RESOURCES 16 + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; +static uint32_t family_id; + +static amdgpu_context_handle context_handle; +static amdgpu_ib_handle ib_handle; +uint32_t *ib_cpu; + +static amdgpu_bo_handle resources[MAX_RESOURCES]; +static unsigned num_resources; + +static void amdgpu_cs_uvd_create(void); +static void amdgpu_cs_uvd_decode(void); +static void amdgpu_cs_uvd_destroy(void); + +CU_TestInfo cs_tests[] = { + { "UVD create", amdgpu_cs_uvd_create }, + { "UVD decode", amdgpu_cs_uvd_decode }, + { "UVD destroy", amdgpu_cs_uvd_destroy }, + CU_TEST_INFO_NULL, +}; + +int suite_cs_tests_init(void) +{ + struct amdgpu_cs_ib_alloc_result ib_result = {0}; + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + if (r) + return CUE_SINIT_FAILED; + + family_id = device_handle->info.family_id; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + if (r) + return CUE_SINIT_FAILED; + + r = amdgpu_cs_alloc_ib(device_handle, context_handle, + IB_SIZE, &ib_result); + if (r) + return CUE_SINIT_FAILED; + + ib_handle = ib_result.handle; + ib_cpu = ib_result.cpu; + + return CUE_SUCCESS; +} + +int suite_cs_tests_clean(void) +{ + int r; + + r = amdgpu_cs_free_ib(device_handle, context_handle, ib_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(device_handle, context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + + return CUE_SUCCESS; +} + +static int submit(unsigned ndw, unsigned ip) +{ + struct amdgpu_cs_ib_alloc_result ib_result = {0}; + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info = {0}; + struct amdgpu_cs_query_fence fence_status = {0}; + uint32_t expired; + int r; + + ib_info.ib_handle = ib_handle; + ib_info.size = ndw; + + ibs_request.ip_type = ip; + ibs_request.number_of_resources = num_resources; + ibs_request.resources = resources; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + + r = amdgpu_cs_submit(device_handle, context_handle, 0, + &ibs_request, 1, &fence_status.fence); + if (r) + return r; + + r = amdgpu_cs_alloc_ib(device_handle, context_handle, + IB_SIZE, &ib_result); + if (r) + return r; + + ib_handle = ib_result.handle; + ib_cpu = ib_result.cpu; + + fence_status.context = context_handle; + fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE; + fence_status.ip_type = ip; + + r = amdgpu_cs_query_fence_status(device_handle, &fence_status, &expired); + if (r) + return r; + + return 0; +} + +static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx) +{ + ib_cpu[(*idx)++] = 0x3BC4; + ib_cpu[(*idx)++] = addr; + ib_cpu[(*idx)++] = 0x3BC5; + ib_cpu[(*idx)++] = addr >> 32; + ib_cpu[(*idx)++] = 0x3BC3; + ib_cpu[(*idx)++] = cmd << 1; +} + +static void amdgpu_cs_uvd_create(void) +{ + struct amdgpu_bo_alloc_request req = {0}; + struct amdgpu_bo_alloc_result res = {0}; + void *msg; + int i, r; + + req.alloc_size = 4*1024; + req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; + + r = amdgpu_bo_alloc(device_handle, &req, &res); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_cpu_map(res.buf_handle, &msg); + CU_ASSERT_EQUAL(r, 0); + + memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); + if (family_id >= AMDGPU_FAMILY_VI) + ((uint8_t*)msg)[0x10] = 7; + + r = amdgpu_bo_cpu_unmap(res.buf_handle); + CU_ASSERT_EQUAL(r, 0); + + num_resources = 0; + resources[num_resources++] = res.buf_handle; + + i = 0; + uvd_cmd(res.virtual_mc_base_address, 0x0, &i); + for (; i % 16; ++i) + ib_cpu[i] = 0x80000000; + + r = submit(i, AMDGPU_HW_IP_UVD); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_free(resources[0]); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_cs_uvd_decode(void) +{ + const unsigned dpb_size = 15923584, dt_size = 737280; + uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr; + struct amdgpu_bo_alloc_request req = {0}; + struct amdgpu_bo_alloc_result res = {0}; + uint64_t sum; + uint8_t *ptr; + int i, r; + + req.alloc_size = 4*1024; /* msg */ + req.alloc_size += 4*1024; /* fb */ + if (family_id >= AMDGPU_FAMILY_VI) + req.alloc_size += 4096; /*it_scaling_table*/ + req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024); + req.alloc_size += ALIGN(dpb_size, 4*1024); + req.alloc_size += ALIGN(dt_size, 4*1024); + + req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; + + r = amdgpu_bo_alloc(device_handle, &req, &res); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_cpu_map(res.buf_handle, (void **)&ptr); + CU_ASSERT_EQUAL(r, 0); + + memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg)); + if (family_id >= AMDGPU_FAMILY_VI) + ptr[0x10] = 7; + + ptr += 4*1024; + memset(ptr, 0, 4*1024); + if (family_id >= AMDGPU_FAMILY_VI) { + ptr += 4*1024; + memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table)); + } + + ptr += 4*1024; + memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream)); + + ptr += ALIGN(sizeof(uvd_bitstream), 4*1024); + memset(ptr, 0, dpb_size); + + ptr += ALIGN(dpb_size, 4*1024); + memset(ptr, 0, dt_size); + + num_resources = 0; + resources[num_resources++] = res.buf_handle; + + msg_addr = res.virtual_mc_base_address; + fb_addr = msg_addr + 4*1024; + if (family_id >= AMDGPU_FAMILY_VI) { + it_addr = fb_addr + 4*1024; + bs_addr = it_addr + 4*1024; + } else + bs_addr = fb_addr + 4*1024; + dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); + dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); + + i = 0; + uvd_cmd(msg_addr, 0x0, &i); + uvd_cmd(dpb_addr, 0x1, &i); + uvd_cmd(dt_addr, 0x2, &i); + uvd_cmd(fb_addr, 0x3, &i); + uvd_cmd(bs_addr, 0x100, &i); + if (family_id >= AMDGPU_FAMILY_VI) + uvd_cmd(it_addr, 0x204, &i); + ib_cpu[i++] = 0x3BC6; + ib_cpu[i++] = 0x1; + for (; i % 16; ++i) + ib_cpu[i] = 0x80000000; + + r = submit(i, AMDGPU_HW_IP_UVD); + CU_ASSERT_EQUAL(r, 0); + + /* TODO: use a real CRC32 */ + for (i = 0, sum = 0; i < dt_size; ++i) + sum += ptr[i]; + CU_ASSERT_EQUAL(sum, 0x20345d8); + + r = amdgpu_bo_cpu_unmap(res.buf_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_free(resources[0]); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_cs_uvd_destroy(void) +{ + struct amdgpu_bo_alloc_request req = {0}; + struct amdgpu_bo_alloc_result res = {0}; + void *msg; + int i, r; + + req.alloc_size = 4*1024; + req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; + + r = amdgpu_bo_alloc(device_handle, &req, &res); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_cpu_map(res.buf_handle, &msg); + CU_ASSERT_EQUAL(r, 0); + + memcpy(msg, uvd_destroy_msg, sizeof(uvd_create_msg)); + if (family_id >= AMDGPU_FAMILY_VI) + ((uint8_t*)msg)[0x10] = 7; + + r = amdgpu_bo_cpu_unmap(res.buf_handle); + CU_ASSERT_EQUAL(r, 0); + + num_resources = 0; + resources[num_resources++] = res.buf_handle; + + i = 0; + uvd_cmd(res.virtual_mc_base_address, 0x0, &i); + for (; i % 16; ++i) + ib_cpu[i] = 0x80000000; + + r = submit(i, AMDGPU_HW_IP_UVD); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_free(resources[0]); + CU_ASSERT_EQUAL(r, 0); +} diff --git a/tests/amdgpu/uvd_messages.h b/tests/amdgpu/uvd_messages.h new file mode 100644 index 00000000..44bcacc5 --- /dev/null +++ b/tests/amdgpu/uvd_messages.h @@ -0,0 +1,813 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _UVD_MESSAGES_H_ +#define _UVD_MESSAGES_H_ + +static uint8_t uvd_create_msg[] = { + 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00, + 0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, + 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, +}; + +#endif /* _UVD_MESSAGES_H_ */ diff --git a/tests/kmstest/main.c b/tests/kmstest/main.c index 19ce5707..120bc0fa 100644 --- a/tests/kmstest/main.c +++ b/tests/kmstest/main.c @@ -62,6 +62,7 @@ static const char *drivers[] = { "nouveau", "vmwgfx", "exynos", + "amdgpu", "imx-drm", "rockchip", "atmel-hlcdc", |