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Diffstat (limited to 'shared/via_drm.h')
-rw-r--r--shared/via_drm.h166
1 files changed, 82 insertions, 84 deletions
diff --git a/shared/via_drm.h b/shared/via_drm.h
index 52adade2..ed2ee2ac 100644
--- a/shared/via_drm.h
+++ b/shared/via_drm.h
@@ -52,8 +52,8 @@
#define VIA_LOG_MIN_TEX_REGION_SIZE 16
#endif
-#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
-#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
+#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
+#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
#define VIA_UPLOAD_CTX 0x4
#define VIA_UPLOAD_BUFFERS 0x8
#define VIA_UPLOAD_TEX0 0x10
@@ -73,12 +73,11 @@
#define DRM_IOCTL_VIA_FLUSH DRM_IO(0x49)
#define DRM_IOCTL_VIA_PCICMD DRM_IOW(0x4A, drm_via_cmdbuffer_t)
-
/* Indices into buf.Setup where various bits of state are mirrored per
* context and per buffer. These can be fired at the card as a unit,
* or in a piecewise fashion as required.
*/
-
+
#define VIA_TEX_SETUP_SIZE 8
/* Flags for clear ioctl
@@ -90,120 +89,119 @@
#define VIDEO 0
#define AGP 1
typedef struct {
- unsigned long offset;
- unsigned long size;
-} drm_via_agp_t;
+ unsigned long offset;
+ unsigned long size;
+} drm_via_agp_t;
typedef struct {
- unsigned long offset;
- unsigned long size;
-} drm_via_fb_t;
+ unsigned long offset;
+ unsigned long size;
+} drm_via_fb_t;
typedef struct {
- uint32_t context;
- uint32_t type;
- unsigned long size;
- unsigned long index;
- unsigned long offset;
-} drm_via_mem_t;
+ uint32_t context;
+ uint32_t type;
+ unsigned long size;
+ unsigned long index;
+ unsigned long offset;
+} drm_via_mem_t;
typedef struct _drm_via_init {
- enum {
- VIA_INIT_MAP = 0x01,
- VIA_CLEANUP_MAP = 0x02
- } func;
-
- unsigned long sarea_priv_offset;
- unsigned long fb_offset;
- unsigned long mmio_offset;
- unsigned long agpAddr;
+ enum {
+ VIA_INIT_MAP = 0x01,
+ VIA_CLEANUP_MAP = 0x02
+ } func;
+
+ unsigned long sarea_priv_offset;
+ unsigned long fb_offset;
+ unsigned long mmio_offset;
+ unsigned long agpAddr;
} drm_via_init_t;
typedef struct _drm_via_futex {
- enum {
- VIA_FUTEX_WAIT = 0x00,
- VIA_FUTEX_WAKE = 0X01
- } func;
- uint32_t ms;
- uint32_t lock;
- uint32_t val;
+ enum {
+ VIA_FUTEX_WAIT = 0x00,
+ VIA_FUTEX_WAKE = 0X01
+ } func;
+ uint32_t ms;
+ uint32_t lock;
+ uint32_t val;
} drm_via_futex_t;
typedef struct _drm_via_dma_init {
- enum {
- VIA_INIT_DMA = 0x01,
- VIA_CLEANUP_DMA = 0x02
- } func;
-
- unsigned long offset;
- unsigned long size;
- unsigned long reg_pause_addr;
+ enum {
+ VIA_INIT_DMA = 0x01,
+ VIA_CLEANUP_DMA = 0x02
+ } func;
+
+ unsigned long offset;
+ unsigned long size;
+ unsigned long reg_pause_addr;
} drm_via_dma_init_t;
typedef struct _drm_via_cmdbuffer {
- char *buf;
- unsigned long size;
+ char *buf;
+ unsigned long size;
} drm_via_cmdbuffer_t;
/* Warning: If you change the SAREA structure you must change the Xserver
* structure as well */
typedef struct _drm_via_tex_region {
- unsigned char next, prev; /* indices to form a circular LRU */
- unsigned char inUse; /* owned by a client, or free? */
- int age; /* tracked by clients to update local LRU's */
+ unsigned char next, prev; /* indices to form a circular LRU */
+ unsigned char inUse; /* owned by a client, or free? */
+ int age; /* tracked by clients to update local LRU's */
} drm_via_tex_region_t;
typedef struct _drm_via_sarea {
- unsigned int dirty;
- unsigned int nbox;
- drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
- drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
- int texAge; /* last time texture was uploaded */
- int ctxOwner; /* last context to upload state */
- int vertexPrim;
-
- /*
- * Below is for XvMC.
- * We want the lock integers alone on, and aligned to, a cache line.
- * Therefore this somewhat strange construct.
- */
-
- char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
-
- unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
- unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
- unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
+ unsigned int dirty;
+ unsigned int nbox;
+ drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
+ drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
+ int texAge; /* last time texture was uploaded */
+ int ctxOwner; /* last context to upload state */
+ int vertexPrim;
+
+ /*
+ * Below is for XvMC.
+ * We want the lock integers alone on, and aligned to, a cache line.
+ * Therefore this somewhat strange construct.
+ */
+
+ char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
+
+ unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
+ unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
+ unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
} drm_via_sarea_t;
-
typedef struct _drm_via_flush_agp {
- unsigned int offset;
- unsigned int size;
- unsigned int index;
- int discard; /* client is finished with the buffer? */
+ unsigned int offset;
+ unsigned int size;
+ unsigned int index;
+ int discard; /* client is finished with the buffer? */
} drm_via_flush_agp_t;
typedef struct _drm_via_flush_sys {
- unsigned int offset;
- unsigned int size;
- unsigned long index;
- int discard; /* client is finished with the buffer? */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long index;
+ int discard; /* client is finished with the buffer? */
} drm_via_flush_sys_t;
#ifdef __KERNEL__
-int via_fb_init( DRM_IOCTL_ARGS );
-int via_mem_alloc( DRM_IOCTL_ARGS );
-int via_mem_free( DRM_IOCTL_ARGS );
-int via_agp_init( DRM_IOCTL_ARGS );
-int via_map_init( DRM_IOCTL_ARGS );
-int via_decoder_futex( DRM_IOCTL_ARGS );
-int via_dma_init( DRM_IOCTL_ARGS );
-int via_cmdbuffer( DRM_IOCTL_ARGS );
-int via_flush_ioctl( DRM_IOCTL_ARGS );
-int via_pci_cmdbuffer( DRM_IOCTL_ARGS );
+int via_fb_init(DRM_IOCTL_ARGS);
+int via_mem_alloc(DRM_IOCTL_ARGS);
+int via_mem_free(DRM_IOCTL_ARGS);
+int via_agp_init(DRM_IOCTL_ARGS);
+int via_map_init(DRM_IOCTL_ARGS);
+int via_decoder_futex(DRM_IOCTL_ARGS);
+int via_dma_init(DRM_IOCTL_ARGS);
+int via_cmdbuffer(DRM_IOCTL_ARGS);
+int via_flush_ioctl(DRM_IOCTL_ARGS);
+int via_pci_cmdbuffer(DRM_IOCTL_ARGS);
#endif
-#endif /* _VIA_DRM_H_ */
+#endif /* _VIA_DRM_H_ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 22:59:51 +0000