diff options
Diffstat (limited to 'bsd/mga')
| -rw-r--r-- | bsd/mga/mga_bufs.c | 604 | ||||
| -rw-r--r-- | bsd/mga/mga_context.c | 200 | ||||
| -rw-r--r-- | bsd/mga/mga_dma.c | 1544 | ||||
| -rw-r--r-- | bsd/mga/mga_drv.c | 752 | ||||
| -rw-r--r-- | bsd/mga/mga_drv.h | 1024 | ||||
| -rw-r--r-- | bsd/mga/mga_state.c | 1577 |
6 files changed, 2061 insertions, 3640 deletions
diff --git a/bsd/mga/mga_bufs.c b/bsd/mga/mga_bufs.c deleted file mode 100644 index 4ae05181..00000000 --- a/bsd/mga/mga_bufs.c +++ /dev/null @@ -1,604 +0,0 @@ -/* mga_bufs.c -- IOCTLs to manage buffers - * Created: Thu Jan 6 01:47:26 2000 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: Rickard E. (Rik) Faith <faith@valinux.com> - * Jeff Hartmann <jhartmann@valinux.com> - * - * - */ - -#define __NO_VERSION__ -#include "drmP.h" -#include "mga_drv.h" -#include <sys/mman.h> -#include <vm/vm.h> -#include <vm/pmap.h> -#include <vm/vm_extern.h> -#include <vm/vm_map.h> - - -static int -mga_addbufs_agp(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - drm_buf_desc_t request; - drm_buf_entry_t *entry; - drm_buf_t *buf; - unsigned long offset; - unsigned long agp_offset; - int count; - int order; - int size; - int alignment; - int page_order; - int total; - int byte_count; - int i; - - if (!dma) return EINVAL; - - request = *(drm_buf_desc_t *) data; - - count = request.count; - order = drm_order(request.size); - size = 1 << order; - agp_offset = request.agp_start; - alignment = (request.flags & _DRM_PAGE_ALIGN) ? round_page(size) :size; - page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; - total = PAGE_SIZE << page_order; - byte_count = 0; - - DRM_DEBUG("count: %d\n", count); - DRM_DEBUG("order: %d\n", order); - DRM_DEBUG("size: %d\n", size); - DRM_DEBUG("agp_offset: %ld\n", agp_offset); - DRM_DEBUG("alignment: %d\n", alignment); - DRM_DEBUG("page_order: %d\n", page_order); - DRM_DEBUG("total: %d\n", total); - DRM_DEBUG("byte_count: %d\n", byte_count); - - if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return EINVAL; - if (dev->queue_count) return EBUSY; /* Not while in use */ - simple_lock(&dev->count_lock); - if (dev->buf_use) { - simple_unlock(&dev->count_lock); - return EBUSY; - } - atomic_inc(&dev->buf_alloc); - simple_unlock(&dev->count_lock); - - lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, curproc); - entry = &dma->bufs[order]; - if (entry->buf_count) { - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - atomic_dec(&dev->buf_alloc); - return ENOMEM; /* May only call once for each order */ - } - - entry->buflist = drm_alloc(count * sizeof(*entry->buflist), - DRM_MEM_BUFS); - if (!entry->buflist) { - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - atomic_dec(&dev->buf_alloc); - return ENOMEM; - } - memset(entry->buflist, 0, count * sizeof(*entry->buflist)); - - entry->buf_size = size; - entry->page_order = page_order; - offset = 0; - - - while(entry->buf_count < count) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; - - DRM_DEBUG("offset : %ld\n", offset); - - buf->offset = offset; /* Hrm */ - buf->bus_address = dev->agp->base + agp_offset + offset; - buf->address = (void *)(agp_offset + offset + dev->agp->base); - buf->next = NULL; - buf->waiting = 0; - buf->pending = 0; - buf->dma_wait = 0; - buf->pid = 0; - - buf->dev_private = drm_alloc(sizeof(drm_mga_buf_priv_t), DRM_MEM_BUFS); - buf->dev_priv_size = sizeof(drm_mga_buf_priv_t); - -#if DRM_DMA_HISTOGRAM - timespecclear(&buf->time_queued); - timespecclear(&buf->time_dispatched); - timespecclear(&buf->time_completed); - timespecclear(&buf->time_freed); -#endif - offset = offset + alignment; - entry->buf_count++; - byte_count += PAGE_SIZE << page_order; - - DRM_DEBUG("buffer %d @ %p\n", - entry->buf_count, buf->address); - } - - dma->buflist = drm_realloc(dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS); - for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) - dma->buflist[i] = &entry->buflist[i - dma->buf_count]; - - dma->buf_count += entry->buf_count; - - DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count); - - dma->byte_count += byte_count; - - DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count); - - drm_freelist_create(&entry->freelist, entry->buf_count); - for (i = 0; i < entry->buf_count; i++) { - drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); - } - - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - - request.count = entry->buf_count; - request.size = size; - - *(drm_buf_desc_t *) data = request; - - atomic_dec(&dev->buf_alloc); - - DRM_DEBUG("count: %d\n", count); - DRM_DEBUG("order: %d\n", order); - DRM_DEBUG("size: %d\n", size); - DRM_DEBUG("agp_offset: %ld\n", agp_offset); - DRM_DEBUG("alignment: %d\n", alignment); - DRM_DEBUG("page_order: %d\n", page_order); - DRM_DEBUG("total: %d\n", total); - DRM_DEBUG("byte_count: %d\n", byte_count); - - dma->flags = _DRM_DMA_USE_AGP; - - DRM_DEBUG("dma->flags : %x\n", dma->flags); - - return 0; -} - -static int -mga_addbufs_pci(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - drm_buf_desc_t request; - int count; - int order; - int size; - int total; - int page_order; - drm_buf_entry_t *entry; - unsigned long page; - drm_buf_t *buf; - int alignment; - unsigned long offset; - int i; - int byte_count; - int page_count; - - if (!dma) return EINVAL; - - request = *(drm_buf_desc_t *) data; - - count = request.count; - order = drm_order(request.size); - size = 1 << order; - - DRM_DEBUG("count = %d, size = %d (%d), order = %d, queue_count = %d\n", - request.count, request.size, size, order, dev->queue_count); - - if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return EINVAL; - if (dev->queue_count) return EBUSY; /* Not while in use */ - - alignment = (request.flags & _DRM_PAGE_ALIGN) ? round_page(size) :size; - page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; - total = PAGE_SIZE << page_order; - - simple_lock(&dev->count_lock); - if (dev->buf_use) { - simple_unlock(&dev->count_lock); - return EBUSY; - } - atomic_inc(&dev->buf_alloc); - simple_unlock(&dev->count_lock); - - lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, curproc); - entry = &dma->bufs[order]; - if (entry->buf_count) { - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - atomic_dec(&dev->buf_alloc); - return ENOMEM; /* May only call once for each order */ - } - - entry->buflist = drm_alloc(count * sizeof(*entry->buflist), - DRM_MEM_BUFS); - if (!entry->buflist) { - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - atomic_dec(&dev->buf_alloc); - return ENOMEM; - } - memset(entry->buflist, 0, count * sizeof(*entry->buflist)); - - entry->seglist = drm_alloc(count * sizeof(*entry->seglist), - DRM_MEM_SEGS); - if (!entry->seglist) { - drm_free(entry->buflist, - count * sizeof(*entry->buflist), - DRM_MEM_BUFS); - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - atomic_dec(&dev->buf_alloc); - return ENOMEM; - } - memset(entry->seglist, 0, count * sizeof(*entry->seglist)); - - dma->pagelist = drm_realloc(dma->pagelist, - dma->page_count * sizeof(*dma->pagelist), - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES); - DRM_DEBUG("pagelist: %d entries\n", - dma->page_count + (count << page_order)); - - - entry->buf_size = size; - entry->page_order = page_order; - byte_count = 0; - page_count = 0; - while (entry->buf_count < count) { - if (!(page = drm_alloc_pages(page_order, DRM_MEM_DMA))) break; - entry->seglist[entry->seg_count++] = page; - for (i = 0; i < (1 << page_order); i++) { - DRM_DEBUG("page %d @ 0x%08lx\n", - dma->page_count + page_count, - page + PAGE_SIZE * i); - dma->pagelist[dma->page_count + page_count++] - = page + PAGE_SIZE * i; - } - for (offset = 0; - offset + size <= total && entry->buf_count < count; - offset += alignment, ++entry->buf_count) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; - buf->offset = (dma->byte_count + byte_count + offset); - buf->address = (void *)(page + offset); - buf->next = NULL; - buf->waiting = 0; - buf->pending = 0; - buf->dma_wait = 0; - buf->pid = 0; -#if DRM_DMA_HISTOGRAM - timespecclear(&buf->time_queued); - timespecclear(&buf->time_dispatched); - timespecclear(&buf->time_completed); - timespecclear(&buf->time_freed); -#endif - DRM_DEBUG("buffer %d @ %p\n", - entry->buf_count, buf->address); - } - byte_count += PAGE_SIZE << page_order; - } - - dma->buflist = drm_realloc(dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS); - for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) - dma->buflist[i] = &entry->buflist[i - dma->buf_count]; - - dma->buf_count += entry->buf_count; - dma->seg_count += entry->seg_count; - dma->page_count += entry->seg_count << page_order; - dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); - - drm_freelist_create(&entry->freelist, entry->buf_count); - for (i = 0; i < entry->buf_count; i++) { - drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); - } - - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - - request.count = entry->buf_count; - request.size = size; - - *(drm_buf_desc_t *) data = request; - - atomic_dec(&dev->buf_alloc); - return 0; -} - -int -mga_addbufs(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_buf_desc_t request; - - request = *(drm_buf_desc_t *) data; - - if(request.flags & _DRM_AGP_BUFFER) - return mga_addbufs_agp(kdev, cmd, data, flags, p); - else - return mga_addbufs_pci(kdev, cmd, data, flags, p); -} - -int -mga_infobufs(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - drm_buf_info_t request; - int i; - int count; - int error; - - if (!dma) return EINVAL; - - simple_lock(&dev->count_lock); - if (atomic_read(&dev->buf_alloc)) { - simple_unlock(&dev->count_lock); - return EBUSY; - } - ++dev->buf_use; /* Can't allocate more after this call */ - simple_unlock(&dev->count_lock); - - request = *(drm_buf_info_t *) data; - - for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { - if (dma->bufs[i].buf_count) ++count; - } - - DRM_DEBUG("count = %d\n", count); - - if (request.count >= count) { - for (i = 0, count = 0; i < DRM_MAX_ORDER+1; i++) { - if (dma->bufs[i].buf_count) { - error = copyout(&dma->bufs[i].buf_count, - &request.list[count].count, - sizeof(dma->bufs[0] - .buf_count)); - if (error) return error; - error = copyout(&dma->bufs[i].buf_size, - &request.list[count].size, - sizeof(dma->bufs[0] - .buf_size)); - if (error) return error; - error = copyout(&dma->bufs[i] - .freelist.low_mark, - &request.list[count].low_mark, - sizeof(dma->bufs[0] - .freelist.low_mark)); - if (error) return error; - error = copyout(&dma->bufs[i] - .freelist.high_mark, - &request.list[count].high_mark, - sizeof(dma->bufs[0] - .freelist.high_mark)); - if (error) return error; - DRM_DEBUG("%d %d %d %d %d\n", - i, - dma->bufs[i].buf_count, - dma->bufs[i].buf_size, - dma->bufs[i].freelist.low_mark, - dma->bufs[i].freelist.high_mark); - ++count; - } - } - } - request.count = count; - - *(drm_buf_info_t *) data = request; - - return 0; -} - -int -mga_markbufs(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - drm_buf_desc_t request; - int order; - drm_buf_entry_t *entry; - - if (!dma) return EINVAL; - - request = *(drm_buf_desc_t *) data; - - DRM_DEBUG("%d, %d, %d\n", - request.size, request.low_mark, request.high_mark); - order = drm_order(request.size); - if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return EINVAL; - entry = &dma->bufs[order]; - - if (request.low_mark < 0 || request.low_mark > entry->buf_count) - return EINVAL; - if (request.high_mark < 0 || request.high_mark > entry->buf_count) - return EINVAL; - - entry->freelist.low_mark = request.low_mark; - entry->freelist.high_mark = request.high_mark; - - return 0; -} - -int -mga_freebufs(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - drm_buf_free_t request; - int i; - int error; - int idx; - drm_buf_t *buf; - - if (!dma) return EINVAL; - - request = *(drm_buf_free_t *) data; - - DRM_DEBUG("%d\n", request.count); - for (i = 0; i < request.count; i++) { - error = copyin(&request.list[i], - &idx, - sizeof(idx)); - if (error) return error; - if (idx < 0 || idx >= dma->buf_count) { - DRM_ERROR("Index %d (of %d max)\n", - idx, dma->buf_count - 1); - return EINVAL; - } - buf = dma->buflist[idx]; - if (buf->pid != p->p_pid) { - DRM_ERROR("Process %d freeing buffer owned by %d\n", - p->p_pid, buf->pid); - return EINVAL; - } - drm_free_buffer(dev, buf); - } - - return 0; -} - -int -mga_mapbufs(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - int retcode = 0; - const int zero = 0; - vm_offset_t virtual; - vm_offset_t address; - drm_buf_map_t request; - int i; - - if (!dma) return EINVAL; - - DRM_DEBUG("\n"); - - simple_lock(&dev->count_lock); - if (atomic_read(&dev->buf_alloc)) { - simple_unlock(&dev->count_lock); - DRM_DEBUG("Busy\n"); - return EBUSY; - } - ++dev->buf_use; /* Can't allocate more after this call */ - simple_unlock(&dev->count_lock); - - request = *(drm_buf_map_t *) data; - - DRM_DEBUG("mga_mapbufs\n"); - DRM_DEBUG("dma->flags : %x\n", dma->flags); - - if (request.count >= dma->buf_count) { - if(dma->flags & _DRM_DMA_USE_AGP) { - drm_mga_private_t *dev_priv = dev->dev_private; - drm_map_t *map = NULL; - - map = dev->maplist[dev_priv->buffer_map_idx]; - if (!map) { - DRM_DEBUG("map is null\n"); - retcode = EINVAL; - goto done; - } - - DRM_DEBUG("map->offset : %lx\n", map->offset); - DRM_DEBUG("map->size : %lx\n", map->size); - DRM_DEBUG("map->type : %d\n", map->type); - DRM_DEBUG("map->flags : %x\n", map->flags); - DRM_DEBUG("map->handle : %p\n", map->handle); - DRM_DEBUG("map->mtrr : %d\n", map->mtrr); - virtual = 0; - retcode = vm_mmap(&p->p_vmspace->vm_map, - &virtual, - map->size, - PROT_READ|PROT_WRITE, VM_PROT_ALL, - MAP_SHARED, - SLIST_FIRST(&kdev->si_hlist), - map->offset); - } else { - virtual = 0; - retcode = vm_mmap(&p->p_vmspace->vm_map, - &virtual, - round_page(dma->byte_count), - PROT_READ|PROT_WRITE, VM_PROT_ALL, - MAP_SHARED, - SLIST_FIRST(&kdev->si_hlist), - 0); - } - if (retcode) { - /* Real error */ - DRM_DEBUG("mmap error\n"); - goto done; - } - request.virtual = (void *)virtual; - - for (i = 0; i < dma->buf_count; i++) { - retcode = copyout(&dma->buflist[i]->idx, - &request.list[i].idx, - sizeof(request.list[0].idx)); - if (retcode) goto done; - retcode = copyout(&dma->buflist[i]->total, - &request.list[i].total, - sizeof(request.list[0].total)); - if (retcode) goto done; - retcode = copyout(&zero, - &request.list[i].used, - sizeof(request.list[0].used)); - if (retcode) goto done; - address = virtual + dma->buflist[i]->offset; - retcode = copyout(&address, - &request.list[i].address, - sizeof(address)); - if (retcode) goto done; - } - } - done: - request.count = dma->buf_count; - DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); - - *(drm_buf_map_t *) data = request; - - DRM_DEBUG("retcode : %d\n", retcode); - - return retcode; -} diff --git a/bsd/mga/mga_context.c b/bsd/mga/mga_context.c deleted file mode 100644 index 63515bab..00000000 --- a/bsd/mga/mga_context.c +++ /dev/null @@ -1,200 +0,0 @@ -/* mga_context.c -- IOCTLs for mga contexts - * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Author: Rickard E. (Rik) Faith <faith@valinux.com> - * Jeff Hartmann <jhartmann@valinux.com> - * - */ - -#define __NO_VERSION__ -#include "drmP.h" -#include "mga_drv.h" - -static int mga_alloc_queue(drm_device_t *dev) -{ - int temp = drm_ctxbitmap_next(dev); - DRM_DEBUG("mga_alloc_queue: %d\n", temp); - return temp; -} - -int mga_context_switch(drm_device_t *dev, int old, int new) -{ - char buf[64]; - - atomic_inc(&dev->total_ctx); - - if (test_and_set_bit(0, &dev->context_flag)) { - DRM_ERROR("Reentering -- FIXME\n"); - return EBUSY; - } - -#if DRM_DMA_HISTOGRAM - getnanotime(&dev->ctx_start); -#endif - - DRM_DEBUG("Context switch from %d to %d\n", old, new); - - if (new == dev->last_context) { - clear_bit(0, &dev->context_flag); - return 0; - } - - if (drm_flags & DRM_FLAG_NOCTX) { - mga_context_switch_complete(dev, new); - } else { - sprintf(buf, "C %d %d\n", old, new); - drm_write_string(dev, buf); - } - - return 0; -} - -int mga_context_switch_complete(drm_device_t *dev, int new) -{ - dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ - dev->last_switch = ticks; - - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("Lock isn't held after context switch\n"); - } - - /* If a context switch is ever initiated - when the kernel holds the lock, release - that lock here. */ -#if DRM_DMA_HISTOGRAM - { - struct timespec ts; - getnanotime(&ts); - timespecsub(&ts, &dev->lck_start); - atomic_inc(&dev->histo.ctx[drm_histogram_slot(&ts)]); - } -#endif - clear_bit(0, &dev->context_flag); - wakeup(&dev->context_wait); - - return 0; -} - -int -mga_resctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_ctx_res_t res; - drm_ctx_t ctx; - int i, error; - - DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); - res = *(drm_ctx_res_t *) data; - if (res.count >= DRM_RESERVED_CONTEXTS) { - memset(&ctx, 0, sizeof(ctx)); - for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { - ctx.handle = i; - error = copyout(&i, &res.contexts[i], sizeof(i)); - if (error) return error; - } - } - res.count = DRM_RESERVED_CONTEXTS; - *(drm_ctx_res_t *) data = res; - return 0; -} - -int -mga_addctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_ctx_t ctx; - - ctx = *(drm_ctx_t *) data; - if ((ctx.handle = mga_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { - /* Skip kernel's context and get a new one. */ - ctx.handle = mga_alloc_queue(dev); - } - if (ctx.handle == -1) { - DRM_DEBUG("Not enough free contexts.\n"); - /* Should this return EBUSY instead? */ - return ENOMEM; - } - DRM_DEBUG("%d\n", ctx.handle); - *(drm_ctx_t *) data = ctx; - return 0; -} - -int -mga_modctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - /* This does nothing for the mga */ - return 0; -} - -int mga_getctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_ctx_t ctx; - - ctx = *(drm_ctx_t *) data; - /* This is 0, because we don't hanlde any context flags */ - ctx.flags = 0; - *(drm_ctx_t *) data = ctx; - return 0; -} - -int mga_switchctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_ctx_t ctx; - - ctx = *(drm_ctx_t *) data; - DRM_DEBUG("%d\n", ctx.handle); - return mga_context_switch(dev, dev->last_context, ctx.handle); -} - -int mga_newctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_ctx_t ctx; - - ctx = *(drm_ctx_t *) data; - DRM_DEBUG("%d\n", ctx.handle); - mga_context_switch_complete(dev, ctx.handle); - - return 0; -} - -int mga_rmctx(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_ctx_t ctx; - - ctx = *(drm_ctx_t *) data; - DRM_DEBUG("%d\n", ctx.handle); -/* - if(ctx.handle == DRM_KERNEL_CONTEXT+1) - priv->remove_auth_on_close = 1; -*/ - if(ctx.handle != DRM_KERNEL_CONTEXT ) { - drm_ctxbitmap_free(dev, ctx.handle); - } - - return 0; -} diff --git a/bsd/mga/mga_dma.c b/bsd/mga/mga_dma.c index 85c29df7..9ed5d095 100644 --- a/bsd/mga/mga_dma.c +++ b/bsd/mga/mga_dma.c @@ -1,4 +1,4 @@ -/* mga_dma.c -- DMA support for mga g200/g400 +/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -11,11 +11,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -24,1054 +24,796 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * - * Authors: Rickard E. (Rik) Faith <faith@valinux.com> - * Jeff Hartmann <jhartmann@valinux.com> - * Keith Whitwell <keithw@valinux.com> + * Authors: + * Rickard E. (Rik) Faith <faith@valinux.com> + * Jeff Hartmann <jhartmann@valinux.com> + * Keith Whitwell <keithw@valinux.com> * + * Rewritten by: + * Gareth Hughes <gareth@valinux.com> */ #define __NO_VERSION__ +#include "mga.h" #include "drmP.h" #include "mga_drv.h" -#include <machine/bus.h> -#include <machine/resource.h> -#include <sys/rman.h> -#include <vm/vm.h> -#include <vm/pmap.h> -#define MGA_REG(reg) 2 -#define MGA_BASE(reg) ((unsigned long) \ - ((drm_device_t *)dev)->maplist[MGA_REG(reg)]->handle) -#define MGA_ADDR(reg) (MGA_BASE(reg) + reg) -#define MGA_DEREF(reg) *(__volatile__ int *)MGA_ADDR(reg) -#define MGA_READ(reg) MGA_DEREF(reg) -#define MGA_WRITE(reg,val) do { MGA_DEREF(reg) = val; } while (0) +#define MGA_DEFAULT_USEC_TIMEOUT 10000 +#define MGA_FREELIST_DEBUG 0 -#define PDEA_pagpxfer_enable 0x2 -static int mga_flush_queue(drm_device_t *dev); +/* ================================================================ + * Engine control + */ -static unsigned long mga_alloc_page(drm_device_t *dev) +int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) { - unsigned long address; - - DRM_DEBUG("%s\n", __FUNCTION__); + u32 status = 0; + int i; + DRM_DEBUG( "%s\n", __FUNCTION__ ); - address = (unsigned long) drm_alloc(PAGE_SIZE, DRM_MEM_DMA); - if(address == 0UL) { - return 0; + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; + if ( status == MGA_ENDPRDMASTS ) { + MGA_WRITE8( MGA_CRTC_INDEX, 0 ); + return 0; + } + DRM_OS_DELAY( 1 ); } - - return address; + +#if MGA_DMA_DEBUG + DRM_ERROR( "failed!\n" ); + DRM_INFO( " status=0x%08x\n", status ); +#endif + DRM_OS_RETURN(EBUSY); } -static void mga_free_page(drm_device_t *dev, unsigned long page) +int mga_do_dma_idle( drm_mga_private_t *dev_priv ) { - DRM_DEBUG("%s\n", __FUNCTION__); + u32 status = 0; + int i; + DRM_DEBUG( "%s\n", __FUNCTION__ ); - if(page == 0UL) { - return; + for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { + status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK; + if ( status == MGA_ENDPRDMASTS ) return 0; + DRM_OS_DELAY( 1 ); } - drm_free((void *) page, PAGE_SIZE, DRM_MEM_DMA); - return; -} -static void mga_delay(void) -{ - return; +#if MGA_DMA_DEBUG + DRM_ERROR( "failed! status=0x%08x\n", status ); +#endif + DRM_OS_RETURN(EBUSY); } -void mga_flush_write_combine(void) +int mga_do_dma_reset( drm_mga_private_t *dev_priv ) { - int xchangeDummy; - DRM_DEBUG("%s\n", __FUNCTION__); + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_primary_buffer_t *primary = &dev_priv->prim; - __asm__ volatile(" push %%eax ; xchg %%eax, %0 ; pop %%eax" : : "m" (xchangeDummy)); - __asm__ volatile(" push %%eax ; push %%ebx ; push %%ecx ; push %%edx ;" - " movl $0,%%eax ; cpuid ; pop %%edx ; pop %%ecx ; pop %%ebx ;" - " pop %%eax" : /* no outputs */ : /* no inputs */ ); -} + DRM_DEBUG( "%s\n", __FUNCTION__ ); -/* These are two age tags that will never be sent to - * the hardware */ -#define MGA_BUF_USED 0xffffffff -#define MGA_BUF_FREE 0 + /* The primary DMA stream should look like new right about now. + */ + primary->tail = 0; + primary->space = primary->size; + primary->last_flush = 0; -static int mga_freelist_init(drm_device_t *dev) -{ - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_mga_freelist_t *item; - int i; - - DRM_DEBUG("%s\n", __FUNCTION__); - - dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); - if(dev_priv->head == NULL) return ENOMEM; - memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); - dev_priv->head->age = MGA_BUF_USED; - - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[ i ]; - buf_priv = buf->dev_private; - item = drm_alloc(sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER); - if(item == NULL) return ENOMEM; - memset(item, 0, sizeof(drm_mga_freelist_t)); - item->age = MGA_BUF_FREE; - item->prev = dev_priv->head; - item->next = dev_priv->head->next; - if(dev_priv->head->next != NULL) - dev_priv->head->next->prev = item; - if(item->next == NULL) dev_priv->tail = item; - item->buf = buf; - buf_priv->my_freelist = item; - buf_priv->discard = 0; - dev_priv->head->next = item; - } - - return 0; -} + sarea_priv->last_wrap = 0; -static void mga_freelist_cleanup(drm_device_t *dev) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_mga_freelist_t *item; - drm_mga_freelist_t *prev; + /* FIXME: Reset counters, buffer ages etc... + */ - DRM_DEBUG("%s\n", __FUNCTION__); + /* FIXME: What else do we need to reinitialize? WARP stuff? + */ - item = dev_priv->head; - while(item) { - prev = item; - item = item->next; - drm_free(prev, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); - } - - dev_priv->head = dev_priv->tail = NULL; + return 0; } -/* Frees dispatch lock */ -static __inline void mga_dma_quiescent(drm_device_t *dev) +int mga_do_engine_reset( drm_mga_private_t *dev_priv ) { - drm_device_dma_t *dma = dev->dma; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned long end; - int i; + DRM_DEBUG( "%s\n", __FUNCTION__ ); - DRM_DEBUG("%s\n", __FUNCTION__); - end = ticks + (hz*3); - while(1) { - if(!test_and_set_bit(MGA_IN_DISPATCH, - &dev_priv->dispatch_status)) { - break; - } - if((signed)(end - ticks) <= 0) { - DRM_ERROR("irqs: %d wanted %d\n", - atomic_read(&dev->total_irq), - atomic_read(&dma->total_lost)); - DRM_ERROR("lockup\n"); - return; - } - for (i = 0 ; i < 2000 ; i++) mga_delay(); - } - end = ticks + (hz*3); - DRM_DEBUG("quiescent status : %x\n", MGA_READ(MGAREG_STATUS)); - while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) { - if((signed)(end - ticks) <= 0) { - DRM_ERROR("irqs: %d wanted %d\n", - atomic_read(&dev->total_irq), - atomic_read(&dma->total_lost)); - DRM_ERROR("lockup\n"); - clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); - return; - } - for (i = 0 ; i < 2000 ; i++) mga_delay(); - } - sarea_priv->dirty |= MGA_DMA_FLUSH; + /* Okay, so we've completely screwed up and locked the engine. + * How about we clean up after ourselves? + */ + MGA_WRITE( MGA_RST, MGA_SOFTRESET ); + DRM_OS_DELAY( 15 ); /* Wait at least 10 usecs */ + MGA_WRITE( MGA_RST, 0 ); + + /* Initialize the registers that get clobbered by the soft + * reset. Many of the core register values survive a reset, + * but the drawing registers are basically all gone. + * + * 3D clients should probably die after calling this. The X + * server should reset the engine state to known values. + */ +#if 0 + MGA_WRITE( MGA_PRIMPTR, + virt_to_bus((void *)dev_priv->prim.status_page) | + MGA_PRIMPTREN0 | + MGA_PRIMPTREN1 ); +#endif - clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); - DRM_DEBUG("exit, dispatch_status = 0x%02x\n",dev_priv->dispatch_status); -} + MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR ); + MGA_WRITE( MGA_IEN, MGA_SOFTRAPIEN ); -static void mga_reset_freelist(drm_device_t *dev) -{ - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - int i; + /* The primary DMA stream should look like new right about now. + */ + mga_do_dma_reset( dev_priv ); - for (i = 0; i < dma->buf_count; i++) { - buf = dma->buflist[ i ]; - buf_priv = buf->dev_private; - buf_priv->my_freelist->age = MGA_BUF_FREE; - } + /* This bad boy will never fail. + */ + return 0; } -/* Least recently used : - * These operations are not atomic b/c they are protected by the - * hardware lock */ -drm_buf_t *mga_freelist_get(drm_device_t *dev) +/* ================================================================ + * Primary DMA stream + */ + +void mga_do_dma_flush( drm_mga_private_t *dev_priv ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; - drm_mga_freelist_t *prev; - drm_mga_freelist_t *next; - static int failed = 0; - int ret, s; - - DRM_DEBUG("%s : tail->age : %d last_prim_age : %d\n", __FUNCTION__, - dev_priv->tail->age, dev_priv->last_prim_age); - - if(failed >= 1000 && dev_priv->tail->age >= dev_priv->last_prim_age) { - DRM_DEBUG("I'm waiting on the freelist!!! %d\n", - dev_priv->last_prim_age); - s = splsofttq(); - set_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status); - for (;;) { - mga_dma_schedule(dev, 0); -/* if(!test_bit(MGA_IN_GETBUF, - &dev_priv->dispatch_status)) */ - if(dev_priv->tail->age < dev_priv->last_prim_age) - break; - atomic_inc(&dev->total_sleeps); - ret = tsleep(&dev_priv->buf_queue, PZERO|PCATCH, - "mgafg", 0); - if (ret == EINTR) { - clear_bit(MGA_IN_GETBUF, - &dev_priv->dispatch_status); - break; - } - } - splx(s); - clear_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status); - if (ret) return NULL; - } - - if(dev_priv->tail->age < dev_priv->last_prim_age) { - prev = dev_priv->tail->prev; - next = dev_priv->tail; - prev->next = NULL; - next->prev = next->next = NULL; - dev_priv->tail = prev; - next->age = MGA_BUF_USED; - failed = 0; - return next->buf; + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + u32 head, tail; + DMA_LOCALS; + DRM_DEBUG( "%s:\n", __FUNCTION__ ); + + if ( primary->tail == primary->last_flush ) { + DRM_DEBUG( " bailing out...\n" ); + return; } - failed++; - return NULL; -} + tail = primary->tail + dev_priv->primary->offset; -int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf) -{ - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_freelist_t *prev; - drm_mga_freelist_t *head; - drm_mga_freelist_t *next; + /* We need to pad the stream between flushes, as the card + * actually (partially?) reads the first of these commands. + * See page 4-16 in the G400 manual, middle of the page or so. + */ + BEGIN_DMA( 1 ); - DRM_DEBUG("%s\n", __FUNCTION__); + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); - if(buf_priv->my_freelist->age == MGA_BUF_USED) { - /* Discarded buffer, put it on the tail */ - next = buf_priv->my_freelist; - next->age = MGA_BUF_FREE; - prev = dev_priv->tail; - prev->next = next; - next->prev = prev; - next->next = NULL; - dev_priv->tail = next; - DRM_DEBUG("Discarded\n"); + ADVANCE_DMA(); + + primary->last_flush = primary->tail; + + head = MGA_READ( MGA_PRIMADDRESS ); + + if ( head <= tail ) { + primary->space = primary->size - primary->tail; } else { - /* Normally aged buffer, put it on the head + 1, - * as the real head is a sentinal element - */ - next = buf_priv->my_freelist; - head = dev_priv->head; - prev = head->next; - head->next = next; - prev->prev = next; - next->prev = head; - next->next = prev; + primary->space = head - tail; } - - return 0; -} -static int mga_init_primary_bufs(drm_device_t *dev, drm_mga_init_t *init) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_prim_buf_t *prim_buffer; - int i, temp, size_of_buf; - int offset = init->reserved_map_agpstart; - - DRM_DEBUG("%s\n", __FUNCTION__); - dev_priv->primary_size = ((init->primary_size + PAGE_SIZE - 1) / - PAGE_SIZE) * PAGE_SIZE; - size_of_buf = dev_priv->primary_size / MGA_NUM_PRIM_BUFS; - dev_priv->warp_ucode_size = init->warp_ucode_size; - dev_priv->prim_bufs = drm_alloc(sizeof(drm_mga_prim_buf_t *) * - (MGA_NUM_PRIM_BUFS + 1), - DRM_MEM_DRIVER); - if(dev_priv->prim_bufs == NULL) { - DRM_ERROR("Unable to allocate memory for prim_buf\n"); - return ENOMEM; - } - memset(dev_priv->prim_bufs, - 0, sizeof(drm_mga_prim_buf_t *) * (MGA_NUM_PRIM_BUFS + 1)); - - temp = init->warp_ucode_size + dev_priv->primary_size; - temp = ((temp + PAGE_SIZE - 1) / PAGE_SIZE) * PAGE_SIZE; - - dev_priv->ioremap = drm_ioremap(dev->agp->base + offset, - temp); - if(dev_priv->ioremap == NULL) { - DRM_DEBUG("Ioremap failed\n"); - return ENOMEM; - } - dev_priv->wait_queue = 0; - - for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { - prim_buffer = drm_alloc(sizeof(drm_mga_prim_buf_t), - DRM_MEM_DRIVER); - if(prim_buffer == NULL) return ENOMEM; - memset(prim_buffer, 0, sizeof(drm_mga_prim_buf_t)); - prim_buffer->phys_head = offset + dev->agp->base; - prim_buffer->current_dma_ptr = - prim_buffer->head = - (u_int32_t *) (dev_priv->ioremap + - offset - - init->reserved_map_agpstart); - prim_buffer->num_dwords = 0; - prim_buffer->max_dwords = size_of_buf / sizeof(u_int32_t); - prim_buffer->max_dwords -= 5; /* Leave room for the softrap */ - prim_buffer->sec_used = 0; - prim_buffer->idx = i; - prim_buffer->prim_age = i + 1; - offset = offset + size_of_buf; - dev_priv->prim_bufs[i] = prim_buffer; - } - dev_priv->current_prim_idx = 0; - dev_priv->next_prim = - dev_priv->last_prim = - dev_priv->current_prim = - dev_priv->prim_bufs[0]; - dev_priv->next_prim_age = 2; - dev_priv->last_prim_age = 1; - set_bit(MGA_BUF_IN_USE, &dev_priv->current_prim->buffer_status); - return 0; + DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); + DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); + DRM_DEBUG( " space = 0x%06x\n", primary->space ); + + mga_flush_write_combine(); + MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); + + DRM_DEBUG( "%s: done.\n", __FUNCTION__ ); } -static void mga_fire_primary(drm_device_t *dev, drm_mga_prim_buf_t *prim) +void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) { - drm_mga_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - int use_agp = PDEA_pagpxfer_enable; - unsigned long end; - int i; - int next_idx; - PRIMLOCALS; - - DRM_DEBUG("%s\n", __FUNCTION__); - dev_priv->last_prim = prim; - - /* We never check for overflow, b/c there is always room */ - PRIMPTR(prim); - if(num_dwords <= 0) { - DRM_DEBUG("num_dwords == 0 when dispatched\n"); - goto out_prim_wait; - } - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_SOFTRAP, 0); - PRIMFINISH(prim); - - end = ticks + (hz*3); - if(sarea_priv->dirty & MGA_DMA_FLUSH) { - DRM_DEBUG("Dma top flush\n"); - while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) { - if((signed)(end - ticks) <= 0) { - DRM_ERROR("irqs: %d wanted %d\n", - atomic_read(&dev->total_irq), - atomic_read(&dma->total_lost)); - DRM_ERROR("lockup in fire primary " - "(Dma Top Flush)\n"); - goto out_prim_wait; - } - - for (i = 0 ; i < 4096 ; i++) mga_delay(); - } - sarea_priv->dirty &= ~(MGA_DMA_FLUSH); + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + u32 head, tail; + DMA_LOCALS; + DRM_DEBUG( "%s:\n", __FUNCTION__ ); + + BEGIN_DMA_WRAP(); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); + + tail = primary->tail + dev_priv->primary->offset; + + primary->tail = 0; + primary->last_flush = 0; + primary->last_wrap++; + + head = MGA_READ( MGA_PRIMADDRESS ); + + if ( head == dev_priv->primary->offset ) { + primary->space = primary->size; } else { - DRM_DEBUG("Status wait\n"); - while((MGA_READ(MGAREG_STATUS) & 0x00020001) != 0x00020000) { - if((signed)(end - ticks) <= 0) { - DRM_ERROR("irqs: %d wanted %d\n", - atomic_read(&dev->total_irq), - atomic_read(&dma->total_lost)); - DRM_ERROR("lockup in fire primary " - "(Status Wait)\n"); - goto out_prim_wait; - } - - for (i = 0 ; i < 4096 ; i++) mga_delay(); - } + primary->space = head - dev_priv->primary->offset; } - mga_flush_write_combine(); - atomic_inc(&dev_priv->pending_bufs); - MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); - MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); - prim->num_dwords = 0; - sarea_priv->last_enqueue = prim->prim_age; - - next_idx = prim->idx + 1; - if(next_idx >= MGA_NUM_PRIM_BUFS) - next_idx = 0; - - dev_priv->next_prim = dev_priv->prim_bufs[next_idx]; - return; - - out_prim_wait: - prim->num_dwords = 0; - prim->sec_used = 0; - clear_bit(MGA_BUF_IN_USE, &prim->buffer_status); - wakeup(&dev_priv->wait_queue); - clear_bit(MGA_BUF_SWAP_PENDING, &prim->buffer_status); - clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); + DRM_DEBUG( " head = 0x%06lx\n", + head - dev_priv->primary->offset ); + DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); + DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); + DRM_DEBUG( " space = 0x%06x\n", primary->space ); + + mga_flush_write_combine(); + MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); + + set_bit( 0, &primary->wrapped ); + DRM_DEBUG( "%s: done.\n", __FUNCTION__ ); } -int mga_advance_primary(drm_device_t *dev) +void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) { - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_prim_buf_t *prim_buffer; - drm_device_dma_t *dma = dev->dma; - int next_prim_idx; - int ret = 0; - int s; - - /* This needs to reset the primary buffer if available, - * we should collect stats on how many times it bites - * it's tail */ - DRM_DEBUG("%s\n", __FUNCTION__); - - next_prim_idx = dev_priv->current_prim_idx + 1; - if(next_prim_idx >= MGA_NUM_PRIM_BUFS) - next_prim_idx = 0; - prim_buffer = dev_priv->prim_bufs[next_prim_idx]; - set_bit(MGA_IN_WAIT, &dev_priv->dispatch_status); - - /* In use is cleared in interrupt handler */ - - s = splsofttq(); - if(test_and_set_bit(MGA_BUF_IN_USE, &prim_buffer->buffer_status)) { - for (;;) { - mga_dma_schedule(dev, 0); - if(!test_and_set_bit(MGA_BUF_IN_USE, - &prim_buffer->buffer_status)) - break; - atomic_inc(&dev->total_sleeps); - atomic_inc(&dma->total_missed_sched); - ret = tsleep(&dev_priv->wait_queue, PZERO|PCATCH, - "mgaap", 0); - if (ret) - break; - } - if(ret) { - splx(s); - return ret; - } - } - clear_bit(MGA_IN_WAIT, &dev_priv->dispatch_status); - splx(s); - - /* This primary buffer is now free to use */ - prim_buffer->current_dma_ptr = prim_buffer->head; - prim_buffer->num_dwords = 0; - prim_buffer->sec_used = 0; - prim_buffer->prim_age = dev_priv->next_prim_age++; - if(prim_buffer->prim_age == 0 || prim_buffer->prim_age == 0xffffffff) { - mga_flush_queue(dev); - mga_dma_quiescent(dev); - mga_reset_freelist(dev); - prim_buffer->prim_age = (dev_priv->next_prim_age += 2); - } + drm_mga_primary_buffer_t *primary = &dev_priv->prim; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + u32 head = dev_priv->primary->offset; + DRM_DEBUG( "%s:\n", __FUNCTION__ ); + + sarea_priv->last_wrap++; + DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); - /* Reset all buffer status stuff */ - clear_bit(MGA_BUF_NEEDS_OVERFLOW, &prim_buffer->buffer_status); - clear_bit(MGA_BUF_FORCE_FIRE, &prim_buffer->buffer_status); - clear_bit(MGA_BUF_SWAP_PENDING, &prim_buffer->buffer_status); + mga_flush_write_combine(); + MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); - dev_priv->current_prim = prim_buffer; - dev_priv->current_prim_idx = next_prim_idx; - return 0; + clear_bit( 0, &primary->wrapped ); + DRM_DEBUG( "%s: done.\n", __FUNCTION__ ); } -/* More dynamic performance decisions */ -static __inline int mga_decide_to_fire(drm_device_t *dev) + +/* ================================================================ + * Freelist management + */ + +#define MGA_BUFFER_USED ~0 +#define MGA_BUFFER_FREE 0 + +#if MGA_FREELIST_DEBUG +static void mga_freelist_print( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_freelist_t *entry; + + DRM_INFO( "\n" ); + DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", + dev_priv->sarea_priv->last_dispatch, + (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - + dev_priv->primary->offset) ); + DRM_INFO( "current freelist:\n" ); + + for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { + DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", + entry, entry->buf->idx, entry->age.head, + entry->age.head - dev_priv->primary->offset ); + } + DRM_INFO( "\n" ); +} +#endif - DRM_DEBUG("%s\n", __FUNCTION__); +static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_freelist_t *entry; + int i; + DRM_DEBUG( "%s: count=%d\n", + __FUNCTION__, dma->buf_count ); - if(test_bit(MGA_BUF_FORCE_FIRE, &dev_priv->next_prim->buffer_status)) { - return 1; - } + dev_priv->head = DRM(alloc)( sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER ); + if ( dev_priv->head == NULL ) + DRM_OS_RETURN(ENOMEM); - if (test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status) && - dev_priv->next_prim->num_dwords) { - return 1; - } + memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); + SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); - if (test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) && - dev_priv->next_prim->num_dwords) { - return 1; - } - - if(atomic_read(&dev_priv->pending_bufs) <= MGA_NUM_PRIM_BUFS - 1) { - if(test_bit(MGA_BUF_SWAP_PENDING, - &dev_priv->next_prim->buffer_status)) { - return 1; - } - } + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; - if(atomic_read(&dev_priv->pending_bufs) <= MGA_NUM_PRIM_BUFS / 2) { - if(dev_priv->next_prim->sec_used >= MGA_DMA_BUF_NR / 8) { - return 1; - } - } + entry = DRM(alloc)( sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER ); + if ( entry == NULL ) + DRM_OS_RETURN(ENOMEM); - if(atomic_read(&dev_priv->pending_bufs) >= MGA_NUM_PRIM_BUFS / 2) { - if(dev_priv->next_prim->sec_used >= MGA_DMA_BUF_NR / 4) { - return 1; - } - } + memset( entry, 0, sizeof(drm_mga_freelist_t) ); - return 0; -} + entry->next = dev_priv->head->next; + entry->prev = dev_priv->head; + SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + entry->buf = buf; -int mga_dma_schedule(drm_device_t *dev, int locked) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - int retval =0 ; + if ( dev_priv->head->next != NULL ) + dev_priv->head->next->prev = entry; + if ( entry->next == NULL ) + dev_priv->tail = entry; - if (!dev_priv) return EBUSY; + buf_priv->list_entry = entry; + buf_priv->discard = 0; + buf_priv->dispatched = 0; - if (test_and_set_bit(0, &dev->dma_flag)) { - retval = EBUSY; - goto sch_out_wakeup; - } - - DRM_DEBUG("%s\n", __FUNCTION__); - if (!dev_priv) { - DRM_DEBUG("dev_priv is not set\n"); - return (0); + dev_priv->head->next = entry; } - if(test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) || - test_bit(MGA_IN_WAIT, &dev_priv->dispatch_status) || - test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status)) { - locked = 1; - } - - if (!locked && - !drm_lock_take(&dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) { - clear_bit(0, &dev->dma_flag); - DRM_DEBUG("Not locked\n"); - retval = EBUSY; - goto sch_out_wakeup; - } + return 0; +} - if(!test_and_set_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status)) { - /* Fire dma buffer */ - if(mga_decide_to_fire(dev)) { - clear_bit(MGA_BUF_FORCE_FIRE, - &dev_priv->next_prim->buffer_status); - if(dev_priv->current_prim == dev_priv->next_prim) { - /* Schedule overflow for a later time */ - set_bit(MGA_BUF_NEEDS_OVERFLOW, - &dev_priv->next_prim->buffer_status); - } - mga_fire_primary(dev, dev_priv->next_prim); - } else { - clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); - } - } - - if (!locked) { - if (drm_lock_free(dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - DRM_ERROR("\n"); - } - } - clear_bit(0, &dev->dma_flag); -sch_out_wakeup: - if(test_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status) && - atomic_read(&dev_priv->pending_bufs) == 0) { - /* Everything has been processed by the hardware */ - clear_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status); - wakeup(&dev_priv->flush_queue); - } +static void mga_freelist_cleanup( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_freelist_t *entry; + drm_mga_freelist_t *next; + DRM_DEBUG( "%s\n", __FUNCTION__ ); - if(test_bit(MGA_IN_GETBUF, &dev_priv->dispatch_status) && - dev_priv->tail->age < dev_priv->last_prim_age) - wakeup(&dev_priv->buf_queue); + entry = dev_priv->head; + while ( entry ) { + next = entry->next; + DRM(free)( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); + entry = next; + } - return retval; + dev_priv->head = dev_priv->tail = NULL; } -static void mga_dma_service(void *arg) +#if 0 +/* FIXME: Still needed? + */ +static void mga_freelist_reset( drm_device_t *dev ) { - drm_device_t *dev = (drm_device_t *)arg; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_mga_prim_buf_t *last_prim_buffer; - - atomic_inc(&dev->total_irq); - if((MGA_READ(MGAREG_STATUS) & 0x00000001) != 0x00000001) return; - MGA_WRITE(MGAREG_ICLEAR, 0x00000001); - last_prim_buffer = dev_priv->last_prim; - last_prim_buffer->num_dwords = 0; - last_prim_buffer->sec_used = 0; - dev_priv->sarea_priv->last_dispatch = - dev_priv->last_prim_age = last_prim_buffer->prim_age; - clear_bit(MGA_BUF_IN_USE, &last_prim_buffer->buffer_status); - clear_bit(MGA_BUF_SWAP_PENDING, &last_prim_buffer->buffer_status); - clear_bit(MGA_IN_DISPATCH, &dev_priv->dispatch_status); - atomic_dec(&dev_priv->pending_bufs); - taskqueue_enqueue(taskqueue_swi, &dev->task); - wakeup(&dev_priv->wait_queue); + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + int i; + + for ( i = 0 ; i < dma->buf_count ; i++ ) { + buf = dma->buflist[i]; + buf_priv = buf->dev_private; + SET_AGE( &buf_priv->list_entry->age, + MGA_BUFFER_FREE, 0 ); + } } +#endif -static void mga_dma_task_queue(void *device, int pending) +static drm_buf_t *mga_freelist_get( drm_device_t *dev ) { - DRM_DEBUG("%s\n", __FUNCTION__); - mga_dma_schedule((drm_device_t *)device, 0); + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_freelist_t *next; + drm_mga_freelist_t *prev; + drm_mga_freelist_t *tail = dev_priv->tail; + u32 head, wrap; + DRM_DEBUG( "%s:\n", __FUNCTION__ ); + + head = MGA_READ( MGA_PRIMADDRESS ); + wrap = dev_priv->sarea_priv->last_wrap; + + DRM_DEBUG( " tail=0x%06lx %d\n", + tail->age.head ? + tail->age.head - dev_priv->primary->offset : 0, + tail->age.wrap ); + DRM_DEBUG( " head=0x%06lx %d\n", + head - dev_priv->primary->offset, wrap ); + + if ( TEST_AGE( &tail->age, head, wrap ) ) { + prev = dev_priv->tail->prev; + next = dev_priv->tail; + prev->next = NULL; + next->prev = next->next = NULL; + dev_priv->tail = prev; + SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); + return next->buf; + } + + DRM_DEBUG( "returning NULL!\n" ); + return NULL; } -int mga_dma_cleanup(drm_device_t *dev) +int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) { - DRM_DEBUG("%s\n", __FUNCTION__); - - if(dev->dev_private) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; - - if (dev->irq) mga_flush_queue(dev); - mga_dma_quiescent(dev); - if(dev_priv->ioremap) { - int temp = (dev_priv->warp_ucode_size + - dev_priv->primary_size + - PAGE_SIZE - 1) / PAGE_SIZE * PAGE_SIZE; - - drm_ioremapfree((void *) dev_priv->ioremap, temp); - } - if(dev_priv->real_status_page != 0UL) { - mga_free_page(dev, dev_priv->real_status_page); - } - if(dev_priv->prim_bufs != NULL) { - int i; - for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { - if(dev_priv->prim_bufs[i] != NULL) { - drm_free(dev_priv->prim_bufs[i], - sizeof(drm_mga_prim_buf_t), - DRM_MEM_DRIVER); - } - } - drm_free(dev_priv->prim_bufs, sizeof(void *) * - (MGA_NUM_PRIM_BUFS + 1), - DRM_MEM_DRIVER); - } - if(dev_priv->head != NULL) { - mga_freelist_cleanup(dev); - } + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_freelist_t *head, *entry, *prev; + DRM_DEBUG( "%s: age=0x%06lx wrap=%d\n", + __FUNCTION__, + buf_priv->list_entry->age.head - + dev_priv->primary->offset, + buf_priv->list_entry->age.wrap ); - drm_free(dev->dev_private, sizeof(drm_mga_private_t), - DRM_MEM_DRIVER); - dev->dev_private = NULL; + entry = buf_priv->list_entry; + head = dev_priv->head; + + if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { + SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + prev = dev_priv->tail; + prev->next = entry; + entry->prev = prev; + entry->next = NULL; + } else { + prev = head->next; + head->next = entry; + prev->prev = entry; + entry->prev = head; + entry->next = prev; } return 0; } -static int mga_dma_initialize(drm_device_t *dev, drm_mga_init_t *init) { + +/* ================================================================ + * DMA initialization, cleanup + */ + +static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) +{ drm_mga_private_t *dev_priv; - drm_map_t *sarea_map = NULL; + drm_map_list_entry_t *listentry; + int ret; + DRM_DEBUG( "%s\n", __FUNCTION__ ); - dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); - if(dev_priv == NULL) return ENOMEM; - dev->dev_private = (void *) dev_priv; + dev_priv = DRM(alloc)( sizeof(drm_mga_private_t), DRM_MEM_DRIVER ); + if ( !dev_priv ) + DRM_OS_RETURN(ENOMEM); - memset(dev_priv, 0, sizeof(drm_mga_private_t)); + memset( dev_priv, 0, sizeof(drm_mga_private_t) ); - if((init->reserved_map_idx >= dev->map_count) || - (init->buffer_map_idx >= dev->map_count)) { - mga_dma_cleanup(dev); - DRM_DEBUG("reserved_map or buffer_map are invalid\n"); - return EINVAL; - } - - dev_priv->reserved_map_idx = init->reserved_map_idx; - dev_priv->buffer_map_idx = init->buffer_map_idx; - sarea_map = dev->maplist[0]; - dev_priv->sarea_priv = (drm_mga_sarea_t *) - ((u_int8_t *)sarea_map->handle + - init->sarea_priv_offset); - - /* Scale primary size to the next page */ dev_priv->chipset = init->chipset; - dev_priv->frontOffset = init->frontOffset; - dev_priv->backOffset = init->backOffset; - dev_priv->depthOffset = init->depthOffset; - dev_priv->textureOffset = init->textureOffset; - dev_priv->textureSize = init->textureSize; - dev_priv->cpp = init->cpp; - dev_priv->sgram = init->sgram; - dev_priv->stride = init->stride; - - dev_priv->mAccess = init->mAccess; - dev_priv->flush_queue = 0; - dev_priv->WarpPipe = 0xff000000; - dev_priv->vertexsize = 0; - - DRM_DEBUG("chipset: %d ucode_size: %d backOffset: %x depthOffset: %x\n", - dev_priv->chipset, dev_priv->warp_ucode_size, - dev_priv->backOffset, dev_priv->depthOffset); - DRM_DEBUG("cpp: %d sgram: %d stride: %d maccess: %x\n", - dev_priv->cpp, dev_priv->sgram, dev_priv->stride, - dev_priv->mAccess); - - memcpy(&dev_priv->WarpIndex, &init->WarpIndex, - sizeof(drm_mga_warp_index_t) * MGA_MAX_WARP_PIPES); - - if(mga_init_primary_bufs(dev, init) != 0) { - DRM_ERROR("Can not initialize primary buffers\n"); - mga_dma_cleanup(dev); - return ENOMEM; + + dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; + + if ( init->sgram ) { + dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; + } else { + dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; } - dev_priv->real_status_page = mga_alloc_page(dev); - if(dev_priv->real_status_page == 0UL) { - mga_dma_cleanup(dev); - DRM_ERROR("Can not allocate status page\n"); - return ENOMEM; + dev_priv->maccess = init->maccess; + + dev_priv->fb_cpp = init->fb_cpp; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; + + dev_priv->depth_cpp = init->depth_cpp; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + + /* FIXME: Need to support AGP textures... + */ + dev_priv->texture_offset = init->texture_offset[0]; + dev_priv->texture_size = init->texture_size[0]; + + TAILQ_FOREACH(listentry, dev->maplist, link) { + drm_map_t *map = listentry->map; + if (map->type == _DRM_SHM && + map->flags & _DRM_CONTAINS_LOCK) { + dev_priv->sarea = map; + break; + } } - dev_priv->status_page = (void*)dev_priv->real_status_page; /* XXX wants nocache */ + if(!dev_priv->sarea) { + DRM_ERROR( "failed to find sarea!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + + + DRM_FIND_MAP( dev_priv->fb, init->fb_offset ); + if(!dev_priv->fb) { + DRM_ERROR( "failed to find framebuffer!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); + if(!dev_priv->mmio) { + DRM_ERROR( "failed to find mmio region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + DRM_FIND_MAP( dev_priv->status, init->status_offset ); + if(!dev_priv->status) { + DRM_ERROR( "failed to find status page!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + DRM_FIND_MAP( dev_priv->warp, init->warp_offset ); + if(!dev_priv->warp) { + DRM_ERROR( "failed to find warp microcode region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + DRM_FIND_MAP( dev_priv->primary, init->primary_offset ); + if(!dev_priv->primary) { + DRM_ERROR( "failed to find primary dma region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); + if(!dev_priv->buffers) { + DRM_ERROR( "failed to find dma buffer region!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(EINVAL); + } + + dev_priv->sarea_priv = + (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + + init->sarea_priv_offset); + + DRM_IOREMAP( dev_priv->warp ); + DRM_IOREMAP( dev_priv->primary ); + DRM_IOREMAP( dev_priv->buffers ); + + if(!dev_priv->warp->handle || + !dev_priv->primary->handle || + !dev_priv->buffers->handle ) { + DRM_ERROR( "failed to ioremap agp regions!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(ENOMEM); + } + + ret = mga_warp_install_microcode( dev_priv ); + if ( ret < 0 ) { + DRM_ERROR( "failed to install WARP ucode!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(ret); + } + + ret = mga_warp_init( dev_priv ); + if ( ret < 0 ) { + DRM_ERROR( "failed to init WARP engine!\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(ret); + } + + dev_priv->prim.status = (u32 *)dev_priv->status->handle; + + mga_do_wait_for_idle( dev_priv ); + + /* Init the primary DMA registers. + */ + MGA_WRITE( MGA_PRIMADDRESS, + dev_priv->primary->offset | MGA_DMA_GENERAL ); #if 0 - dev_priv->status_page = - ioremap_nocache(virt_to_bus((void *)dev_priv->real_status_page), - PAGE_SIZE); - - if(dev_priv->status_page == NULL) { - mga_dma_cleanup(dev); - DRM_ERROR("Can not remap status page\n"); - return ENOMEM; - } + MGA_WRITE( MGA_PRIMPTR, + virt_to_bus((void *)dev_priv->prim.status) | + MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ + MGA_PRIMPTREN1 ); /* DWGSYNC */ #endif - /* Write status page when secend or softrap occurs */ - MGA_WRITE(MGAREG_PRIMPTR, - vtophys((void *)dev_priv->real_status_page) | 0x00000003); - - - /* Private is now filled in, initialize the hardware */ - { - PRIMLOCALS; - PRIMGETPTR( dev_priv ); - - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0x0100); - PRIMOUTREG(MGAREG_SOFTRAP, 0); - /* Poll for the first buffer to insure that - * the status register will be correct - */ - - mga_flush_write_combine(); - MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); - - MGA_WRITE(MGAREG_PRIMEND, ((phys_head + num_dwords * 4) | - PDEA_pagpxfer_enable)); - - while(MGA_READ(MGAREG_DWGSYNC) != 0x0100) ; + dev_priv->prim.start = (u8 *)dev_priv->primary->handle; + dev_priv->prim.end = ((u8 *)dev_priv->primary->handle + + dev_priv->primary->size); + dev_priv->prim.size = dev_priv->primary->size; + + dev_priv->prim.tail = 0; + dev_priv->prim.space = dev_priv->prim.size; + dev_priv->prim.wrapped = 0; + + dev_priv->prim.last_flush = 0; + dev_priv->prim.last_wrap = 0; + + dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; + + + dev_priv->prim.status[0] = dev_priv->primary->offset; + dev_priv->prim.status[1] = 0; + + dev_priv->sarea_priv->last_wrap = 0; + dev_priv->sarea_priv->last_frame.head = 0; + dev_priv->sarea_priv->last_frame.wrap = 0; + + if ( mga_freelist_init( dev, dev_priv ) < 0 ) { + DRM_ERROR( "could not initialize freelist\n" ); + /* Assign dev_private so we can do cleanup. */ + dev->dev_private = (void *)dev_priv; + mga_do_cleanup_dma( dev ); + DRM_OS_RETURN(ENOMEM); } - if(mga_freelist_init(dev) != 0) { - DRM_ERROR("Could not initialize freelist\n"); - mga_dma_cleanup(dev); - return ENOMEM; + /* Make dev_private visable to others. */ + dev->dev_private = (void *)dev_priv; + return 0; +} + +int mga_do_cleanup_dma( drm_device_t *dev ) +{ + DRM_DEBUG( "%s\n", __FUNCTION__ ); + + if ( dev->dev_private ) { + drm_mga_private_t *dev_priv = dev->dev_private; + + DRM_IOREMAPFREE( dev_priv->warp ); + DRM_IOREMAPFREE( dev_priv->primary ); + DRM_IOREMAPFREE( dev_priv->buffers ); + + if ( dev_priv->head != NULL ) { + mga_freelist_cleanup( dev ); + } + + DRM(free)( dev->dev_private, sizeof(drm_mga_private_t), + DRM_MEM_DRIVER ); + dev->dev_private = NULL; } + return 0; } -int -mga_dma_init(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) +int mga_dma_init( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; + DRM_OS_DEVICE; drm_mga_init_t init; - - DRM_DEBUG("%s\n", __FUNCTION__); - init = *(drm_mga_init_t *) data; - - switch(init.func) { + DRM_OS_KRNFROMUSR( init, (drm_mga_init_t *) data, sizeof(init) ); + + switch ( init.func ) { case MGA_INIT_DMA: - return mga_dma_initialize(dev, &init); + return mga_do_init_dma( dev, &init ); case MGA_CLEANUP_DMA: - return mga_dma_cleanup(dev); + return mga_do_cleanup_dma( dev ); } - return EINVAL; + DRM_OS_RETURN( EINVAL ); } -int mga_irq_install(drm_device_t *dev, int irq) + +/* ================================================================ + * Primary DMA stream management + */ + +int mga_dma_flush( DRM_OS_IOCTL ) { - int rid; - int retcode; + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_lock_t lock; - if (!irq) return EINVAL; - - lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, curproc); - if (dev->irq) { - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - return EBUSY; - } - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - - DRM_DEBUG("install irq handler %d\n", irq); - - dev->context_flag = 0; - dev->interrupt_flag = 0; - dev->dma_flag = 0; - dev->dma->next_buffer = NULL; - dev->dma->next_queue = NULL; - dev->dma->this_buffer = NULL; - TASK_INIT(&dev->task, 0, mga_dma_task_queue, dev); - - /* Before installing handler */ - MGA_WRITE(MGAREG_IEN, 0); - /* Install handler */ - rid = 0; - dev->irq = bus_alloc_resource(dev->device, SYS_RES_IRQ, &rid, - 0, ~0, 1, RF_SHAREABLE); - if (!dev->irq) - return ENOENT; - - retcode = bus_setup_intr(dev->device, dev->irq, INTR_TYPE_TTY, - mga_dma_service, dev, &dev->irqh); - if (retcode) { - bus_release_resource(dev->device, SYS_RES_IRQ, 0, dev->irq); - dev->irq = 0; - return retcode; - } + LOCK_TEST_WITH_RETURN( dev ); - /* After installing handler */ - MGA_WRITE(MGAREG_ICLEAR, 0x00000001); - MGA_WRITE(MGAREG_IEN, 0x00000001); - return 0; -} + DRM_OS_KRNFROMUSR( lock, (drm_lock_t *) data, sizeof(lock) ); -int mga_irq_uninstall(drm_device_t *dev) -{ - if (!dev->irq) - return EINVAL; - - DRM_DEBUG("remove irq handler %ld\n", rman_get_start(dev->irq)); - MGA_WRITE(MGAREG_ICLEAR, 0x00000001); - MGA_WRITE(MGAREG_IEN, 0); + DRM_DEBUG( "%s: %s%s%s\n", + __FUNCTION__, + (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", + (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", + (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); - bus_teardown_intr(dev->device, dev->irq, dev->irqh); - bus_release_resource(dev->device, SYS_RES_IRQ, 0, dev->irq); - dev->irq = 0; + WRAP_WAIT_WITH_RETURN( dev_priv ); - return 0; -} + if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { + mga_do_dma_flush( dev_priv ); + } -int mga_control(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_control_t ctl; - - ctl = *(drm_control_t *) data; - - DRM_DEBUG("%s\n", __FUNCTION__); - - switch (ctl.func) { - case DRM_INST_HANDLER: - return mga_irq_install(dev, ctl.irq); - case DRM_UNINST_HANDLER: - return mga_irq_uninstall(dev); - default: - return EINVAL; + if ( lock.flags & _DRM_LOCK_QUIESCENT ) { +#if MGA_DMA_DEBUG + int ret = mga_do_wait_for_idle( dev_priv ); + if ( ret ) + DRM_INFO( __FUNCTION__": -EBUSY\n" ); + return ret; +#else + return mga_do_wait_for_idle( dev_priv ); +#endif + } else { + return 0; } } -static int mga_flush_queue(drm_device_t *dev) +int mga_dma_reset( DRM_OS_IOCTL ) { - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - int ret = 0; - int s; - - DRM_DEBUG("%s\n", __FUNCTION__); - - if(!dev_priv) return 0; - - if(dev_priv->next_prim->num_dwords != 0) { - s = splsofttq(); - set_bit(MGA_IN_FLUSH, &dev_priv->dispatch_status); - for (;;) { - mga_dma_schedule(dev, 0); - if (!test_bit(MGA_IN_FLUSH, - &dev_priv->dispatch_status)) - break; - atomic_inc(&dev->total_sleeps); - ret = tsleep(&dev_priv->flush_queue, PZERO|PCATCH, - "mgafq", 0); - if (ret) { - clear_bit(MGA_IN_FLUSH, - &dev_priv->dispatch_status); - break; - } - } - splx(s); - } - return ret; + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + + LOCK_TEST_WITH_RETURN( dev ); + + return mga_do_dma_reset( dev_priv ); } -/* Must be called with the lock held */ -void mga_reclaim_buffers(drm_device_t *dev, pid_t pid) + +/* ================================================================ + * DMA buffer management + */ + +#if 0 +static int mga_dma_get_buffers( drm_device_t *dev, drm_dma_t *d ) { - drm_device_dma_t *dma = dev->dma; - int i; + drm_buf_t *buf; + int i; - if (!dma) return; - if(dev->dev_private == NULL) return; - if(dma->buflist == NULL) return; + for ( i = d->granted_count ; i < d->request_count ; i++ ) { + buf = mga_freelist_get( dev ); + if ( !buf ) + DRM_OS_RETURN( EAGAIN ); - DRM_DEBUG("%s\n", __FUNCTION__); - mga_flush_queue(dev); + buf->pid = current->pid; - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; + if ( DRM_OS_COPYTOUSR( &d->request_indices[i], + &buf->idx, sizeof(buf->idx) ) ) + DRM_OS_RETURN( EFAULT ); + if ( DRM_OS_COPYTOUSR( &d->request_sizes[i], + &buf->total, sizeof(buf->total) ) ) + DRM_OS_RETURN( EFAULT ); - /* Only buffers that need to get reclaimed ever - * get set to free - */ - if (buf->pid == pid && buf_priv) { - if(buf_priv->my_freelist->age == MGA_BUF_USED) - buf_priv->my_freelist->age = MGA_BUF_FREE; - } + d->granted_count++; } + return 0; } +#endif /* 0 */ -int mga_lock(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) +int mga_dma_buffers( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; - int ret = 0; - drm_lock_t lock; + DRM_OS_DEVICE; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_dma_t d; + drm_buf_t *buf; + int i; + int ret = 0; - DRM_DEBUG("%s\n", __FUNCTION__); - lock = *(drm_lock_t *) data; + LOCK_TEST_WITH_RETURN( dev ); - if (lock.context == DRM_KERNEL_CONTEXT) { - DRM_ERROR("Process %d using kernel context %d\n", - p->p_pid, lock.context); - return EINVAL; - } - - DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", - lock.context, p->p_pid, dev->lock.hw_lock->lock, - lock.flags); + DRM_OS_KRNFROMUSR( d, (drm_dma_t *) data, sizeof(d) ); - if (lock.context < 0) { - return EINVAL; - } - - /* Only one queue: + /* Please don't send us buffers. */ - - if (!ret) { - atomic_inc(&dev->lock.lock_queue); - for (;;) { - if (!dev->lock.hw_lock) { - /* Device has been unregistered */ - ret = EINTR; - break; - } - if (drm_lock_take(&dev->lock.hw_lock->lock, - lock.context)) { - dev->lock.pid = p->p_pid; - dev->lock.lock_time = ticks; - atomic_inc(&dev->total_locks); - break; /* Got lock */ - } - - /* Contention */ - atomic_inc(&dev->total_sleeps); - ret = tsleep(&dev->lock.lock_queue, PZERO|PCATCH, - "mgal2", 0); - if (ret) - break; - } - atomic_dec(&dev->lock.lock_queue); + if ( d.send_count != 0 ) { + DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", + DRM_OS_CURRENTPID, d.send_count ); + DRM_OS_RETURN( EINVAL ); } - - if (!ret) { - if (lock.flags & _DRM_LOCK_QUIESCENT) { - DRM_DEBUG("_DRM_LOCK_QUIESCENT\n"); - mga_flush_queue(dev); - mga_dma_quiescent(dev); - } + + /* We'll send you buffers. + */ + if ( d.request_count < 0 || d.request_count > dma->buf_count ) { + DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", + DRM_OS_CURRENTPID, d.request_count, dma->buf_count ); + DRM_OS_RETURN( EINVAL ); } - - if (ret) DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); - return ret; -} - -int mga_flush_ioctl(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_lock_t lock; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - int s; - DRM_DEBUG("%s\n", __FUNCTION__); - lock = *(drm_lock_t *) data; + WRAP_TEST_WITH_RETURN( dev_priv ); - if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_flush_ioctl called without lock held\n"); - return EINVAL; - } + d.granted_count = 0; - if(lock.flags & _DRM_LOCK_FLUSH || lock.flags & _DRM_LOCK_FLUSH_ALL) { - drm_mga_prim_buf_t *temp_buf; - temp_buf = dev_priv->current_prim; - - s = splsofttq(); - if(temp_buf && temp_buf->num_dwords) { - set_bit(MGA_BUF_FORCE_FIRE, &temp_buf->buffer_status); - mga_advance_primary(dev); - } - mga_dma_schedule(dev, 1); - splx(s); - } - if(lock.flags & _DRM_LOCK_QUIESCENT) { - mga_flush_queue(dev); - mga_dma_quiescent(dev); + if ( d.request_count ) { + for ( i = d.granted_count ; i < d.request_count ; i++ ) { + buf = mga_freelist_get( dev ); + if ( !buf ) + DRM_OS_RETURN( EAGAIN ); + + buf->pid = DRM_OS_CURRENTPID; + + if ( DRM_OS_COPYTOUSR( &d.request_indices[i], + &buf->idx, sizeof(buf->idx) ) ) + DRM_OS_RETURN( EFAULT ); + if ( DRM_OS_COPYTOUSR( &d.request_sizes[i], + &buf->total, sizeof(buf->total) ) ) + DRM_OS_RETURN( EFAULT ); + + d.granted_count++; + } + ret = 0; } - return 0; + DRM_OS_KRNTOUSR( (drm_dma_t *) data, d, sizeof(d) ); + + return ret; } diff --git a/bsd/mga/mga_drv.c b/bsd/mga/mga_drv.c index 77d7c440..206a77dc 100644 --- a/bsd/mga/mga_drv.c +++ b/bsd/mga/mga_drv.c @@ -1,6 +1,6 @@ -/* mga_drv.c -- Matrox g200/g400 driver +/* mga_drv.c -- Matrox G200/G400 driver -*- linux-c -*- * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com - * + * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. @@ -11,704 +11,88 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: Rickard E. (Rik) Faith <faith@valinux.com> - * Jeff Hartmann <jhartmann@valinux.com> - * + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: + * Rickard E. (Rik) Faith <faith@valinux.com> + * Gareth Hughes <gareth@valinux.com> */ -#include "drmP.h" -#include "mga_drv.h" +#include <sys/types.h> +#include <sys/bus.h> #include <pci/pcivar.h> +#include <opt_drm_linux.h> -MODULE_DEPEND(mga, drm, 1, 1, 1); -MODULE_DEPEND(mga, agp, 1, 1, 1); - -#define MGA_NAME "mga" -#define MGA_DESC "Matrox g200/g400" -#define MGA_DATE "20000928" -#define MGA_MAJOR 2 -#define MGA_MINOR 0 -#define MGA_PATCHLEVEL 0 - -drm_ctx_t mga_res_ctx; - -static int mga_probe(device_t dev) -{ - const char *s = 0; - - switch (pci_get_devid(dev)) { - case 0x0525102b: - s = "Matrox MGA G400 AGP graphics accelerator"; - break; - - case 0x0521102b: - s = "Matrox MGA G200 AGP graphics accelerator"; - break; - } - - if (s) { - device_set_desc(dev, s); - return 0; - } - - return ENXIO; -} - -static int mga_attach(device_t dev) -{ - return mga_init(dev); -} - -static int mga_detach(device_t dev) -{ - mga_cleanup(dev); - return 0; -} - -static device_method_t mga_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, mga_probe), - DEVMETHOD(device_attach, mga_attach), - DEVMETHOD(device_detach, mga_detach), - - { 0, 0 } -}; - -static driver_t mga_driver = { - "drm", - mga_methods, - sizeof(drm_device_t), -}; - -static devclass_t mga_devclass; -#define MGA_SOFTC(unit) \ - ((drm_device_t *) devclass_get_softc(mga_devclass, unit)) - -DRIVER_MODULE(if_mga, pci, mga_driver, mga_devclass, 0, 0); - -#define CDEV_MAJOR 145 - /* mga_drv.c */ -static struct cdevsw mga_cdevsw = { - /* open */ mga_open, - /* close */ mga_close, - /* read */ drm_read, - /* write */ drm_write, - /* ioctl */ mga_ioctl, - /* poll */ drm_poll, - /* mmap */ drm_mmap, - /* strategy */ nostrategy, - /* name */ "mga", - /* maj */ CDEV_MAJOR, - /* dump */ nodump, - /* psize */ nopsize, - /* flags */ D_TTY | D_TRACKCLOSE, - /* bmaj */ -1 -}; - -static drm_ioctl_desc_t mga_ioctls[] = { - [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { mga_version, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { mga_control, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { mga_addbufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { mga_markbufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { mga_infobufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { mga_mapbufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { mga_freebufs, 1, 0 }, +#include "mga.h" +#include "drmP.h" +#include "mga_drv.h" - [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { mga_addctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { mga_rmctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { mga_modctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { mga_getctx, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { mga_switchctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { mga_newctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { mga_resctx, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, +#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." - [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma, 1, 0 }, +#define DRIVER_NAME "mga" +#define DRIVER_DESC "Matrox G200/G400" +#define DRIVER_DATE "20010321" - [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { mga_lock, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { mga_unlock, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, +#define DRIVER_MAJOR 3 +#define DRIVER_MINOR 0 +#define DRIVER_PATCHLEVEL 2 - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_swap_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_clear_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_iload, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_flush_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_indices, 1, 0 }, +/* List acquired from http://www.yourvote.com/pci/pcihdr.h and xc/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h + * Please report to anholt@teleport.com inaccuracies or if a chip you have works that is marked unsupported here. + */ +drm_chipinfo_t DRM(devicelist)[] = { + {0x102b, 0x0520, 0, "Matrox G200 (PCI)"}, + {0x102b, 0x0521, 1, "Matrox G200 (AGP)"}, + {0x102b, 0x0525, 1, "Matrox G400 (AGP)"}, + {0, 0, 0, NULL} }; -#define MGA_IOCTL_COUNT DRM_ARRAY_SIZE(mga_ioctls) - -static int mga_setup(drm_device_t *dev) -{ - int i; - - device_busy(dev->device); - - atomic_set(&dev->ioctl_count, 0); - atomic_set(&dev->vma_count, 0); - dev->buf_use = 0; - atomic_set(&dev->buf_alloc, 0); - - drm_dma_setup(dev); - - atomic_set(&dev->total_open, 0); - atomic_set(&dev->total_close, 0); - atomic_set(&dev->total_ioctl, 0); - atomic_set(&dev->total_irq, 0); - atomic_set(&dev->total_ctx, 0); - atomic_set(&dev->total_locks, 0); - atomic_set(&dev->total_unlocks, 0); - atomic_set(&dev->total_contends, 0); - atomic_set(&dev->total_sleeps, 0); - - for (i = 0; i < DRM_HASH_SIZE; i++) { - dev->magiclist[i].head = NULL; - dev->magiclist[i].tail = NULL; - } - dev->maplist = NULL; - dev->map_count = 0; - dev->vmalist = NULL; - dev->lock.hw_lock = NULL; - dev->lock.lock_queue = 0; - dev->queue_count = 0; - dev->queue_reserved = 0; - dev->queue_slots = 0; - dev->queuelist = NULL; - dev->irq = 0; - dev->context_flag = 0; - dev->interrupt_flag = 0; - dev->dma_flag = 0; - dev->last_context = 0; - dev->last_switch = 0; - dev->last_checked = 0; - callout_init(&dev->timer); - dev->context_wait = 0; - - timespecclear(&dev->ctx_start); - timespecclear(&dev->lck_start); - - dev->buf_rp = dev->buf; - dev->buf_wp = dev->buf; - dev->buf_end = dev->buf + DRM_BSZ; - bzero(&dev->buf_sel, sizeof dev->buf_sel); - dev->buf_sigio = NULL; - dev->buf_readers = 0; - dev->buf_writers = 0; - dev->buf_selecting = 0; - - DRM_DEBUG("\n"); - - /* The kernel's context could be created here, but is now created - in drm_dma_enqueue. This is more resource-efficient for - hardware that does not do DMA, but may mean that - drm_select_queue fails between the time the interrupt is - initialized and the time the queues are initialized. */ - - return 0; -} - - -static int mga_takedown(drm_device_t *dev) -{ - int i; - drm_magic_entry_t *pt, *next; - drm_map_t *map; - drm_vma_entry_t *vma, *vma_next; - - DRM_DEBUG("\n"); - - if (dev->irq) mga_irq_uninstall(dev); - - lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, curproc); - callout_stop(&dev->timer); - - if (dev->devname) { - drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); - dev->devname = NULL; - } - - if (dev->unique) { - drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); - dev->unique = NULL; - dev->unique_len = 0; - } - /* Clear pid list */ - for (i = 0; i < DRM_HASH_SIZE; i++) { - for (pt = dev->magiclist[i].head; pt; pt = next) { - next = pt->next; - drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); - } - dev->magiclist[i].head = dev->magiclist[i].tail = NULL; - } - /* Clear AGP information */ - if (dev->agp) { - drm_agp_mem_t *entry; - drm_agp_mem_t *nexte; - - /* Remove AGP resources, but leave dev->agp - intact until cleanup is called. */ - for (entry = dev->agp->memory; entry; entry = nexte) { - nexte = entry->next; - if (entry->bound) drm_unbind_agp(entry->handle); - drm_free_agp(entry->handle, entry->pages); - drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); - } - dev->agp->memory = NULL; - - if (dev->agp->acquired) - agp_release(dev->agp->agpdev); - - dev->agp->acquired = 0; - dev->agp->enabled = 0; - } - /* Clear vma list (only built for debugging) */ - if (dev->vmalist) { - for (vma = dev->vmalist; vma; vma = vma_next) { - vma_next = vma->next; - drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); - } - dev->vmalist = NULL; - } - - /* Clear map area and mtrr information */ - if (dev->maplist) { - for (i = 0; i < dev->map_count; i++) { - map = dev->maplist[i]; - switch (map->type) { - case _DRM_REGISTERS: - case _DRM_FRAME_BUFFER: -#ifdef CONFIG_MTRR - if (map->mtrr >= 0) { - int retcode; - retcode = mtrr_del(map->mtrr, - map->offset, - map->size); - DRM_DEBUG("mtrr_del = %d\n", retcode); - } -#endif - drm_ioremapfree(map->handle, map->size); - break; - case _DRM_SHM: - drm_free_pages((unsigned long)map->handle, - drm_order(map->size) - - PAGE_SHIFT, - DRM_MEM_SAREA); - break; - case _DRM_AGP: - break; - } - drm_free(map, sizeof(*map), DRM_MEM_MAPS); - } - drm_free(dev->maplist, - dev->map_count * sizeof(*dev->maplist), - DRM_MEM_MAPS); - dev->maplist = NULL; - dev->map_count = 0; - } - - if (dev->queuelist) { - for (i = 0; i < dev->queue_count; i++) { - drm_waitlist_destroy(&dev->queuelist[i]->waitlist); - if (dev->queuelist[i]) { - drm_free(dev->queuelist[i], - sizeof(*dev->queuelist[0]), - DRM_MEM_QUEUES); - dev->queuelist[i] = NULL; - } - } - drm_free(dev->queuelist, - dev->queue_slots * sizeof(*dev->queuelist), - DRM_MEM_QUEUES); - dev->queuelist = NULL; - } - - drm_dma_takedown(dev); - - dev->queue_count = 0; - if (dev->lock.hw_lock) { - dev->lock.hw_lock = NULL; /* SHM removed */ - dev->lock.pid = 0; - wakeup(&dev->lock.lock_queue); - } - lockmgr(&dev->dev_lock, LK_RELEASE, 0, curproc); - - return 0; -} - -/* mga_init is called via mga_attach at module load time, */ - -int -mga_init(device_t nbdev) -{ - int retcode; - drm_device_t *dev = device_get_softc(nbdev); - - DRM_DEBUG("\n"); - - memset((void *)dev, 0, sizeof(*dev)); - simple_lock_init(&dev->count_lock); - lockinit(&dev->dev_lock, PZERO, "drmlk", 0, 0); - -#if 0 - drm_parse_options(mga); -#endif - dev->device = nbdev; - dev->devnode = make_dev(&mga_cdevsw, - device_get_unit(nbdev), - DRM_DEV_UID, - DRM_DEV_GID, - DRM_DEV_MODE, - MGA_NAME); - dev->name = MGA_NAME; - - DRM_DEBUG("doing mem init\n"); - drm_mem_init(); - DRM_DEBUG("doing proc init\n"); - drm_sysctl_init(dev); - TAILQ_INIT(&dev->files); - DRM_DEBUG("doing agp init\n"); - dev->agp = drm_agp_init(); - if(dev->agp == NULL) { - DRM_INFO("The mga drm module requires the agp module" - " to function correctly\nPlease load the agp" - " module before you load the mga module\n"); - drm_sysctl_cleanup(dev); - mga_takedown(dev); - return ENOMEM; - } -#if 0 - dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, - dev->agp->agp_info.aper_size * 1024 * 1024, - MTRR_TYPE_WRCOMB, - 1); -#endif - DRM_DEBUG("doing ctxbitmap init\n"); - if((retcode = drm_ctxbitmap_init(dev))) { - DRM_ERROR("Cannot allocate memory for context bitmap.\n"); - drm_sysctl_cleanup(dev); - mga_takedown(dev); - return retcode; - } - - DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", - MGA_NAME, - MGA_MAJOR, - MGA_MINOR, - MGA_PATCHLEVEL, - MGA_DATE, - device_get_unit(nbdev)); - - return 0; -} - -/* mga_cleanup is called via cleanup_module at module unload time. */ - -void mga_cleanup(device_t nbdev) -{ - drm_device_t *dev = device_get_softc(nbdev); - - DRM_DEBUG("\n"); - - drm_sysctl_cleanup(dev); - destroy_dev(dev->devnode); - - DRM_INFO("Module unloaded\n"); - drm_ctxbitmap_cleanup(dev); - mga_dma_cleanup(dev); -#if 0 - if(dev->agp && dev->agp->agp_mtrr) { - int retval; - retval = mtrr_del(dev->agp->agp_mtrr, - dev->agp->agp_info.aper_base, - dev->agp->agp_info.aper_size * 1024*1024); - DRM_DEBUG("mtrr_del = %d\n", retval); - } -#endif - - mga_takedown(dev); - if (dev->agp) { - drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); - dev->agp = NULL; - } -} - -int -mga_version(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_version_t version; - int len; - - version = *(drm_version_t *) data; - -#define DRM_COPY(name,value) \ - len = strlen(value); \ - if (len > name##_len) len = name##_len; \ - name##_len = strlen(value); \ - if (len && name) { \ - int error = copyout(value, name, len); \ - if (error) return error; \ - } - - version.version_major = MGA_MAJOR; - version.version_minor = MGA_MINOR; - version.version_patchlevel = MGA_PATCHLEVEL; - - DRM_COPY(version.name, MGA_NAME); - DRM_COPY(version.date, MGA_DATE); - DRM_COPY(version.desc, MGA_DESC); - - *(drm_version_t *) data = version; - return 0; -} - -int -mga_open(dev_t kdev, int flags, int fmt, struct proc *p) -{ - drm_device_t *dev = MGA_SOFTC(minor(kdev)); - int retcode = 0; - - DRM_DEBUG("open_count = %d\n", dev->open_count); - - device_busy(dev->device); - if (!(retcode = drm_open_helper(kdev, flags, fmt, p, dev))) { - atomic_inc(&dev->total_open); - simple_lock(&dev->count_lock); - if (!dev->open_count++) { - simple_unlock(&dev->count_lock); - retcode = mga_setup(dev); - } - simple_unlock(&dev->count_lock); - } - device_unbusy(dev->device); - - return retcode; -} - -int -mga_close(dev_t kdev, int flags, int fmt, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_file_t *priv; - int retcode = 0; - - DRM_DEBUG("pid = %d, open_count = %d\n", - p->p_pid, dev->open_count); - - priv = drm_find_file_by_proc(dev, p); - if (!priv) { - DRM_DEBUG("can't find authenticator\n"); - return EINVAL; - } - - if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) - && dev->lock.pid == p->p_pid) { - mga_reclaim_buffers(dev, priv->pid); - DRM_ERROR("Process %d dead, freeing lock for context %d\n", - p->p_pid, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - drm_lock_free(dev, - &dev->lock.hw_lock->lock, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - - /* FIXME: may require heavy-handed reset of - hardware at this point, possibly - processed via a callback to the X - server. */ - } else if (dev->lock.hw_lock) { - /* The lock is required to reclaim buffers */ - for (;;) { - if (!dev->lock.hw_lock) { - /* Device has been unregistered */ - retcode = EINTR; - break; - } - if (drm_lock_take(&dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - dev->lock.pid = p->p_pid; - dev->lock.lock_time = ticks; - atomic_inc(&dev->total_locks); - break; /* Got lock */ - } - /* Contention */ - atomic_inc(&dev->total_sleeps); - retcode = tsleep(&dev->lock.lock_queue, - PZERO|PCATCH, - "drmlk2", - 0); - if (retcode) - break; - } - if(!retcode) { - mga_reclaim_buffers(dev, priv->pid); - drm_lock_free(dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT); - } - } - funsetown(dev->buf_sigio); - - lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, p); - priv = drm_find_file_by_proc(dev, p); - if (priv) { - priv->refs--; - if (!priv->refs) { - TAILQ_REMOVE(&dev->files, priv, link); - drm_free(priv, sizeof(*priv), DRM_MEM_FILES); - } - } - lockmgr(&dev->dev_lock, LK_RELEASE, 0, p); - - atomic_inc(&dev->total_close); - simple_lock(&dev->count_lock); - if (!--dev->open_count) { - if (atomic_read(&dev->ioctl_count) || dev->blocked) { - DRM_ERROR("Device busy: %d %d\n", - atomic_read(&dev->ioctl_count), - dev->blocked); - simple_unlock(&dev->count_lock); - return EBUSY; - } - simple_unlock(&dev->count_lock); - device_unbusy(dev->device); - return mga_takedown(dev); - } - simple_unlock(&dev->count_lock); - return retcode; -} - - -/* mga_ioctl is called whenever a process performs an ioctl on /dev/drm. */ - -int -mga_ioctl(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - int nr = DRM_IOCTL_NR(cmd); - drm_device_t *dev = kdev->si_drv1; - drm_file_t *priv; - int retcode = 0; - drm_ioctl_desc_t *ioctl; - d_ioctl_t *func; - - DRM_DEBUG("dev=%p\n", dev); - priv = drm_find_file_by_proc(dev, p); - if (!priv) { - DRM_DEBUG("can't find authenticator\n"); - return EINVAL; - } - - atomic_inc(&dev->ioctl_count); - atomic_inc(&dev->total_ioctl); - ++priv->ioctl_count; - - DRM_DEBUG("pid = %d, cmd = 0x%02lx, nr = 0x%02x, auth = %d\n", - p->p_pid, cmd, nr, priv->authenticated); - - switch (cmd) { - case FIONBIO: - atomic_dec(&dev->ioctl_count); - return 0; - - case FIOASYNC: - atomic_dec(&dev->ioctl_count); - dev->flags |= FASYNC; - return 0; - - case FIOSETOWN: - atomic_dec(&dev->ioctl_count); - return fsetown(*(int *)data, &dev->buf_sigio); - - case FIOGETOWN: - atomic_dec(&dev->ioctl_count); - *(int *) data = fgetown(dev->buf_sigio); - return 0; - } - - if (nr >= MGA_IOCTL_COUNT) { - retcode = EINVAL; - } else { - ioctl = &mga_ioctls[nr]; - func = ioctl->func; - - if (!func) { - DRM_DEBUG("no function\n"); - retcode = EINVAL; - } else if ((ioctl->root_only && suser(p)) - || (ioctl->auth_needed && !priv->authenticated)) { - retcode = EACCES; - } else { - retcode = (func)(kdev, cmd, data, flags, p); - } - } - - atomic_dec(&dev->ioctl_count); - return retcode; -} - -int -mga_unlock(dev_t kdev, u_long cmd, caddr_t data, int flags, struct proc *p) -{ - drm_device_t *dev = kdev->si_drv1; - drm_lock_t lock; - int s; - - lock = *(drm_lock_t *) data; - - if (lock.context == DRM_KERNEL_CONTEXT) { - DRM_ERROR("Process %d using kernel context %d\n", - p->p_pid, lock.context); - return EINVAL; - } - - DRM_DEBUG("%d frees lock (%d holds)\n", - lock.context, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - atomic_inc(&dev->total_unlocks); - if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) - atomic_inc(&dev->total_contends); - drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); - - s = splsofttq(); - mga_dma_schedule(dev, 1); - splx(s); - - if (drm_lock_free(dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - DRM_ERROR("\n"); - } - - return 0; -} +#define DRIVER_IOCTLS \ + [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma_buffers, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_dma_flush, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_RESET)] = { mga_dma_reset, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_dma_swap, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_dma_clear, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, \ + [DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, + + +#define __HAVE_COUNTERS 3 +#define __HAVE_COUNTER6 _DRM_STAT_IRQ +#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY +#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY + + +#include "drm_agpsupport.h" +#include "drm_auth.h" +#include "drm_bufs.h" +#include "drm_context.h" +#include "drm_dma.h" +#include "drm_drawable.h" +#include "drm_drv.h" + + +#include "drm_fops.h" +#include "drm_init.h" +#include "drm_ioctl.h" +#include "drm_lock.h" +#include "drm_memory.h" +#include "drm_vm.h" +#include "drm_sysctl.h" + +DRIVER_MODULE(mga, pci, mga_driver, mga_devclass, 0, 0); diff --git a/bsd/mga/mga_drv.h b/bsd/mga/mga_drv.h index 9e51a20d..be207e30 100644 --- a/bsd/mga/mga_drv.h +++ b/bsd/mga/mga_drv.h @@ -1,4 +1,4 @@ -/* mga_drv.h -- Private header for the Matrox g200/g400 driver +/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -11,163 +11,157 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: Rickard E. (Rik) Faith <faith@valinux.com> - * Jeff Hartmann <jhartmann@valinux.com> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: + * Gareth Hughes <gareth@valinux.com> */ -#ifndef _MGA_DRV_H_ -#define _MGA_DRV_H_ +#ifndef __MGA_DRV_H__ +#define __MGA_DRV_H__ -#define MGA_BUF_IN_USE 0 -#define MGA_BUF_SWAP_PENDING 1 -#define MGA_BUF_FORCE_FIRE 2 -#define MGA_BUF_NEEDS_OVERFLOW 3 +#ifndef u8 +#define u8 u_int8_t +#define u16 u_int16_t +#define u32 u_int32_t +#endif -typedef struct { - u_int32_t buffer_status; - int num_dwords; - int max_dwords; - u_int32_t *current_dma_ptr; - u_int32_t *head; - u_int32_t phys_head; - unsigned int prim_age; - int sec_used; - int idx; -} drm_mga_prim_buf_t; - -typedef struct _drm_mga_freelist { - __volatile__ unsigned int age; +typedef struct drm_mga_primary_buffer { + u8 *start; + u8 *end; + int size; + + u32 tail; + int space; + volatile long wrapped; + + volatile u32 *status; + + u32 last_flush; + u32 last_wrap; + + u32 high_mark; + + spinlock_t list_lock; +} drm_mga_primary_buffer_t; + +typedef struct drm_mga_freelist { + struct drm_mga_freelist *next; + struct drm_mga_freelist *prev; + drm_mga_age_t age; drm_buf_t *buf; - struct _drm_mga_freelist *next; - struct _drm_mga_freelist *prev; } drm_mga_freelist_t; -#define MGA_IN_DISPATCH 0 -#define MGA_IN_FLUSH 1 -#define MGA_IN_WAIT 2 -#define MGA_IN_GETBUF 3 - -typedef struct _drm_mga_private { - u_int32_t dispatch_status; - unsigned int next_prim_age; - __volatile__ unsigned int last_prim_age; - int reserved_map_idx; - int buffer_map_idx; - drm_mga_sarea_t *sarea_priv; - int primary_size; - int warp_ucode_size; - int chipset; - unsigned int frontOffset; - unsigned int backOffset; - unsigned int depthOffset; - unsigned int textureOffset; - unsigned int textureSize; - int cpp; - unsigned int stride; - int sgram; - int use_agp; - drm_mga_warp_index_t WarpIndex[MGA_MAX_G400_PIPES]; - unsigned int WarpPipe; - unsigned int vertexsize; - atomic_t pending_bufs; - void *status_page; - unsigned long real_status_page; - u_int8_t *ioremap; - drm_mga_prim_buf_t **prim_bufs; - drm_mga_prim_buf_t *next_prim; - drm_mga_prim_buf_t *last_prim; - drm_mga_prim_buf_t *current_prim; - int current_prim_idx; +typedef struct { + drm_mga_freelist_t *list_entry; + int discard; + int dispatched; +} drm_mga_buf_priv_t; + +typedef struct drm_mga_private { + drm_mga_primary_buffer_t prim; + drm_mga_sarea_t *sarea_priv; + drm_mga_freelist_t *head; drm_mga_freelist_t *tail; - int flush_queue; /* Processes waiting until flush */ - int wait_queue; /* Processes waiting until interrupt */ - int buf_queue; /* Processes waiting for a free buf */ - /* Some validated register values: - */ - u_int32_t mAccess; -} drm_mga_private_t; - /* mga_drv.c */ -extern int mga_init(device_t); -extern void mga_cleanup(device_t); -extern d_ioctl_t mga_version; -extern d_open_t mga_open; -extern d_close_t mga_close; -extern d_ioctl_t mga_ioctl; -extern d_ioctl_t mga_unlock; + unsigned int warp_pipe; + unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; + + int chipset; + int usec_timeout; + + u32 clear_cmd; + u32 maccess; + + unsigned int fb_cpp; + unsigned int front_offset; + unsigned int front_pitch; + unsigned int back_offset; + unsigned int back_pitch; + + unsigned int depth_cpp; + unsigned int depth_offset; + unsigned int depth_pitch; + + unsigned int texture_offset; + unsigned int texture_size; + + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *status; + drm_map_t *warp; + drm_map_t *primary; + drm_map_t *buffers; + drm_map_t *agp_textures; +} drm_mga_private_t; /* mga_dma.c */ -extern int mga_dma_schedule(drm_device_t *dev, int locked); -extern int mga_irq_install(drm_device_t *dev, int irq); -extern int mga_irq_uninstall(drm_device_t *dev); -extern d_ioctl_t mga_dma; -extern d_ioctl_t mga_control; -extern d_ioctl_t mga_lock; - -/* mga_dma_init does init and release */ -extern int mga_dma_cleanup(drm_device_t *dev); -extern d_ioctl_t mga_dma_init; -extern d_ioctl_t mga_flush_ioctl; -extern void mga_flush_write_combine(void); -extern unsigned int mga_create_sync_tag(drm_device_t *dev); -extern drm_buf_t *mga_freelist_get(drm_device_t *dev); -extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf); -extern int mga_advance_primary(drm_device_t *dev); -extern void mga_reclaim_buffers(drm_device_t *dev, pid_t pid); - - /* mga_bufs.c */ -extern d_ioctl_t mga_addbufs; -extern d_ioctl_t mga_infobufs; -extern d_ioctl_t mga_markbufs; -extern d_ioctl_t mga_freebufs; -extern d_ioctl_t mga_mapbufs; -extern d_ioctl_t mga_addmap; - /* mga_state.c */ -extern d_ioctl_t mga_clear_bufs; -extern d_ioctl_t mga_swap_bufs; -extern d_ioctl_t mga_iload; -extern d_ioctl_t mga_vertex; -extern d_ioctl_t mga_indices; - /* mga_context.c */ -extern d_ioctl_t mga_resctx; -extern d_ioctl_t mga_addctx; -extern d_ioctl_t mga_modctx; -extern d_ioctl_t mga_getctx; -extern d_ioctl_t mga_switchctx; -extern d_ioctl_t mga_newctx; -extern d_ioctl_t mga_rmctx; - -extern int mga_context_switch(drm_device_t *dev, int old, int new); -extern int mga_context_switch_complete(drm_device_t *dev, int new); - - -typedef enum { - TT_GENERAL, - TT_BLIT, - TT_VECTOR, - TT_VERTEX -} transferType_t; +extern int mga_dma_init( DRM_OS_IOCTL ); +extern int mga_dma_flush( DRM_OS_IOCTL ); +extern int mga_dma_reset( DRM_OS_IOCTL ); +extern int mga_dma_buffers( DRM_OS_IOCTL ); -typedef struct { - drm_mga_freelist_t *my_freelist; - int discard; - int dispatched; -} drm_mga_buf_priv_t; +extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); +extern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); +extern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); +extern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); +extern int mga_do_cleanup_dma( drm_device_t *dev ); + +extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); +extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); +extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); + +extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); + + /* mga_state.c */ +extern int mga_dma_clear( DRM_OS_IOCTL ); +extern int mga_dma_swap( DRM_OS_IOCTL ); +extern int mga_dma_vertex( DRM_OS_IOCTL ); +extern int mga_dma_indices( DRM_OS_IOCTL ); +extern int mga_dma_iload( DRM_OS_IOCTL ); +extern int mga_dma_blit( DRM_OS_IOCTL ); + + /* mga_warp.c */ +extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); +extern int mga_warp_init( drm_mga_private_t *dev_priv ); + +#define mga_flush_write_combine() DRM_OS_READMEMORYBARRIER + +#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) +#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) + +#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) +#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) + +#ifdef __alpha__ +#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) +#define MGA_WRITE( reg, val ) do { wmb(); MGA_DEREF( reg ) = val; } while (0) +#define MGA_WRITE8( reg, val ) do { wmb(); MGA_DEREF8( reg ) = val; } while (0) + +static inline u32 _MGA_READ(u32 *addr) +{ + mb(); + return *(volatile u32 *)addr; +} + +#else +#define MGA_READ( reg ) MGA_DEREF( reg ) +#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0) +#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0) +#endif #define DWGREG0 0x1c00 #define DWGREG0_END 0x1dff @@ -175,322 +169,470 @@ typedef struct { #define DWGREG1_END 0x2dff #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) -#define ADRINDEX0(r) (u_int8_t)((r - DWGREG0) >> 2) -#define ADRINDEX1(r) (u_int8_t)(((r - DWGREG1) >> 2) | 0x80) -#define ADRINDEX(r) (ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r)) - -#define MGA_VERBOSE 0 -#define MGA_NUM_PRIM_BUFS 8 - -#define PRIMLOCALS u_int8_t tempIndex[4]; u_int32_t *dma_ptr; u_int32_t phys_head; \ - int outcount, num_dwords - -#define PRIM_OVERFLOW(dev, dev_priv, length) do { \ - drm_mga_prim_buf_t *tmp_buf = \ - dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ - if( test_bit(MGA_BUF_NEEDS_OVERFLOW, \ - &tmp_buf->buffer_status)) { \ - mga_advance_primary(dev); \ - mga_dma_schedule(dev, 1); \ - tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ - } else if( tmp_buf->max_dwords - tmp_buf->num_dwords < length ||\ - tmp_buf->sec_used > MGA_DMA_BUF_NR/2) { \ - set_bit(MGA_BUF_FORCE_FIRE, &tmp_buf->buffer_status); \ - mga_advance_primary(dev); \ - mga_dma_schedule(dev, 1); \ - tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ +#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) +#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) +#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) + + + +/* ================================================================ + * Helper macross... + */ + +#define MGA_EMIT_STATE( dev_priv, dirty ) \ +do { \ + if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ + if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ + mga_g400_emit_state( dev_priv ); \ + } else { \ + mga_g200_emit_state( dev_priv ); \ + } \ } \ - if(MGA_VERBOSE) \ - DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ - dma_ptr = tmp_buf->current_dma_ptr; \ - num_dwords = tmp_buf->num_dwords; \ - phys_head = tmp_buf->phys_head; \ - outcount = 0; \ -} while(0) - -#define PRIMGETPTR(dev_priv) do { \ - drm_mga_prim_buf_t *tmp_buf = \ - dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ - if(MGA_VERBOSE) \ - DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ - dma_ptr = tmp_buf->current_dma_ptr; \ - num_dwords = tmp_buf->num_dwords; \ - phys_head = tmp_buf->phys_head; \ - outcount = 0; \ -} while(0) - -#define PRIMPTR(prim_buf) do { \ - if(MGA_VERBOSE) \ - DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__); \ - dma_ptr = prim_buf->current_dma_ptr; \ - num_dwords = prim_buf->num_dwords; \ - phys_head = prim_buf->phys_head; \ - outcount = 0; \ -} while(0) - -#define PRIMFINISH(prim_buf) do { \ - if (MGA_VERBOSE) { \ - DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__); \ - if (outcount & 3) \ - DRM_DEBUG(" --- truncation\n"); \ - } \ - prim_buf->num_dwords = num_dwords; \ - prim_buf->current_dma_ptr = dma_ptr; \ -} while(0) - -#define PRIMADVANCE(dev_priv) do { \ -drm_mga_prim_buf_t *tmp_buf = \ - dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ - if (MGA_VERBOSE) { \ - DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__); \ - if (outcount & 3) \ - DRM_DEBUG(" --- truncation\n"); \ - } \ - tmp_buf->num_dwords = num_dwords; \ - tmp_buf->current_dma_ptr = dma_ptr; \ } while (0) -#define PRIMUPDATE(dev_priv) do { \ - drm_mga_prim_buf_t *tmp_buf = \ - dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ - tmp_buf->sec_used++; \ +#define LOCK_TEST_WITH_RETURN( dev ) \ +do { \ + if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ + dev->lock.pid != DRM_OS_CURRENTPID ) { \ + DRM_ERROR( "%s called without lock held\n", \ + __FUNCTION__ ); \ + DRM_OS_RETURN( EINVAL ); \ + } \ } while (0) -#define AGEBUF(dev_priv, buf_priv) do { \ - drm_mga_prim_buf_t *tmp_buf = \ - dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ - buf_priv->my_freelist->age = tmp_buf->prim_age; \ +#define WRAP_TEST_WITH_RETURN( dev_priv ) \ +do { \ + if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ + if ( mga_is_idle( dev_priv ) ) { \ + mga_do_dma_wrap_end( dev_priv ); \ + } else if ( dev_priv->prim.space < \ + dev_priv->prim.high_mark ) { \ + if ( MGA_DMA_DEBUG ) \ + DRM_INFO( __FUNCTION__": wrap...\n" ); \ + DRM_OS_RETURN( EBUSY); \ + } \ + } \ } while (0) +#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ +do { \ + if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ + if ( mga_do_wait_for_idle( dev_priv ) ) { \ + if ( MGA_DMA_DEBUG ) \ + DRM_INFO( __FUNCTION__": wrap...\n" ); \ + DRM_OS_RETURN( EBUSY); \ + } \ + mga_do_dma_wrap_end( dev_priv ); \ + } \ +} while (0) + + +/* ================================================================ + * Primary DMA command stream + */ + +#define MGA_VERBOSE 0 -#define PRIMOUTREG(reg, val) do { \ - tempIndex[outcount]=ADRINDEX(reg); \ - dma_ptr[1+outcount] = val; \ - if (MGA_VERBOSE) \ - DRM_DEBUG(" PRIMOUT %d: 0x%x -- 0x%x\n", \ - num_dwords + 1 + outcount, ADRINDEX(reg), val); \ - if( ++outcount == 4) { \ - outcount = 0; \ - dma_ptr[0] = *(u_int32_t *)tempIndex; \ - dma_ptr+=5; \ - num_dwords += 5; \ +#define DMA_LOCALS unsigned int write; volatile u8 *prim; + +#define DMA_BLOCK_SIZE (5 * sizeof(u32)) + +#define BEGIN_DMA( n ) \ +do { \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ + (n), __FUNCTION__ ); \ + DRM_INFO( " space=0x%x req=0x%x\n", \ + dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ } \ -}while (0) + prim = dev_priv->prim.start; \ + write = dev_priv->prim.tail; \ +} while (0) + +#define BEGIN_DMA_WRAP() \ +do { \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ + DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ + } \ + prim = dev_priv->prim.start; \ + write = dev_priv->prim.tail; \ +} while (0) + +#define ADVANCE_DMA() \ +do { \ + dev_priv->prim.tail = write; \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ + write, dev_priv->prim.space ); \ + } \ +} while (0) + +#define FLUSH_DMA() \ +do { \ + if ( 0 ) { \ + DRM_INFO( __FUNCTION__ ":\n" ); \ + DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ + dev_priv->prim.tail, \ + MGA_READ( MGA_PRIMADDRESS ) - \ + dev_priv->primary->offset ); \ + } \ + if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ + if ( dev_priv->prim.space < \ + dev_priv->prim.high_mark ) { \ + mga_do_dma_wrap_start( dev_priv ); \ + } else { \ + mga_do_dma_flush( dev_priv ); \ + } \ + } \ +} while (0) + +/* Never use this, always use DMA_BLOCK(...) for primary DMA output. + */ +#define DMA_WRITE( offset, val ) \ +do { \ + if ( MGA_VERBOSE ) { \ + DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \ + (u32)(val), write + (offset) * sizeof(u32) ); \ + } \ + *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ +} while (0) + +#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ +do { \ + DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ + (DMAREG( reg1 ) << 8) | \ + (DMAREG( reg2 ) << 16) | \ + (DMAREG( reg3 ) << 24)) ); \ + DMA_WRITE( 1, val0 ); \ + DMA_WRITE( 2, val1 ); \ + DMA_WRITE( 3, val2 ); \ + DMA_WRITE( 4, val3 ); \ + write += DMA_BLOCK_SIZE; \ +} while (0) + + +/* Buffer aging via primary DMA stream head pointer. + */ + +#define SET_AGE( age, h, w ) \ +do { \ + (age)->head = h; \ + (age)->wrap = w; \ +} while (0) + +#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ + ( (age)->wrap == w && \ + (age)->head < h ) ) + +#define AGE_BUFFER( buf_priv ) \ +do { \ + drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ + if ( (buf_priv)->dispatched ) { \ + entry->age.head = (dev_priv->prim.tail + \ + dev_priv->primary->offset); \ + entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ + } else { \ + entry->age.head = 0; \ + entry->age.wrap = 0; \ + } \ +} while (0) + + +#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ + MGA_DWGENGSTS | \ + MGA_ENDPRDMASTS) +#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ + MGA_ENDPRDMASTS) + +#define MGA_DMA_DEBUG 0 + + /* A reduced set of the mga registers. */ +#define MGA_CRTC_INDEX 0x1fd4 + +#define MGA_ALPHACTRL 0x2c7c +#define MGA_AR0 0x1c60 +#define MGA_AR1 0x1c64 +#define MGA_AR2 0x1c68 +#define MGA_AR3 0x1c6c +#define MGA_AR4 0x1c70 +#define MGA_AR5 0x1c74 +#define MGA_AR6 0x1c78 + +#define MGA_CXBNDRY 0x1c80 +#define MGA_CXLEFT 0x1ca0 +#define MGA_CXRIGHT 0x1ca4 + +#define MGA_DMAPAD 0x1c54 +#define MGA_DSTORG 0x2cb8 +#define MGA_DWGCTL 0x1c00 +# define MGA_OPCOD_MASK (15 << 0) +# define MGA_OPCOD_TRAP (4 << 0) +# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) +# define MGA_OPCOD_BITBLT (8 << 0) +# define MGA_OPCOD_ILOAD (9 << 0) +# define MGA_ATYPE_MASK (7 << 4) +# define MGA_ATYPE_RPL (0 << 4) +# define MGA_ATYPE_RSTR (1 << 4) +# define MGA_ATYPE_ZI (3 << 4) +# define MGA_ATYPE_BLK (4 << 4) +# define MGA_ATYPE_I (7 << 4) +# define MGA_LINEAR (1 << 7) +# define MGA_ZMODE_MASK (7 << 8) +# define MGA_ZMODE_NOZCMP (0 << 8) +# define MGA_ZMODE_ZE (2 << 8) +# define MGA_ZMODE_ZNE (3 << 8) +# define MGA_ZMODE_ZLT (4 << 8) +# define MGA_ZMODE_ZLTE (5 << 8) +# define MGA_ZMODE_ZGT (6 << 8) +# define MGA_ZMODE_ZGTE (7 << 8) +# define MGA_SOLID (1 << 11) +# define MGA_ARZERO (1 << 12) +# define MGA_SGNZERO (1 << 13) +# define MGA_SHIFTZERO (1 << 14) +# define MGA_BOP_MASK (15 << 16) +# define MGA_BOP_ZERO (0 << 16) +# define MGA_BOP_DST (10 << 16) +# define MGA_BOP_SRC (12 << 16) +# define MGA_BOP_ONE (15 << 16) +# define MGA_TRANS_SHIFT 20 +# define MGA_TRANS_MASK (15 << 20) +# define MGA_BLTMOD_MASK (15 << 25) +# define MGA_BLTMOD_BMONOLEF (0 << 25) +# define MGA_BLTMOD_BMONOWF (4 << 25) +# define MGA_BLTMOD_PLAN (1 << 25) +# define MGA_BLTMOD_BFCOL (2 << 25) +# define MGA_BLTMOD_BU32BGR (3 << 25) +# define MGA_BLTMOD_BU32RGB (7 << 25) +# define MGA_BLTMOD_BU24BGR (11 << 25) +# define MGA_BLTMOD_BU24RGB (15 << 25) +# define MGA_PATTERN (1 << 29) +# define MGA_TRANSC (1 << 30) +# define MGA_CLIPDIS (1 << 31) +#define MGA_DWGSYNC 0x2c4c + +#define MGA_FCOL 0x1c24 +#define MGA_FIFOSTATUS 0x1e10 +#define MGA_FOGCOL 0x1cf4 +#define MGA_FXBNDRY 0x1c84 +#define MGA_FXLEFT 0x1ca8 +#define MGA_FXRIGHT 0x1cac + +#define MGA_ICLEAR 0x1e18 +# define MGA_SOFTRAPICLR (1 << 0) +#define MGA_IEN 0x1e1c +# define MGA_SOFTRAPIEN (1 << 0) + +#define MGA_LEN 0x1c5c + +#define MGA_MACCESS 0x1c04 + +#define MGA_PITCH 0x1c8c +#define MGA_PLNWT 0x1c1c +#define MGA_PRIMADDRESS 0x1e58 +# define MGA_DMA_GENERAL (0 << 0) +# define MGA_DMA_BLIT (1 << 0) +# define MGA_DMA_VECTOR (2 << 0) +# define MGA_DMA_VERTEX (3 << 0) +#define MGA_PRIMEND 0x1e5c +# define MGA_PRIMNOSTART (1 << 0) +# define MGA_PAGPXFER (1 << 1) +#define MGA_PRIMPTR 0x1e50 +# define MGA_PRIMPTREN0 (1 << 0) +# define MGA_PRIMPTREN1 (1 << 1) + +#define MGA_RST 0x1e40 +# define MGA_SOFTRESET (1 << 0) +# define MGA_SOFTEXTRST (1 << 1) + +#define MGA_SECADDRESS 0x2c40 +#define MGA_SECEND 0x2c44 +#define MGA_SETUPADDRESS 0x2cd0 +#define MGA_SETUPEND 0x2cd4 +#define MGA_SGN 0x1c58 +#define MGA_SOFTRAP 0x2c48 +#define MGA_SRCORG 0x2cb4 +# define MGA_SRMMAP_MASK (1 << 0) +# define MGA_SRCMAP_FB (0 << 0) +# define MGA_SRCMAP_SYSMEM (1 << 0) +# define MGA_SRCACC_MASK (1 << 1) +# define MGA_SRCACC_PCI (0 << 1) +# define MGA_SRCACC_AGP (1 << 1) +#define MGA_STATUS 0x1e14 +# define MGA_SOFTRAPEN (1 << 0) +# define MGA_DWGENGSTS (1 << 16) +# define MGA_ENDPRDMASTS (1 << 17) +#define MGA_STENCIL 0x2cc8 +#define MGA_STENCILCTL 0x2ccc + +#define MGA_TDUALSTAGE0 0x2cf8 +#define MGA_TDUALSTAGE1 0x2cfc +#define MGA_TEXBORDERCOL 0x2c5c +#define MGA_TEXCTL 0x2c30 +#define MGA_TEXCTL2 0x2c3c +# define MGA_DUALTEX (1 << 7) +# define MGA_G400_TC2_MAGIC (1 << 15) +# define MGA_MAP1_ENABLE (1 << 31) +#define MGA_TEXFILTER 0x2c58 +#define MGA_TEXHEIGHT 0x2c2c +#define MGA_TEXORG 0x2c24 +# define MGA_TEXORGMAP_MASK (1 << 0) +# define MGA_TEXORGMAP_FB (0 << 0) +# define MGA_TEXORGMAP_SYSMEM (1 << 0) +# define MGA_TEXORGACC_MASK (1 << 1) +# define MGA_TEXORGACC_PCI (0 << 1) +# define MGA_TEXORGACC_AGP (1 << 1) +#define MGA_TEXORG1 0x2ca4 +#define MGA_TEXORG2 0x2ca8 +#define MGA_TEXORG3 0x2cac +#define MGA_TEXORG4 0x2cb0 +#define MGA_TEXTRANS 0x2c34 +#define MGA_TEXTRANSHIGH 0x2c38 +#define MGA_TEXWIDTH 0x2c28 + +#define MGA_WACCEPTSEQ 0x1dd4 +#define MGA_WCODEADDR 0x1e6c +#define MGA_WFLAG 0x1dc4 +#define MGA_WFLAG1 0x1de0 +#define MGA_WFLAGNB 0x1e64 +#define MGA_WFLAGNB1 0x1e08 +#define MGA_WGETMSB 0x1dc8 +#define MGA_WIADDR 0x1dc0 +#define MGA_WIADDR2 0x1dd8 +# define MGA_WMODE_SUSPEND (0 << 0) +# define MGA_WMODE_RESUME (1 << 0) +# define MGA_WMODE_JUMP (2 << 0) +# define MGA_WMODE_START (3 << 0) +# define MGA_WAGP_ENABLE (1 << 2) +#define MGA_WMISC 0x1e70 +# define MGA_WUCODECACHE_ENABLE (1 << 0) +# define MGA_WMASTER_ENABLE (1 << 1) +# define MGA_WCACHEFLUSH_ENABLE (1 << 3) +#define MGA_WVRTXSZ 0x1dcc + +#define MGA_YBOT 0x1c9c +#define MGA_YDST 0x1c90 +#define MGA_YDSTLEN 0x1c88 +#define MGA_YDSTORG 0x1c94 +#define MGA_YTOP 0x1c98 + +#define MGA_ZORG 0x1c0c + +/* This finishes the current batch of commands + */ +#define MGA_EXEC 0x0100 -#define MGAREG_MGA_EXEC 0x0100 -#define MGAREG_ALPHACTRL 0x2c7c -#define MGAREG_AR0 0x1c60 -#define MGAREG_AR1 0x1c64 -#define MGAREG_AR2 0x1c68 -#define MGAREG_AR3 0x1c6c -#define MGAREG_AR4 0x1c70 -#define MGAREG_AR5 0x1c74 -#define MGAREG_AR6 0x1c78 -#define MGAREG_CXBNDRY 0x1c80 -#define MGAREG_CXLEFT 0x1ca0 -#define MGAREG_CXRIGHT 0x1ca4 -#define MGAREG_DMAPAD 0x1c54 -#define MGAREG_DSTORG 0x2cb8 -#define MGAREG_DWGCTL 0x1c00 -#define MGAREG_DWGSYNC 0x2c4c -#define MGAREG_FCOL 0x1c24 -#define MGAREG_FIFOSTATUS 0x1e10 -#define MGAREG_FOGCOL 0x1cf4 -#define MGAREG_FXBNDRY 0x1c84 -#define MGAREG_FXLEFT 0x1ca8 -#define MGAREG_FXRIGHT 0x1cac -#define MGAREG_ICLEAR 0x1e18 -#define MGAREG_IEN 0x1e1c -#define MGAREG_LEN 0x1c5c -#define MGAREG_MACCESS 0x1c04 -#define MGAREG_PITCH 0x1c8c -#define MGAREG_PLNWT 0x1c1c -#define MGAREG_PRIMADDRESS 0x1e58 -#define MGAREG_PRIMEND 0x1e5c -#define MGAREG_PRIMPTR 0x1e50 -#define MGAREG_SECADDRESS 0x2c40 -#define MGAREG_SECEND 0x2c44 -#define MGAREG_SETUPADDRESS 0x2cd0 -#define MGAREG_SETUPEND 0x2cd4 -#define MGAREG_SOFTRAP 0x2c48 -#define MGAREG_SRCORG 0x2cb4 -#define MGAREG_STATUS 0x1e14 -#define MGAREG_STENCIL 0x2cc8 -#define MGAREG_STENCILCTL 0x2ccc -#define MGAREG_TDUALSTAGE0 0x2cf8 -#define MGAREG_TDUALSTAGE1 0x2cfc -#define MGAREG_TEXBORDERCOL 0x2c5c -#define MGAREG_TEXCTL 0x2c30 -#define MGAREG_TEXCTL2 0x2c3c -#define MGAREG_TEXFILTER 0x2c58 -#define MGAREG_TEXHEIGHT 0x2c2c -#define MGAREG_TEXORG 0x2c24 -#define MGAREG_TEXORG1 0x2ca4 -#define MGAREG_TEXORG2 0x2ca8 -#define MGAREG_TEXORG3 0x2cac -#define MGAREG_TEXORG4 0x2cb0 -#define MGAREG_TEXTRANS 0x2c34 -#define MGAREG_TEXTRANSHIGH 0x2c38 -#define MGAREG_TEXWIDTH 0x2c28 -#define MGAREG_WACCEPTSEQ 0x1dd4 -#define MGAREG_WCODEADDR 0x1e6c -#define MGAREG_WFLAG 0x1dc4 -#define MGAREG_WFLAG1 0x1de0 -#define MGAREG_WFLAGNB 0x1e64 -#define MGAREG_WFLAGNB1 0x1e08 -#define MGAREG_WGETMSB 0x1dc8 -#define MGAREG_WIADDR 0x1dc0 -#define MGAREG_WIADDR2 0x1dd8 -#define MGAREG_WMISC 0x1e70 -#define MGAREG_WVRTXSZ 0x1dcc -#define MGAREG_YBOT 0x1c9c -#define MGAREG_YDST 0x1c90 -#define MGAREG_YDSTLEN 0x1c88 -#define MGAREG_YDSTORG 0x1c94 -#define MGAREG_YTOP 0x1c98 -#define MGAREG_ZORG 0x1c0c - -/* Warp registers */ -#define MGAREG_WR0 0x2d00 -#define MGAREG_WR1 0x2d04 -#define MGAREG_WR2 0x2d08 -#define MGAREG_WR3 0x2d0c -#define MGAREG_WR4 0x2d10 -#define MGAREG_WR5 0x2d14 -#define MGAREG_WR6 0x2d18 -#define MGAREG_WR7 0x2d1c -#define MGAREG_WR8 0x2d20 -#define MGAREG_WR9 0x2d24 -#define MGAREG_WR10 0x2d28 -#define MGAREG_WR11 0x2d2c -#define MGAREG_WR12 0x2d30 -#define MGAREG_WR13 0x2d34 -#define MGAREG_WR14 0x2d38 -#define MGAREG_WR15 0x2d3c -#define MGAREG_WR16 0x2d40 -#define MGAREG_WR17 0x2d44 -#define MGAREG_WR18 0x2d48 -#define MGAREG_WR19 0x2d4c -#define MGAREG_WR20 0x2d50 -#define MGAREG_WR21 0x2d54 -#define MGAREG_WR22 0x2d58 -#define MGAREG_WR23 0x2d5c -#define MGAREG_WR24 0x2d60 -#define MGAREG_WR25 0x2d64 -#define MGAREG_WR26 0x2d68 -#define MGAREG_WR27 0x2d6c -#define MGAREG_WR28 0x2d70 -#define MGAREG_WR29 0x2d74 -#define MGAREG_WR30 0x2d78 -#define MGAREG_WR31 0x2d7c -#define MGAREG_WR32 0x2d80 -#define MGAREG_WR33 0x2d84 -#define MGAREG_WR34 0x2d88 -#define MGAREG_WR35 0x2d8c -#define MGAREG_WR36 0x2d90 -#define MGAREG_WR37 0x2d94 -#define MGAREG_WR38 0x2d98 -#define MGAREG_WR39 0x2d9c -#define MGAREG_WR40 0x2da0 -#define MGAREG_WR41 0x2da4 -#define MGAREG_WR42 0x2da8 -#define MGAREG_WR43 0x2dac -#define MGAREG_WR44 0x2db0 -#define MGAREG_WR45 0x2db4 -#define MGAREG_WR46 0x2db8 -#define MGAREG_WR47 0x2dbc -#define MGAREG_WR48 0x2dc0 -#define MGAREG_WR49 0x2dc4 -#define MGAREG_WR50 0x2dc8 -#define MGAREG_WR51 0x2dcc -#define MGAREG_WR52 0x2dd0 -#define MGAREG_WR53 0x2dd4 -#define MGAREG_WR54 0x2dd8 -#define MGAREG_WR55 0x2ddc -#define MGAREG_WR56 0x2de0 -#define MGAREG_WR57 0x2de4 -#define MGAREG_WR58 0x2de8 -#define MGAREG_WR59 0x2dec -#define MGAREG_WR60 0x2df0 -#define MGAREG_WR61 0x2df4 -#define MGAREG_WR62 0x2df8 -#define MGAREG_WR63 0x2dfc - - -#define PDEA_pagpxfer_enable 0x2 - -#define WIA_wmode_suspend 0x0 -#define WIA_wmode_start 0x3 -#define WIA_wagp_agp 0x4 - -#define DC_opcod_line_open 0x0 -#define DC_opcod_autoline_open 0x1 -#define DC_opcod_line_close 0x2 -#define DC_opcod_autoline_close 0x3 -#define DC_opcod_trap 0x4 -#define DC_opcod_texture_trap 0x6 -#define DC_opcod_bitblt 0x8 -#define DC_opcod_iload 0x9 -#define DC_atype_rpl 0x0 -#define DC_atype_rstr 0x10 -#define DC_atype_zi 0x30 -#define DC_atype_blk 0x40 -#define DC_atype_i 0x70 -#define DC_linear_xy 0x0 -#define DC_linear_linear 0x80 -#define DC_zmode_nozcmp 0x0 -#define DC_zmode_ze 0x200 -#define DC_zmode_zne 0x300 -#define DC_zmode_zlt 0x400 -#define DC_zmode_zlte 0x500 -#define DC_zmode_zgt 0x600 -#define DC_zmode_zgte 0x700 -#define DC_solid_disable 0x0 -#define DC_solid_enable 0x800 -#define DC_arzero_disable 0x0 -#define DC_arzero_enable 0x1000 -#define DC_sgnzero_disable 0x0 -#define DC_sgnzero_enable 0x2000 -#define DC_shftzero_disable 0x0 -#define DC_shftzero_enable 0x4000 -#define DC_bop_SHIFT 16 -#define DC_trans_SHIFT 20 -#define DC_bltmod_bmonolef 0x0 -#define DC_bltmod_bmonowf 0x8000000 -#define DC_bltmod_bplan 0x2000000 -#define DC_bltmod_bfcol 0x4000000 -#define DC_bltmod_bu32bgr 0x6000000 -#define DC_bltmod_bu32rgb 0xe000000 -#define DC_bltmod_bu24bgr 0x16000000 -#define DC_bltmod_bu24rgb 0x1e000000 -#define DC_pattern_disable 0x0 -#define DC_pattern_enable 0x20000000 -#define DC_transc_disable 0x0 -#define DC_transc_enable 0x40000000 -#define DC_clipdis_disable 0x0 -#define DC_clipdis_enable 0x80000000 - -#define SETADD_mode_vertlist 0x0 - - -#define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \ - DC_sgnzero_enable | DC_shftzero_enable | \ - (0xC << DC_bop_SHIFT) | DC_clipdis_enable | \ - DC_solid_enable | DC_transc_enable) - - -#define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \ - DC_solid_disable | DC_arzero_disable | \ - DC_sgnzero_enable | DC_shftzero_enable | \ - (0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \ - DC_pattern_disable | DC_transc_disable | \ - DC_clipdis_enable) \ - -#define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\ - DC_arzero_enable | DC_sgnzero_enable | \ - DC_atype_i) +/* Warp registers + */ +#define MGA_WR0 0x2d00 +#define MGA_WR1 0x2d04 +#define MGA_WR2 0x2d08 +#define MGA_WR3 0x2d0c +#define MGA_WR4 0x2d10 +#define MGA_WR5 0x2d14 +#define MGA_WR6 0x2d18 +#define MGA_WR7 0x2d1c +#define MGA_WR8 0x2d20 +#define MGA_WR9 0x2d24 +#define MGA_WR10 0x2d28 +#define MGA_WR11 0x2d2c +#define MGA_WR12 0x2d30 +#define MGA_WR13 0x2d34 +#define MGA_WR14 0x2d38 +#define MGA_WR15 0x2d3c +#define MGA_WR16 0x2d40 +#define MGA_WR17 0x2d44 +#define MGA_WR18 0x2d48 +#define MGA_WR19 0x2d4c +#define MGA_WR20 0x2d50 +#define MGA_WR21 0x2d54 +#define MGA_WR22 0x2d58 +#define MGA_WR23 0x2d5c +#define MGA_WR24 0x2d60 +#define MGA_WR25 0x2d64 +#define MGA_WR26 0x2d68 +#define MGA_WR27 0x2d6c +#define MGA_WR28 0x2d70 +#define MGA_WR29 0x2d74 +#define MGA_WR30 0x2d78 +#define MGA_WR31 0x2d7c +#define MGA_WR32 0x2d80 +#define MGA_WR33 0x2d84 +#define MGA_WR34 0x2d88 +#define MGA_WR35 0x2d8c +#define MGA_WR36 0x2d90 +#define MGA_WR37 0x2d94 +#define MGA_WR38 0x2d98 +#define MGA_WR39 0x2d9c +#define MGA_WR40 0x2da0 +#define MGA_WR41 0x2da4 +#define MGA_WR42 0x2da8 +#define MGA_WR43 0x2dac +#define MGA_WR44 0x2db0 +#define MGA_WR45 0x2db4 +#define MGA_WR46 0x2db8 +#define MGA_WR47 0x2dbc +#define MGA_WR48 0x2dc0 +#define MGA_WR49 0x2dc4 +#define MGA_WR50 0x2dc8 +#define MGA_WR51 0x2dcc +#define MGA_WR52 0x2dd0 +#define MGA_WR53 0x2dd4 +#define MGA_WR54 0x2dd8 +#define MGA_WR55 0x2ddc +#define MGA_WR56 0x2de0 +#define MGA_WR57 0x2de4 +#define MGA_WR58 0x2de8 +#define MGA_WR59 0x2dec +#define MGA_WR60 0x2df0 +#define MGA_WR61 0x2df4 +#define MGA_WR62 0x2df8 +#define MGA_WR63 0x2dfc +# define MGA_G400_WR_MAGIC (1 << 6) +# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ + + +#define MGA_ILOAD_ALIGN 64 +#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) + +#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ + MGA_ATYPE_I | \ + MGA_ZMODE_NOZCMP | \ + MGA_ARZERO | \ + MGA_SGNZERO | \ + MGA_BOP_SRC | \ + (15 << MGA_TRANS_SHIFT)) + +#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ + MGA_ZMODE_NOZCMP | \ + MGA_SOLID | \ + MGA_ARZERO | \ + MGA_SGNZERO | \ + MGA_SHIFTZERO | \ + MGA_BOP_SRC | \ + (0 << MGA_TRANS_SHIFT) | \ + MGA_BLTMOD_BMONOLEF | \ + MGA_TRANSC | \ + MGA_CLIPDIS) + +#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ + MGA_ATYPE_RPL | \ + MGA_SGNZERO | \ + MGA_SHIFTZERO | \ + MGA_BOP_SRC | \ + (0 << MGA_TRANS_SHIFT) | \ + MGA_BLTMOD_BFCOL | \ + MGA_CLIPDIS) + +/* Simple idle test. + */ +static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) +{ + u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; + return ( status == MGA_ENDPRDMASTS ); +} #endif diff --git a/bsd/mga/mga_state.c b/bsd/mga/mga_state.c index fb365631..320e2b3e 100644 --- a/bsd/mga/mga_state.c +++ b/bsd/mga/mga_state.c @@ -1,4 +1,4 @@ -/* mga_state.c -- State support for mga g200/g400 +/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*- * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -11,431 +11,408 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. * - * Authors: Jeff Hartmann <jhartmann@precisioninsight.com> - * Keith Whitwell <keithw@precisioninsight.com> + * Authors: + * Jeff Hartmann <jhartmann@valinux.com> + * Keith Whitwell <keithw@valinux.com> * + * Rewritten by: + * Gareth Hughes <gareth@valinux.com> */ #define __NO_VERSION__ +#include "mga.h" #include "drmP.h" #include "mga_drv.h" #include "drm.h" -typedef u_int16_t u16; -typedef u_int32_t u32; - -#define MGAEMITCLIP_SIZE 10 -#define MGAEMITCTX_SIZE 20 -#define MGAG200EMITTEX_SIZE 20 -#define MGAG400EMITTEX0_SIZE 30 -#define MGAG400EMITTEX1_SIZE 25 -#define MGAG400EMITPIPE_SIZE 50 -#define MGAG200EMITPIPE_SIZE 15 - -#define MAX_STATE_SIZE ((MGAEMITCLIP_SIZE * MGA_NR_SAREA_CLIPRECTS) + \ - MGAEMITCTX_SIZE + MGAG400EMITTEX0_SIZE + \ - MGAG400EMITTEX1_SIZE + MGAG400EMITPIPE_SIZE) - +/* ================================================================ + * DMA hardware state programming functions + */ -static void mgaEmitClipRect(drm_mga_private_t * dev_priv, - drm_clip_rect_t * box) +static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, + drm_clip_rect_t *box ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->ContextState; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + unsigned int pitch = dev_priv->front_pitch; + DMA_LOCALS; - /* This takes 10 dwords */ - PRIMGETPTR(dev_priv); + BEGIN_DMA( 2 ); - /* Force reset of dwgctl (eliminates clip disable) */ - if (dev_priv->chipset == MGA_CARD_TYPE_G400) { -#if 0 - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0); - PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); -#else - PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); - PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000); - PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); - PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000); -#endif + /* Force reset of DWGCTL on G400 (eliminates clip disable bit). + */ + if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { + DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl, + MGA_LEN + MGA_EXEC, 0x80000000, + MGA_DWGCTL, ctx->dwgctl, + MGA_LEN + MGA_EXEC, 0x80000000 ); } - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_CXBNDRY, ((box->x2) << 16) | (box->x1)); - PRIMOUTREG(MGAREG_YTOP, box->y1 * dev_priv->stride / dev_priv->cpp); - PRIMOUTREG(MGAREG_YBOT, box->y2 * dev_priv->stride / dev_priv->cpp); + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_CXBNDRY, (box->x2 << 16) | box->x1, + MGA_YTOP, box->y1 * pitch, + MGA_YBOT, box->y2 * pitch ); - PRIMADVANCE(dev_priv); + ADVANCE_DMA(); } -static void mgaEmitContext(drm_mga_private_t * dev_priv) +static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->ContextState; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - /* This takes a max of 20 dwords */ - PRIMGETPTR(dev_priv); - - PRIMOUTREG(MGAREG_DSTORG, regs[MGA_CTXREG_DSTORG]); - PRIMOUTREG(MGAREG_MACCESS, regs[MGA_CTXREG_MACCESS]); - PRIMOUTREG(MGAREG_PLNWT, regs[MGA_CTXREG_PLNWT]); - PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); - - PRIMOUTREG(MGAREG_ALPHACTRL, regs[MGA_CTXREG_ALPHACTRL]); - PRIMOUTREG(MGAREG_FOGCOL, regs[MGA_CTXREG_FOGCOLOR]); - PRIMOUTREG(MGAREG_WFLAG, regs[MGA_CTXREG_WFLAG]); - PRIMOUTREG(MGAREG_ZORG, dev_priv->depthOffset); /* invarient */ - - if (dev_priv->chipset == MGA_CARD_TYPE_G400) { - PRIMOUTREG(MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG]); - PRIMOUTREG(MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0]); - PRIMOUTREG(MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1]); - PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]); - - PRIMOUTREG(MGAREG_STENCIL, regs[MGA_CTXREG_STENCIL]); - PRIMOUTREG(MGAREG_STENCILCTL, regs[MGA_CTXREG_STENCILCTL]); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + DMA_LOCALS; - } else { - PRIMOUTREG(MGAREG_FCOL, regs[MGA_CTXREG_FCOL]); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - } + BEGIN_DMA( 3 ); + + DMA_BLOCK( MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, + MGA_DWGCTL, ctx->dwgctl ); - PRIMADVANCE(dev_priv); + DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, + MGA_ZORG, dev_priv->depth_offset ); + + DMA_BLOCK( MGA_FCOL, ctx->fcol, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + ADVANCE_DMA(); } -static void mgaG200EmitTex(drm_mga_private_t * dev_priv) +static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->TexState[0]; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - PRIMGETPTR(dev_priv); + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + DMA_LOCALS; - /* This takes 20 dwords */ + BEGIN_DMA( 4 ); - PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2]); - PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); - PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); - PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); + DMA_BLOCK( MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, + MGA_DWGCTL, ctx->dwgctl ); - PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]); - PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]); - PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]); - PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]); + DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, + MGA_ZORG, dev_priv->depth_offset ); - PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]); - PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]); - PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]); - PRIMOUTREG(MGAREG_WR24, regs[MGA_TEXREG_WIDTH]); + DMA_BLOCK( MGA_WFLAG1, ctx->wflag, + MGA_TDUALSTAGE0, ctx->tdualstage0, + MGA_TDUALSTAGE1, ctx->tdualstage1, + MGA_FCOL, ctx->fcol ); - PRIMOUTREG(MGAREG_WR34, regs[MGA_TEXREG_HEIGHT]); - PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); - PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); - PRIMOUTREG(MGAREG_DMAPAD, 0); + DMA_BLOCK( MGA_STENCIL, ctx->stencil, + MGA_STENCILCTL, ctx->stencilctl, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); - PRIMADVANCE(dev_priv); + ADVANCE_DMA(); } -#define TMC_dualtex_enable 0x80 - -static void mgaG400EmitTex0(drm_mga_private_t * dev_priv) +static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->TexState[0]; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - PRIMGETPTR(dev_priv); - - /* This takes a max of 30 dwords */ - - PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000); - PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); - PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); - PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; + DMA_LOCALS; - PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]); - PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]); - PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]); - PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]); + BEGIN_DMA( 4 ); - PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]); - PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]); - PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]); - PRIMOUTREG(MGAREG_WR49, 0); + DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol ); - PRIMOUTREG(MGAREG_WR57, 0); - PRIMOUTREG(MGAREG_WR53, 0); - PRIMOUTREG(MGAREG_WR61, 0); - PRIMOUTREG(MGAREG_WR52, 0x40); + DMA_BLOCK( MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, + MGA_TEXORG3, tex->texorg3 ); - PRIMOUTREG(MGAREG_WR60, 0x40); - PRIMOUTREG(MGAREG_WR54, regs[MGA_TEXREG_WIDTH] | 0x40); - PRIMOUTREG(MGAREG_WR62, regs[MGA_TEXREG_HEIGHT] | 0x40); - PRIMOUTREG(MGAREG_DMAPAD, 0); + DMA_BLOCK( MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, + MGA_WR24, tex->texwidth ); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); + DMA_BLOCK( MGA_WR34, tex->texheight, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, + MGA_DMAPAD, 0x00000000 ); - PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); - PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); - - PRIMADVANCE(dev_priv); + ADVANCE_DMA(); } -#define TMC_map1_enable 0x80000000 - -static void mgaG400EmitTex1(drm_mga_private_t * dev_priv) +static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->TexState[1]; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - PRIMGETPTR(dev_priv); - - /* This takes 25 dwords */ - - PRIMOUTREG(MGAREG_TEXCTL2, - regs[MGA_TEXREG_CTL2] | TMC_map1_enable | 0x00008000); - PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL]); - PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER]); - PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL]); + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; + DMA_LOCALS; + + BEGIN_DMA( 6 ); + + DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol ); + + DMA_BLOCK( MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, + MGA_TEXORG3, tex->texorg3 ); + + DMA_BLOCK( MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, + MGA_WR49, 0x00000000 ); + + DMA_BLOCK( MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, + MGA_WR52, MGA_G400_WR_MAGIC ); + + DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, + MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, + MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff ); + + ADVANCE_DMA(); +} - PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG]); - PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1]); - PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2]); - PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3]); +static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; + DMA_LOCALS; + + BEGIN_DMA( 5 ); + + DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | + MGA_MAP1_ENABLE | + MGA_G400_TC2_MAGIC), + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol ); + + DMA_BLOCK( MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, + MGA_TEXORG3, tex->texorg3 ); + + DMA_BLOCK( MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, + MGA_WR49, 0x00000000 ); + + DMA_BLOCK( MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, + MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); + + DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, + MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); + + ADVANCE_DMA(); +} - PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4]); - PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH]); - PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT]); - PRIMOUTREG(MGAREG_WR49, 0); +static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) +{ + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int pipe = sarea_priv->warp_pipe; + DMA_LOCALS; - PRIMOUTREG(MGAREG_WR57, 0); - PRIMOUTREG(MGAREG_WR53, 0); - PRIMOUTREG(MGAREG_WR61, 0); - PRIMOUTREG(MGAREG_WR52, regs[MGA_TEXREG_WIDTH] | 0x40); + BEGIN_DMA( 3 ); - PRIMOUTREG(MGAREG_WR60, regs[MGA_TEXREG_HEIGHT] | 0x40); + DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, + MGA_WVRTXSZ, 0x00000007, + MGA_WFLAG, 0x00000000, + MGA_WR24, 0x00000000 ); - PRIMOUTREG(MGAREG_TEXTRANS, 0xffff); - PRIMOUTREG(MGAREG_TEXTRANSHIGH, 0xffff); - PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | 0x00008000); + DMA_BLOCK( MGA_WR25, 0x00000100, + MGA_WR34, 0x00000000, + MGA_WR42, 0x0000ffff, + MGA_WR60, 0x0000ffff ); - PRIMADVANCE(dev_priv); + /* Padding required to to hardware bug. + */ + DMA_BLOCK( MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | + MGA_WMODE_START | + MGA_WAGP_ENABLE) ); + + ADVANCE_DMA(); } -#define MAGIC_FPARAM_HEX_VALUE 0x46480000 -/* This is the hex value of 12800.0f which is a magic value we must - * set in wr56. - */ - - -#define EMIT_PIPE 50 -static void mgaG400EmitPipe(drm_mga_private_t * dev_priv) +static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int pipe = sarea_priv->WarpPipe; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - PRIMGETPTR(dev_priv); - - /* This takes 50 dwords */ - - /* Establish vertex size. - */ - PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - - if (pipe & MGA_T2) { - PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000); + unsigned int pipe = sarea_priv->warp_pipe; + DMA_LOCALS; + + BEGIN_DMA( 10 ); + + DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + if ( pipe & MGA_T2 ) { + DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x1e000000 ); } else { - if (dev_priv->WarpPipe & MGA_T2) { + if ( dev_priv->warp_pipe & MGA_T2 ) { /* Flush the WARP pipe */ - PRIMOUTREG(MGAREG_YDST, 0); - PRIMOUTREG(MGAREG_FXLEFT, 0); - PRIMOUTREG(MGAREG_FXRIGHT, 1); - PRIMOUTREG(MGAREG_DWGCTL, MGA_FLUSH_CMD); - - PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 1); - PRIMOUTREG(MGAREG_DWGSYNC, 0x7000); - PRIMOUTREG(MGAREG_TEXCTL2, 0x00008000); - PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0); - - PRIMOUTREG(MGAREG_TEXCTL2, 0x80 | 0x00008000); - PRIMOUTREG(MGAREG_LEN + MGAREG_MGA_EXEC, 0); - PRIMOUTREG(MGAREG_TEXCTL2, 0x00008000); - PRIMOUTREG(MGAREG_DMAPAD, 0); + DMA_BLOCK( MGA_YDST, 0x00000000, + MGA_FXLEFT, 0x00000000, + MGA_FXRIGHT, 0x00000001, + MGA_DWGCTL, MGA_DWGCTL_FLUSH ); + + DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, + MGA_DWGSYNC, 0x00007000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_LEN + MGA_EXEC, 0x00000000 ); + + DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | + MGA_G400_TC2_MAGIC), + MGA_LEN + MGA_EXEC, 0x00000000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_DMAPAD, 0x00000000 ); } - PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); + DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000 ); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0); - PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x18000000); + DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x18000000 ); } - PRIMOUTREG(MGAREG_WFLAG, 0); - PRIMOUTREG(MGAREG_WFLAG1, 0); - PRIMOUTREG(MGAREG_WR56, MAGIC_FPARAM_HEX_VALUE); - PRIMOUTREG(MGAREG_DMAPAD, 0); - - PRIMOUTREG(MGAREG_WR49, 0); /* Tex stage 0 */ - PRIMOUTREG(MGAREG_WR57, 0); /* Tex stage 0 */ - PRIMOUTREG(MGAREG_WR53, 0); /* Tex stage 1 */ - PRIMOUTREG(MGAREG_WR61, 0); /* Tex stage 1 */ - - - PRIMOUTREG(MGAREG_WR54, 0x40); /* Tex stage 0 : w */ - PRIMOUTREG(MGAREG_WR62, 0x40); /* Tex stage 0 : h */ - PRIMOUTREG(MGAREG_WR52, 0x40); /* Tex stage 1 : w */ - PRIMOUTREG(MGAREG_WR60, 0x40); /* Tex stage 1 : h */ - - - /* Dma pading required due to hw bug */ - PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_WIADDR2, - (u32) (dev_priv->WarpIndex[pipe]. - phys_addr | WIA_wmode_start | WIA_wagp_agp)); - PRIMADVANCE(dev_priv); + DMA_BLOCK( MGA_WFLAG, 0x00000000, + MGA_WFLAG1, 0x00000000, + MGA_WR56, MGA_G400_WR56_MAGIC, + MGA_DMAPAD, 0x00000000 ); + + DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ + MGA_WR57, 0x00000000, /* tex0 */ + MGA_WR53, 0x00000000, /* tex1 */ + MGA_WR61, 0x00000000 ); /* tex1 */ + + DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ + MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ + MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ + MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ + + /* Padding required to to hardware bug */ + DMA_BLOCK( MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_DMAPAD, 0xffffffff, + MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | + MGA_WMODE_START | + MGA_WAGP_ENABLE) ); + + ADVANCE_DMA(); } -static void mgaG200EmitPipe(drm_mga_private_t * dev_priv) +static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int pipe = sarea_priv->WarpPipe; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - PRIMGETPTR(dev_priv); - - /* This takes 15 dwords */ - - PRIMOUTREG(MGAREG_WIADDR, WIA_wmode_suspend); - PRIMOUTREG(MGAREG_WVRTXSZ, 7); - PRIMOUTREG(MGAREG_WFLAG, 0); - PRIMOUTREG(MGAREG_WR24, 0); /* tex w/h */ + unsigned int dirty = sarea_priv->dirty; - PRIMOUTREG(MGAREG_WR25, 0x100); - PRIMOUTREG(MGAREG_WR34, 0); /* tex w/h */ - PRIMOUTREG(MGAREG_WR42, 0xFFFF); - PRIMOUTREG(MGAREG_WR60, 0xFFFF); + if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { + mga_g200_emit_pipe( dev_priv ); + dev_priv->warp_pipe = sarea_priv->warp_pipe; + } - /* Dma pading required due to hw bug */ - PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_WIADDR, - (u32) (dev_priv->WarpIndex[pipe]. - phys_addr | WIA_wmode_start | WIA_wagp_agp)); + if ( dirty & MGA_UPLOAD_CONTEXT ) { + mga_g200_emit_context( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; + } - PRIMADVANCE(dev_priv); + if ( dirty & MGA_UPLOAD_TEX0 ) { + mga_g200_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } } -static void mgaEmitState(drm_mga_private_t * dev_priv) +static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - DRM_DEBUG("%s\n", __FUNCTION__); - - if (dev_priv->chipset == MGA_CARD_TYPE_G400) { - int multitex = sarea_priv->WarpPipe & MGA_T2; - - if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { - mgaG400EmitPipe(dev_priv); - dev_priv->WarpPipe = sarea_priv->WarpPipe; - } - - if (dirty & MGA_UPLOAD_CTX) { - mgaEmitContext(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_CTX; - } + int multitex = sarea_priv->warp_pipe & MGA_T2; - if (dirty & MGA_UPLOAD_TEX0) { - mgaG400EmitTex0(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; - } + if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { + mga_g400_emit_pipe( dev_priv ); + dev_priv->warp_pipe = sarea_priv->warp_pipe; + } - if ((dirty & MGA_UPLOAD_TEX1) && multitex) { - mgaG400EmitTex1(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; - } - } else { - if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { - mgaG200EmitPipe(dev_priv); - dev_priv->WarpPipe = sarea_priv->WarpPipe; - } + if ( dirty & MGA_UPLOAD_CONTEXT ) { + mga_g400_emit_context( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; + } - if (dirty & MGA_UPLOAD_CTX) { - mgaEmitContext(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_CTX; - } + if ( dirty & MGA_UPLOAD_TEX0 ) { + mga_g400_emit_tex0( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } - if (dirty & MGA_UPLOAD_TEX0) { - mgaG200EmitTex(dev_priv); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; - } + if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { + mga_g400_emit_tex1( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; } } +/* ================================================================ + * SAREA state verification + */ + /* Disallow all write destinations except the front and backbuffer. */ -static int mgaVerifyContext(drm_mga_private_t * dev_priv) +static int mga_verify_context( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->ContextState; - - DRM_DEBUG("%s\n", __FUNCTION__); - - if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOffset && - regs[MGA_CTXREG_DSTORG] != dev_priv->backOffset) { - DRM_DEBUG("BAD DSTORG: %x (front %x, back %x)\n\n", - regs[MGA_CTXREG_DSTORG], dev_priv->frontOffset, - dev_priv->backOffset); - regs[MGA_CTXREG_DSTORG] = 0; - return -1; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + + if ( ctx->dstorg != dev_priv->front_offset && + ctx->dstorg != dev_priv->back_offset ) { + DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", + ctx->dstorg, dev_priv->front_offset, + dev_priv->back_offset ); + ctx->dstorg = 0; + DRM_OS_RETURN( EINVAL ); } return 0; @@ -443,667 +420,647 @@ static int mgaVerifyContext(drm_mga_private_t * dev_priv) /* Disallow texture reads from PCI space. */ -static int mgaVerifyTex(drm_mga_private_t * dev_priv, int unit) +static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; + unsigned int org; - DRM_DEBUG("%s\n", __FUNCTION__); + org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); - if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) { - DRM_DEBUG("BAD TEXREG_ORG: %x, unit %d\n", - sarea_priv->TexState[unit][MGA_TEXREG_ORG], - unit); - sarea_priv->TexState[unit][MGA_TEXREG_ORG] = 0; - return -1; + if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { + DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", + tex->texorg, unit ); + tex->texorg = 0; + DRM_OS_RETURN( EINVAL ); } return 0; } -static int mgaVerifyState(drm_mga_private_t * dev_priv) +static int mga_verify_state( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - int rv = 0; - - DRM_DEBUG("%s\n", __FUNCTION__); + int ret = 0; - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if (dirty & MGA_UPLOAD_CTX) - rv |= mgaVerifyContext(dev_priv); + if ( dirty & MGA_UPLOAD_CONTEXT ) + ret |= mga_verify_context( dev_priv ); - if (dirty & MGA_UPLOAD_TEX0) - rv |= mgaVerifyTex(dev_priv, 0); + if ( dirty & MGA_UPLOAD_TEX0 ) + ret |= mga_verify_tex( dev_priv, 0 ); - if (dev_priv->chipset == MGA_CARD_TYPE_G400) { - if (dirty & MGA_UPLOAD_TEX1) - rv |= mgaVerifyTex(dev_priv, 1); + if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { + if ( dirty & MGA_UPLOAD_TEX1 ) + ret |= mga_verify_tex( dev_priv, 1 ); - if (dirty & MGA_UPLOAD_PIPE) - rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES); + if ( dirty & MGA_UPLOAD_PIPE ) + ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); } else { - if (dirty & MGA_UPLOAD_PIPE) - rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES); + if ( dirty & MGA_UPLOAD_PIPE ) + ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); } - return rv == 0; + return ( ret == 0 ); } -static int mgaVerifyIload(drm_mga_private_t * dev_priv, - unsigned long bus_address, - unsigned int dstOrg, int length) +static int mga_verify_iload( drm_mga_private_t *dev_priv, + unsigned int dstorg, unsigned int length ) { - DRM_DEBUG("%s\n", __FUNCTION__); + if ( dstorg < dev_priv->texture_offset || + dstorg + length > (dev_priv->texture_offset + + dev_priv->texture_size) ) { + DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); + DRM_OS_RETURN( EINVAL ); + } - if (dstOrg < dev_priv->textureOffset || - dstOrg + length > - (dev_priv->textureOffset + dev_priv->textureSize)) { - return EINVAL; + if ( length & MGA_ILOAD_MASK ) { + DRM_ERROR( "*** bad iload length: 0x%x\n", + length & MGA_ILOAD_MASK ); + DRM_OS_RETURN( EINVAL ); } - if (length % 64) { - return EINVAL; + + return 0; +} + +static int mga_verify_blit( drm_mga_private_t *dev_priv, + unsigned int srcorg, unsigned int dstorg ) +{ + if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || + (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { + DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", + srcorg, dstorg ); + DRM_OS_RETURN( EINVAL ); } return 0; } -/* This copies a 64 byte aligned agp region to the frambuffer - * with a standard blit, the ioctl needs to do checking */ -static void mga_dma_dispatch_tex_blit(drm_device_t * dev, - unsigned long bus_address, - int length, unsigned int destOrg) +/* ================================================================ + * + */ + +static void mga_dma_dispatch_clear( drm_device_t *dev, + drm_mga_clear_t *clear ) { drm_mga_private_t *dev_priv = dev->dev_private; - int use_agp = PDEA_pagpxfer_enable | 0x00000001; - u16 y2; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + int i; + DMA_LOCALS; + DRM_DEBUG( __FUNCTION__ ":\n" ); - y2 = length / 64; + BEGIN_DMA( 1 ); - PRIM_OVERFLOW(dev, dev_priv, 30); + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); - PRIMOUTREG(MGAREG_DSTORG, destOrg); - PRIMOUTREG(MGAREG_MACCESS, 0x00000000); - DRM_DEBUG("srcorg : %lx\n", bus_address | use_agp); - PRIMOUTREG(MGAREG_SRCORG, (u32) bus_address | use_agp); - PRIMOUTREG(MGAREG_AR5, 64); + ADVANCE_DMA(); - PRIMOUTREG(MGAREG_PITCH, 64); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD); + for ( i = 0 ; i < nbox ; i++ ) { + drm_clip_rect_t *box = &pbox[i]; + u32 height = box->y2 - box->y1; - PRIMOUTREG(MGAREG_AR0, 63); - PRIMOUTREG(MGAREG_AR3, 0); - PRIMOUTREG(MGAREG_FXBNDRY, (63 << 16)); - PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC, y2); + DRM_DEBUG( " from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2 ); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_SRCORG, 0); - PRIMOUTREG(MGAREG_PITCH, dev_priv->stride / dev_priv->cpp); - PRIMOUTREG(MGAREG_DWGSYNC, 0x7000); + if ( clear->flags & MGA_FRONT ) { + BEGIN_DMA( 2 ); - PRIMADVANCE(dev_priv); -} + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); -static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned long address = (unsigned long) buf->bus_address; - int length = buf->used; - int use_agp = PDEA_pagpxfer_enable; - int i = 0; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->front_offset, + MGA_DWGCTL + MGA_EXEC, + dev_priv->clear_cmd ); - DRM_DEBUG("dispatch vertex %d addr 0x%lx, " - "length 0x%x nbox %d dirty %x\n", - buf->idx, address, length, - sarea_priv->nbox, sarea_priv->dirty); + ADVANCE_DMA(); + } - DRM_DEBUG("used : %d, total : %d\n", buf->used, buf->total); - if (buf->used) { - /* WARNING: if you change any of the state functions verify - * these numbers (Overestimating this doesn't hurt). - */ - buf_priv->dispatched = 1; - PRIM_OVERFLOW(dev, dev_priv, - (MAX_STATE_SIZE + (5 * MGA_NR_SAREA_CLIPRECTS))); - mgaEmitState(dev_priv); + if ( clear->flags & MGA_BACK ) { + BEGIN_DMA( 2 ); -#if 0 - length = dev_priv->vertexsize * 3 * 4; -#endif + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->back_offset, + MGA_DWGCTL + MGA_EXEC, + dev_priv->clear_cmd ); + ADVANCE_DMA(); + } - do { - if (i < sarea_priv->nbox) { - DRM_DEBUG("idx %d Emit box %d/%d:" - "%d,%d - %d,%d\n", - buf->idx, - i, sarea_priv->nbox, - sarea_priv->boxes[i].x1, - sarea_priv->boxes[i].y1, - sarea_priv->boxes[i].x2, - sarea_priv->boxes[i].y2); - - mgaEmitClipRect(dev_priv, - &sarea_priv->boxes[i]); - } + if ( clear->flags & MGA_DEPTH ) { + BEGIN_DMA( 2 ); - PRIMGETPTR(dev_priv); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_SECADDRESS, - ((u32) address) | TT_VERTEX); - PRIMOUTREG(MGAREG_SECEND, - (((u32) (address + length)) | use_agp)); - PRIMADVANCE(dev_priv); - } while (++i < sarea_priv->nbox); - } + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->depth_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_depth, + MGA_DSTORG, dev_priv->depth_offset, + MGA_DWGCTL + MGA_EXEC, + dev_priv->clear_cmd ); + + ADVANCE_DMA(); + } - if (buf_priv->discard) { - if (buf_priv->dispatched == 1) - AGEBUF(dev_priv, buf_priv); - buf_priv->dispatched = 0; - mga_freelist_put(dev, buf); } + BEGIN_DMA( 1 ); + + /* Force reset of DWGCTL */ + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_DWGCTL, ctx->dwgctl ); + + ADVANCE_DMA(); + FLUSH_DMA(); } +static void mga_dma_dispatch_swap( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + int i; + DMA_LOCALS; + DRM_DEBUG( __FUNCTION__ ":\n" ); + + sarea_priv->last_frame.head = dev_priv->prim.tail; + sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; + + BEGIN_DMA( 4 + nbox ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); + + DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, + MGA_MACCESS, dev_priv->maccess, + MGA_SRCORG, dev_priv->back_offset, + MGA_AR5, dev_priv->front_pitch ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, 0xffffffff, + MGA_DWGCTL, MGA_DWGCTL_COPY ); + + for ( i = 0 ; i < nbox ; i++ ) { + drm_clip_rect_t *box = &pbox[i]; + u32 height = box->y2 - box->y1; + u32 start = box->y1 * dev_priv->front_pitch; + + DRM_DEBUG( " from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2 ); + + DMA_BLOCK( MGA_AR0, start + box->x2 - 1, + MGA_AR3, start + box->x1, + MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, + MGA_YDSTLEN + MGA_EXEC, + (box->y1 << 16) | height ); + } -static void mga_dma_dispatch_indices(drm_device_t * dev, - drm_buf_t * buf, - unsigned int start, unsigned int end) + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, + MGA_DWGCTL, ctx->dwgctl ); + + ADVANCE_DMA(); + + FLUSH_DMA(); + + DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); +} + +static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int address = (unsigned int) buf->bus_address; - int use_agp = PDEA_pagpxfer_enable; + u32 address = (u32) buf->bus_address; + u32 length = (u32) buf->used; int i = 0; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - DRM_DEBUG("dispatch indices %d addr 0x%x, " - "start 0x%x end 0x%x nbox %d dirty %x\n", - buf->idx, address, start, end, - sarea_priv->nbox, sarea_priv->dirty); - - if (start != end) { - /* WARNING: if you change any of the state functions verify - * these numbers (Overestimating this doesn't hurt). - */ + DMA_LOCALS; + DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); + + if ( buf->used ) { buf_priv->dispatched = 1; - PRIM_OVERFLOW(dev, dev_priv, - (MAX_STATE_SIZE + (5 * MGA_NR_SAREA_CLIPRECTS))); - mgaEmitState(dev_priv); + MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); do { - if (i < sarea_priv->nbox) { - DRM_DEBUG("idx %d Emit box %d/%d:" - "%d,%d - %d,%d\n", - buf->idx, - i, sarea_priv->nbox, - sarea_priv->boxes[i].x1, - sarea_priv->boxes[i].y1, - sarea_priv->boxes[i].x2, - sarea_priv->boxes[i].y2); - - mgaEmitClipRect(dev_priv, - &sarea_priv->boxes[i]); + if ( i < sarea_priv->nbox ) { + mga_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); } - PRIMGETPTR(dev_priv); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_SETUPADDRESS, - ((address + start) | - SETADD_mode_vertlist)); - PRIMOUTREG(MGAREG_SETUPEND, - ((address + end) | use_agp)); - - PRIMADVANCE(dev_priv); - } while (++i < sarea_priv->nbox); + BEGIN_DMA( 1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_SECADDRESS, (address | + MGA_DMA_VERTEX), + MGA_SECEND, ((address + length) | + MGA_PAGPXFER) ); + + ADVANCE_DMA(); + } while ( ++i < sarea_priv->nbox ); } - if (buf_priv->discard) { - if (buf_priv->dispatched == 1) - AGEBUF(dev_priv, buf_priv); + + if ( buf_priv->discard ) { + AGE_BUFFER( buf_priv ); + buf->pending = 0; + buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put(dev, buf); - } -} + mga_freelist_put( dev, buf ); + } -static void mga_dma_dispatch_clear(drm_device_t * dev, int flags, - unsigned int clear_color, - unsigned int clear_zval, - unsigned int clear_colormask, - unsigned int clear_depthmask) + FLUSH_DMA(); +} +static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, + unsigned int start, unsigned int end ) { drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->ContextState; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - unsigned int cmd; - int i; - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); - - if (dev_priv->sgram) - cmd = MGA_CLEAR_CMD | DC_atype_blk; - else - cmd = MGA_CLEAR_CMD | DC_atype_rstr; - - PRIM_OVERFLOW(dev, dev_priv, 35 * MGA_NR_SAREA_CLIPRECTS); - - for (i = 0; i < nbox; i++) { - unsigned int height = pbox[i].y2 - pbox[i].y1; - - DRM_DEBUG("dispatch clear %d,%d-%d,%d flags %x!\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, - pbox[i].y2, flags); - - if (flags & MGA_FRONT) { - DRM_DEBUG("clear front\n"); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_PLNWT, clear_colormask); - PRIMOUTREG(MGAREG_YDSTLEN, - (pbox[i].y1 << 16) | height); - PRIMOUTREG(MGAREG_FXBNDRY, - (pbox[i].x2 << 16) | pbox[i].x1); - - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_FCOL, clear_color); - PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset); - PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd); - } + u32 address = (u32) buf->bus_address; + int i = 0; + DMA_LOCALS; + DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); - if (flags & MGA_BACK) { - DRM_DEBUG("clear back\n"); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_PLNWT, clear_colormask); - PRIMOUTREG(MGAREG_YDSTLEN, - (pbox[i].y1 << 16) | height); - PRIMOUTREG(MGAREG_FXBNDRY, - (pbox[i].x2 << 16) | pbox[i].x1); - - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_FCOL, clear_color); - PRIMOUTREG(MGAREG_DSTORG, dev_priv->backOffset); - PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd); - } + if ( start != end ) { + buf_priv->dispatched = 1; - if (flags & MGA_DEPTH) { - DRM_DEBUG("clear depth\n"); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_PLNWT, clear_depthmask); - PRIMOUTREG(MGAREG_YDSTLEN, - (pbox[i].y1 << 16) | height); - PRIMOUTREG(MGAREG_FXBNDRY, - (pbox[i].x2 << 16) | pbox[i].x1); - - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_FCOL, clear_zval); - PRIMOUTREG(MGAREG_DSTORG, dev_priv->depthOffset); - PRIMOUTREG(MGAREG_DWGCTL + MGAREG_MGA_EXEC, cmd); - } + MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + + do { + if ( i < sarea_priv->nbox ) { + mga_emit_clip_rect( dev_priv, + &sarea_priv->boxes[i] ); + } + + BEGIN_DMA( 1 ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_SETUPADDRESS, address + start, + MGA_SETUPEND, ((address + end) | + MGA_PAGPXFER) ); + + ADVANCE_DMA(); + } while ( ++i < sarea_priv->nbox ); } - /* Force reset of DWGCTL */ - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); - PRIMADVANCE(dev_priv); + if ( buf_priv->discard ) { + AGE_BUFFER( buf_priv ); + buf->pending = 0; + buf->used = 0; + buf_priv->dispatched = 0; + + mga_freelist_put( dev, buf ); + } + + FLUSH_DMA(); } -static void mga_dma_dispatch_swap(drm_device_t * dev) +/* This copies a 64 byte aligned agp region to the frambuffer with a + * standard blit, the ioctl needs to do checking. + */ +static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, + unsigned int dstorg, unsigned int length ) { drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int *regs = sarea_priv->ContextState; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int i; - int pixel_stride = dev_priv->stride / dev_priv->cpp; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; + u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM; + u32 y2; + DMA_LOCALS; + DRM_DEBUG( "%s: buf=%d used=%d\n", + __FUNCTION__, buf->idx, buf->used ); - PRIMLOCALS; - DRM_DEBUG("%s\n", __FUNCTION__); + y2 = length / 64; - PRIM_OVERFLOW(dev, dev_priv, (MGA_NR_SAREA_CLIPRECTS * 5) + 20); + BEGIN_DMA( 5 ); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0x7100); - PRIMOUTREG(MGAREG_DWGSYNC, 0x7000); + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); - PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset); - PRIMOUTREG(MGAREG_MACCESS, dev_priv->mAccess); - PRIMOUTREG(MGAREG_SRCORG, dev_priv->backOffset); - PRIMOUTREG(MGAREG_AR5, pixel_stride); + DMA_BLOCK( MGA_DSTORG, dstorg, + MGA_MACCESS, 0x00000000, + MGA_SRCORG, srcorg, + MGA_AR5, 64 ); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD); + DMA_BLOCK( MGA_PITCH, 64, + MGA_PLNWT, 0xffffffff, + MGA_DMAPAD, 0x00000000, + MGA_DWGCTL, MGA_DWGCTL_COPY ); + DMA_BLOCK( MGA_AR0, 63, + MGA_AR3, 0, + MGA_FXBNDRY, (63 << 16) | 0, + MGA_YDSTLEN + MGA_EXEC, y2 ); - for (i = 0; i < nbox; i++) { - unsigned int h = pbox[i].y2 - pbox[i].y1; - unsigned int start = pbox[i].y1 * pixel_stride; + DMA_BLOCK( MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, + MGA_PITCH, dev_priv->front_pitch, + MGA_DWGSYNC, 0x00007000 ); - PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1); - PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1); - PRIMOUTREG(MGAREG_FXBNDRY, - pbox[i].x1 | ((pbox[i].x2 - 1) << 16)); - PRIMOUTREG(MGAREG_YDSTLEN + MGAREG_MGA_EXEC, - (pbox[i].y1 << 16) | h); - } + ADVANCE_DMA(); - /* Force reset of DWGCTL */ - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_SRCORG, 0); - PRIMOUTREG(MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL]); + AGE_BUFFER( buf_priv ); + + buf->pending = 0; + buf->used = 0; + buf_priv->dispatched = 0; - PRIMADVANCE(dev_priv); + mga_freelist_put( dev, buf ); + + FLUSH_DMA(); } -int mga_clear_bufs(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) +static void mga_dma_dispatch_blit( drm_device_t *dev, + drm_mga_blit_t *blit ) { - drm_device_t *dev = kdev->si_drv1; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; + drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_clear_t clear; - int s; + drm_mga_context_regs_t *ctx = &sarea_priv->context_state; + drm_clip_rect_t *pbox = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + u32 scandir = 0, i; + DMA_LOCALS; + DRM_DEBUG( __FUNCTION__ ":\n" ); + + BEGIN_DMA( 4 + nbox ); + + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, + MGA_DWGSYNC, 0x00007000 ); + + DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, + MGA_PLNWT, blit->planemask, + MGA_SRCORG, blit->srcorg, + MGA_DSTORG, blit->dstorg ); + + DMA_BLOCK( MGA_SGN, scandir, + MGA_MACCESS, dev_priv->maccess, + MGA_AR5, blit->ydir * blit->src_pitch, + MGA_PITCH, blit->dst_pitch ); + + for ( i = 0 ; i < nbox ; i++ ) { + int srcx = pbox[i].x1 + blit->delta_sx; + int srcy = pbox[i].y1 + blit->delta_sy; + int dstx = pbox[i].x1 + blit->delta_dx; + int dsty = pbox[i].y1 + blit->delta_dy; + int h = pbox[i].y2 - pbox[i].y1; + int w = pbox[i].x2 - pbox[i].x1 - 1; + int start; + + if ( blit->ydir == -1 ) { + srcy = blit->height - srcy - 1; + } - clear = *(drm_mga_clear_t *) data; - DRM_DEBUG("%s\n", __FUNCTION__); + start = srcy * blit->src_pitch + srcx; - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_clear_bufs called without lock held\n"); - return EINVAL; + DMA_BLOCK( MGA_AR0, start + w, + MGA_AR3, start, + MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), + MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); } - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - /* Make sure we restore the 3D state next time. + /* Do something to flush AGP? */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; - mga_dma_dispatch_clear(dev, clear.flags, - clear.clear_color, - clear.clear_depth, - clear.clear_color_mask, - clear.clear_depth_mask); - PRIMUPDATE(dev_priv); - mga_flush_write_combine(); - s = splsofttq(); - mga_dma_schedule(dev, 1); - splx(s); - return 0; + + /* Force reset of DWGCTL */ + DMA_BLOCK( MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_PITCH, dev_priv->front_pitch, + MGA_DWGCTL, ctx->dwgctl ); + + ADVANCE_DMA(); } -int mga_swap_bufs(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) + +/* ================================================================ + * + */ + +int mga_dma_clear( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - int s; + drm_mga_clear_t clear; - DRM_DEBUG("%s\n", __FUNCTION__); + LOCK_TEST_WITH_RETURN( dev ); - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_swap_bufs called without lock held\n"); - return EINVAL; - } + DRM_OS_KRNFROMUSR( clear, (drm_mga_clear_t *) data, sizeof(clear) ); - if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_clear( dev, &clear ); + /* Make sure we restore the 3D state next time. */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; - mga_dma_dispatch_swap(dev); - PRIMUPDATE(dev_priv); - set_bit(MGA_BUF_SWAP_PENDING, - &dev_priv->current_prim->buffer_status); - mga_flush_write_combine(); - s = splsofttq(); - mga_dma_schedule(dev, 1); - splx(s); + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + return 0; } -int mga_iload(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) +int mga_dma_swap( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_iload_t iload; - unsigned long bus_address; - int s; - DRM_DEBUG("%s\n", __FUNCTION__); + LOCK_TEST_WITH_RETURN( dev ); - DRM_DEBUG("Starting Iload\n"); - iload = *(drm_mga_iload_t *) data; + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_iload called without lock held\n"); - return EINVAL; - } + WRAP_TEST_WITH_RETURN( dev_priv ); - buf = dma->buflist[iload.idx]; - buf_priv = buf->dev_private; - bus_address = buf->bus_address; - DRM_DEBUG("bus_address %lx, length %d, destorg : %x\n", - bus_address, iload.length, iload.destOrg); - - if (mgaVerifyIload(dev_priv, - bus_address, iload.destOrg, iload.length)) { - mga_freelist_put(dev, buf); - return EINVAL; - } + mga_dma_dispatch_swap( dev ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - sarea_priv->dirty |= MGA_UPLOAD_CTX; - - mga_dma_dispatch_tex_blit(dev, bus_address, iload.length, - iload.destOrg); - AGEBUF(dev_priv, buf_priv); - buf_priv->discard = 1; - mga_freelist_put(dev, buf); - mga_flush_write_combine(); - s = splsofttq(); - mga_dma_schedule(dev, 1); - splx(s); return 0; } -int mga_vertex(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) +int mga_dma_vertex( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; - DRM_DEBUG("%s\n", __FUNCTION__); + LOCK_TEST_WITH_RETURN( dev ); - vertex = *(drm_mga_vertex_t *) data; - - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_vertex called without lock held\n"); - return EINVAL; - } - - DRM_DEBUG("mga_vertex\n"); + DRM_OS_KRNFROMUSR( vertex, (drm_mga_vertex_t *) data, sizeof(vertex) ); + if(vertex.idx < 0 || vertex.idx > dma->buf_count) DRM_OS_RETURN( EINVAL ); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; buf->used = vertex.used; buf_priv->discard = vertex.discard; - if (!mgaVerifyState(dev_priv)) { - if (vertex.discard) { - if (buf_priv->dispatched == 1) - AGEBUF(dev_priv, buf_priv); + if ( !mga_verify_state( dev_priv ) ) { + if ( vertex.discard ) { + if ( buf_priv->dispatched == 1 ) + AGE_BUFFER( buf_priv ); buf_priv->dispatched = 0; - mga_freelist_put(dev, buf); + mga_freelist_put( dev, buf ); } - DRM_DEBUG("bad state\n"); - return EINVAL; + DRM_OS_RETURN( EINVAL ); } - mga_dma_dispatch_vertex(dev, buf); + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_vertex( dev, buf ); - PRIMUPDATE(dev_priv); - mga_flush_write_combine(); - mga_dma_schedule(dev, 1); return 0; } - -int mga_indices(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) +int mga_dma_indices( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; - DRM_DEBUG("%s\n", __FUNCTION__); - indices = *(drm_mga_indices_t *) data; + LOCK_TEST_WITH_RETURN( dev ); - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_indices called without lock held\n"); - return EINVAL; - } + DRM_OS_KRNFROMUSR( indices, (drm_mga_indices_t *) data, sizeof(indices) ); - DRM_DEBUG("mga_indices\n"); + if(indices.idx < 0 || indices.idx > dma->buf_count) DRM_OS_RETURN( EINVAL ); buf = dma->buflist[indices.idx]; buf_priv = buf->dev_private; buf_priv->discard = indices.discard; - if (!mgaVerifyState(dev_priv)) { - if (indices.discard) { - if (buf_priv->dispatched == 1) - AGEBUF(dev_priv, buf_priv); + if ( !mga_verify_state( dev_priv ) ) { + if ( indices.discard ) { + if ( buf_priv->dispatched == 1 ) + AGE_BUFFER( buf_priv ); buf_priv->dispatched = 0; - mga_freelist_put(dev, buf); + mga_freelist_put( dev, buf ); } - return EINVAL; + DRM_OS_RETURN( EINVAL ); } - mga_dma_dispatch_indices(dev, buf, indices.start, indices.end); + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); - PRIMUPDATE(dev_priv); - mga_flush_write_combine(); - mga_dma_schedule(dev, 1); return 0; } - - -static int -mga_dma_get_buffers(drm_device_t * dev, drm_dma_t * d, struct proc *p) +int mga_dma_iload( DRM_OS_IOCTL ) { - int i, error; + DRM_OS_DEVICE; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = dev->dev_private; drm_buf_t *buf; - DRM_DEBUG("%s\n", __FUNCTION__); - - for (i = d->granted_count; i < d->request_count; i++) { - buf = mga_freelist_get(dev); - if (!buf) - break; - buf->pid = p->p_pid; - error = copyout(&buf->idx, - &d->request_indices[i], - sizeof(buf->idx)); - if (error) return error; - error = copyout(&buf->total, - &d->request_sizes[i], - sizeof(buf->total)); - if (error) return error; - ++d->granted_count; + drm_mga_buf_priv_t *buf_priv; + drm_mga_iload_t iload; + DRM_DEBUG( __FUNCTION__ ":\n" ); + + LOCK_TEST_WITH_RETURN( dev ); + + DRM_OS_KRNFROMUSR( iload, (drm_mga_iload_t *) data, sizeof(iload) ); + +#if 0 + if ( mga_do_wait_for_idle( dev_priv ) ) { + if ( MGA_DMA_DEBUG ) + DRM_INFO( __FUNCTION__": -EBUSY\n" ); + DRM_OS_RETURN( EBUSY ); } +#endif + if(iload.idx < 0 || iload.idx > dma->buf_count) DRM_OS_RETURN( EINVAL ); + + buf = dma->buflist[iload.idx]; + buf_priv = buf->dev_private; + + if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { + mga_freelist_put( dev, buf ); + DRM_OS_RETURN( EINVAL ); + } + + WRAP_TEST_WITH_RETURN( dev_priv ); + + mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + return 0; } -int mga_dma(dev_t kdev, u_long cmd, caddr_t data, - int flags, struct proc *p) +int mga_dma_blit( DRM_OS_IOCTL ) { - drm_device_t *dev = kdev->si_drv1; - drm_device_dma_t *dma = dev->dma; - int retcode = 0; - drm_dma_t d; - DRM_DEBUG("%s\n", __FUNCTION__); + DRM_OS_DEVICE; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_blit_t blit; + DRM_DEBUG( "%s\n", __FUNCTION__ ); - d = *(drm_dma_t *) data; - DRM_DEBUG("%d %d: %d send, %d req\n", - p->p_pid, d.context, d.send_count, d.request_count); + LOCK_TEST_WITH_RETURN( dev ); - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("mga_dma called without lock held\n"); - return EINVAL; - } + DRM_OS_KRNFROMUSR( blit, (drm_mga_blit_t *) data, sizeof(blit) ); - /* Please don't send us buffers. - */ - if (d.send_count != 0) { - DRM_ERROR - ("Process %d trying to send %d buffers via drmDMA\n", - p->p_pid, d.send_count); - return EINVAL; - } + if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - /* We'll send you buffers. - */ - if (d.request_count < 0 || d.request_count > dma->buf_count) { - DRM_ERROR - ("Process %d trying to get %d buffers (of %d max)\n", - p->p_pid, d.request_count, dma->buf_count); - return EINVAL; - } + if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) + DRM_OS_RETURN( EINVAL ); - d.granted_count = 0; + WRAP_TEST_WITH_RETURN( dev_priv ); - if (d.request_count) { - retcode = mga_dma_get_buffers(dev, &d, p); - } + mga_dma_dispatch_blit( dev, &blit ); - DRM_DEBUG("%d returning, granted = %d\n", - p->p_pid, d.granted_count); - *(drm_dma_t *) data = d; - return retcode; + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; + + return 0; } |