diff options
61 files changed, 1500 insertions, 390 deletions
@@ -93,15 +93,6 @@ typedef struct drm_tex_region { unsigned int age; } drm_tex_region_t; -/* Seperate include files for the driver specific structures */ -#include "mga_drm.h" -#include "i810_drm.h" -#include "i830_drm.h" -#include "r128_drm.h" -#include "radeon_drm.h" -#include "sis_drm.h" -#include "gamma_drm.h" - typedef struct drm_version { int version_major; /* Major version */ int version_minor; /* Minor version */ @@ -422,87 +413,8 @@ typedef struct drm_scatter_gather { #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) -/* MGA specific ioctls */ -#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) -#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) -#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) - -/* i810 specific ioctls */ -#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) -#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) -#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) -#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) -#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) -#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) -#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) -#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) -#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) - -/* Rage 128 specific ioctls */ -#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) -#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) - -/* Radeon specific ioctls */ -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t) - -/* Gamma specific ioctls */ -#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) -#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) - -/* SiS specific ioctls */ - -#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) -#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) -#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) -#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) -#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) -#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) -#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) - -/* I830 specific ioctls */ -#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) -#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) -#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) -#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) -#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) -#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) -#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) -#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) -#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) +/* Device specfic ioctls should only be in their respective headers + * The device specific ioctl range is 0x40 to 0x79. */ +#define DRM_COMMAND_BASE 0x40 #endif diff --git a/bsd/gamma/gamma_dma.c b/bsd/gamma/gamma_dma.c index fd0da710..0dee8c74 100644 --- a/bsd/gamma/gamma_dma.c +++ b/bsd/gamma/gamma_dma.c @@ -33,6 +33,8 @@ #include "gamma.h" #include "drmP.h" +#include "drm.h" +#include "gamma_drm.h" #include "gamma_drv.h" diff --git a/bsd/gamma/gamma_drv.c b/bsd/gamma/gamma_drv.c index e58d853c..50658bba 100644 --- a/bsd/gamma/gamma_drv.c +++ b/bsd/gamma/gamma_drv.c @@ -35,6 +35,8 @@ #include <opt_drm_linux.h> #include "gamma.h" #include "drmP.h" +#include "drm.h" +#include "gamma_drm.h" #include "gamma_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/bsd/gamma_drm.h b/bsd/gamma_drm.h index d06763ae..0d58b07b 100644 --- a/bsd/gamma_drm.h +++ b/bsd/gamma_drm.h @@ -48,6 +48,16 @@ typedef struct _drm_gamma_sarea { int vertex_prim; } drm_gamma_sarea_t; +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmGamma.h) + */ + +/* Gamma specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) +#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) + typedef struct drm_gamma_copy { unsigned int DMAOutputAddress; unsigned int DMAOutputCount; diff --git a/bsd/i810/i810_dma.c b/bsd/i810/i810_dma.c index 4558c199..4310851a 100644 --- a/bsd/i810/i810_dma.c +++ b/bsd/i810/i810_dma.c @@ -33,6 +33,8 @@ #include "i810.h" #include "drmP.h" +#include "drm.h" +#include "i810_drm.h" #include "i810_drv.h" #define I810_BUF_FREE 2 @@ -125,7 +127,7 @@ static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) return 0; } - +#if 0 int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { DRM_OS_DEVICE; @@ -150,6 +152,7 @@ int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) vma->vm_page_prot)) DRM_OS_RETURN(EAGAIN); return 0; } +#endif static int i810_map_buffer(drm_buf_t *buf, struct file *filp) { diff --git a/bsd/i810/i810_drv.c b/bsd/i810/i810_drv.c index e1c08127..e76e3a8a 100644 --- a/bsd/i810/i810_drv.c +++ b/bsd/i810/i810_drv.c @@ -38,6 +38,8 @@ #include "i810.h" #include "drmP.h" +#include "drm.h" +#include "i810_drm.h" #include "i810_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/bsd/i810_drm.h b/bsd/i810_drm.h index f2114dd1..990e50e2 100644 --- a/bsd/i810_drm.h +++ b/bsd/i810_drm.h @@ -166,14 +166,34 @@ typedef struct _drm_i810_sarea { } drm_i810_sarea_t; +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmMga.h) + */ + +/* i810 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) +#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) +#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) +#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) +#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) +#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) +#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) +#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) +#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) +#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) +#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) +#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) +#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) +#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) + typedef struct _drm_i810_clear { int clear_color; int clear_depth; int flags; } drm_i810_clear_t; - - /* These may be placeholders if we have more cliprects than * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a diff --git a/bsd/i830/i830_dma.c b/bsd/i830/i830_dma.c index 69b1c8a3..fbdc9523 100644 --- a/bsd/i830/i830_dma.c +++ b/bsd/i830/i830_dma.c @@ -34,6 +34,8 @@ #define __NO_VERSION__ #include "i830.h" #include "drmP.h" +#include "drm.h" +#include "i830_drm.h" #include "i830_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/bsd/i830/i830_drv.c b/bsd/i830/i830_drv.c index 904f3660..ad31d1ef 100644 --- a/bsd/i830/i830_drv.c +++ b/bsd/i830/i830_drv.c @@ -34,6 +34,8 @@ #include <linux/config.h> #include "i830.h" #include "drmP.h" +#include "drm.h" +#include "i830_drm.h" #include "i830_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/bsd/i830_drm.h b/bsd/i830_drm.h index e4a2a257..725ad369 100644 --- a/bsd/i830_drm.h +++ b/bsd/i830_drm.h @@ -201,6 +201,19 @@ typedef struct _drm_i830_sarea { int vertex_prim; } drm_i830_sarea_t; +/* I830 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) +#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) +#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) +#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) +#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) +#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) +#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) +#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) +#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) + typedef struct _drm_i830_clear { int clear_color; int clear_depth; diff --git a/bsd/mga/mga_dma.c b/bsd/mga/mga_dma.c index 9ed5d095..d9449c53 100644 --- a/bsd/mga/mga_dma.c +++ b/bsd/mga/mga_dma.c @@ -36,6 +36,8 @@ #define __NO_VERSION__ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" diff --git a/bsd/mga/mga_drv.c b/bsd/mga/mga_drv.c index 206a77dc..d8af2236 100644 --- a/bsd/mga/mga_drv.c +++ b/bsd/mga/mga_drv.c @@ -37,6 +37,8 @@ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." diff --git a/bsd/mga/mga_state.c b/bsd/mga/mga_state.c index b71f333d..a0bd404a 100644 --- a/bsd/mga/mga_state.c +++ b/bsd/mga/mga_state.c @@ -35,6 +35,8 @@ #define __NO_VERSION__ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #include "drm.h" diff --git a/bsd/mga/mga_warp.c b/bsd/mga/mga_warp.c index 4fe4315c..f11cd922 100644 --- a/bsd/mga/mga_warp.c +++ b/bsd/mga/mga_warp.c @@ -30,6 +30,8 @@ #define __NO_VERSION__ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #include "mga_ucode.h" diff --git a/bsd/mga_drm.h b/bsd/mga_drm.h index 4af2ca2e..8f56beed 100644 --- a/bsd/mga_drm.h +++ b/bsd/mga_drm.h @@ -38,6 +38,7 @@ /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (mga_sarea.h) */ + #ifndef __MGA_SAREA_DEFINES__ #define __MGA_SAREA_DEFINES__ @@ -225,6 +226,20 @@ typedef struct _drm_mga_sarea { /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ + +/* MGA specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) +#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) +#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) +#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) +#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) +#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) +#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) +#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) + typedef struct _drm_mga_warp_index { int installed; unsigned long phys_addr; diff --git a/bsd/r128/r128_cce.c b/bsd/r128/r128_cce.c index 6c4a5e65..36cc3120 100644 --- a/bsd/r128/r128_cce.c +++ b/bsd/r128/r128_cce.c @@ -31,6 +31,8 @@ #define __NO_VERSION__ #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" diff --git a/bsd/r128/r128_drv.c b/bsd/r128/r128_drv.c index 51e08a28..cf59aa0d 100644 --- a/bsd/r128/r128_drv.c +++ b/bsd/r128/r128_drv.c @@ -37,6 +37,8 @@ #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" #if __REALLY_HAVE_SG #include "ati_pcigart.h" diff --git a/bsd/r128/r128_state.c b/bsd/r128/r128_state.c index 0fce0c55..34500bb3 100644 --- a/bsd/r128/r128_state.c +++ b/bsd/r128/r128_state.c @@ -30,6 +30,8 @@ #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" #include "drm.h" diff --git a/bsd/r128_drm.h b/bsd/r128_drm.h index 0fc6a6cd..a8d23008 100644 --- a/bsd/r128_drm.h +++ b/bsd/r128_drm.h @@ -170,6 +170,27 @@ typedef struct drm_r128_sarea { /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmR128.h) */ + +/* Rage 128 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) +#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) +#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) +#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) +#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) +#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) +#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) +#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) +#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) +#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) +#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) +#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) +#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) +#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) +#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) +#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) + typedef struct drm_r128_init { enum { R128_INIT_CCE = 0x01, diff --git a/bsd/radeon/radeon_cp.c b/bsd/radeon/radeon_cp.c index ed5128b2..9c262ae3 100644 --- a/bsd/radeon/radeon_cp.c +++ b/bsd/radeon/radeon_cp.c @@ -30,6 +30,8 @@ #include "radeon.h" #include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" #include "radeon_drv.h" #include <vm/vm.h> @@ -624,7 +626,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", + DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08x\n", entry->busaddr[page_ofs], entry->handle + tmp_ofs ); } diff --git a/bsd/radeon/radeon_drv.c b/bsd/radeon/radeon_drv.c index 61be65f7..009f90c1 100644 --- a/bsd/radeon/radeon_drv.c +++ b/bsd/radeon/radeon_drv.c @@ -36,6 +36,8 @@ #include "radeon.h" #include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" #include "radeon_drv.h" #if __REALLY_HAVE_SG #include "ati_pcigart.h" diff --git a/bsd/radeon/radeon_state.c b/bsd/radeon/radeon_state.c index a7e301e7..cbb9d1f6 100644 --- a/bsd/radeon/radeon_state.c +++ b/bsd/radeon/radeon_state.c @@ -29,8 +29,9 @@ #include "radeon.h" #include "drmP.h" -#include "radeon_drv.h" #include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" /* ================================================================ diff --git a/bsd/radeon_drm.h b/bsd/radeon_drm.h index 81e76b19..6774b2bc 100644 --- a/bsd/radeon_drm.h +++ b/bsd/radeon_drm.h @@ -236,7 +236,29 @@ typedef struct { /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) + * + * KW: actually it's illegal to change any of this (backwards compatibility). + */ + +/* Radeon specific ioctls + * The device specific ioctl range is 0x40 to 0x79. */ +#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) +#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) +#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) +#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) +#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) +#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) +#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) +#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) +#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) +#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) +#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) +#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) +#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) +#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) +#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t) + typedef struct drm_radeon_init { enum { RADEON_INIT_CP = 0x01, diff --git a/bsd/sis_drm.h b/bsd/sis_drm.h index db11cf63..21b66350 100644 --- a/bsd/sis_drm.h +++ b/bsd/sis_drm.h @@ -2,6 +2,16 @@ #ifndef _sis_drm_public_h_ #define _sis_drm_public_h_ +/* SiS specific ioctls */ +#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) +#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) +#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) +#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) +#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) +#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) +#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) +#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) + typedef struct { int context; unsigned int offset; diff --git a/libdrm/xf86drm.c b/libdrm/xf86drm.c index 1d26b6e6..9cc83a27 100644 --- a/libdrm/xf86drm.c +++ b/libdrm/xf86drm.c @@ -434,7 +434,7 @@ static void drmCopyVersion(drmVersionPtr d, const drm_version_t *s) d->desc = drmStrdup(s->desc); } -/* drmVersion obtains the version information via an ioctl. Similar +/* drmGet Version obtains the driver version information via an ioctl. Similar * information is available via /proc/dri. */ drmVersionPtr drmGetVersion(int fd) @@ -483,6 +483,26 @@ drmVersionPtr drmGetVersion(int fd) return retval; } +/* drmGetLibVersion set version information for the drm user space library. + * this version number is driver indepedent */ + +drmVersionPtr drmGetLibVersion(int fd) +{ + drm_version_t *version = drmMalloc(sizeof(*version)); + + /* Version history: + * revision 1.0.x = original DRM interface with no drmGetLibVersion + * entry point and many drm<Device> extensions + * revision 1.1.x = added drmCommand entry points for device extensions + * added drmGetLibVersion to identify libdrm.a version + */ + version->version_major = 1; + version->version_minor = 1; + version->version_patchlevel = 0; + + return (drmVersionPtr)version; +} + void drmFreeBusid(const char *busid) { drmFree((void *)busid); @@ -1343,6 +1363,58 @@ int drmGetStats(int fd, drmStatsT *stats) return 0; } +int drmCommandNone(int fd, unsigned long drmCommandIndex) +{ + void *data = NULL; /* dummy */ + unsigned long request; + + request = DRM_IO( DRM_COMMAND_BASE + drmCommandIndex); + + if (ioctl(fd, request, data)) { + return -errno; + } + return 0; +} + +int drmCommandRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size ) +{ + unsigned long request; + + request = DRM_IOR( DRM_COMMAND_BASE + drmCommandIndex, size); + + if (ioctl(fd, request, data)) { + return -errno; + } + return 0; +} + +int drmCommandWrite(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size ) +{ + unsigned long request; + + request = DRM_IOW( DRM_COMMAND_BASE + drmCommandIndex, size); + + if (ioctl(fd, request, data)) { + return -errno; + } + return 0; +} + +int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size ) +{ + unsigned long request; + + request = DRM_IOWR( DRM_COMMAND_BASE + drmCommandIndex, size); + + if (ioctl(fd, request, data)) { + return -errno; + } + return 0; +} + #if defined(XFree86Server) || defined(DRM_USE_MALLOC) static void drmSIGIOHandler(int interrupt, void *closure) { diff --git a/libdrm/xf86drmCompat.c b/libdrm/xf86drmCompat.c new file mode 100644 index 00000000..efe744ec --- /dev/null +++ b/libdrm/xf86drmCompat.c @@ -0,0 +1,1073 @@ +/* xf86drmCompat.c -- User-level interface to old DRM device drivers + * + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Backwards compatability modules broken out by: + * Jens Owen <jens@tungstengraphics.com> + * + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c,v 1.4 2001/08/27 17:40:59 dawes Exp $ */ + +#ifdef XFree86Server +# include "xf86.h" +# include "xf86_OSproc.h" +# include "xf86_ansic.h" +# define _DRM_MALLOC xalloc +# define _DRM_FREE xfree +# ifndef XFree86LOADER +# include <sys/mman.h> +# endif +#else +# include <stdio.h> +# include <stdlib.h> +# include <unistd.h> +# include <string.h> +# include <ctype.h> +# include <fcntl.h> +# include <errno.h> +# include <signal.h> +# include <sys/types.h> +# include <sys/ioctl.h> +# include <sys/mman.h> +# include <sys/time.h> +# ifdef DRM_USE_MALLOC +# define _DRM_MALLOC malloc +# define _DRM_FREE free +extern int xf86InstallSIGIOHandler(int fd, void (*f)(int, void *), void *); +extern int xf86RemoveSIGIOHandler(int fd); +# else +# include <X11/Xlibint.h> +# define _DRM_MALLOC Xmalloc +# define _DRM_FREE Xfree +# endif +#endif + +/* Not all systems have MAP_FAILED defined */ +#ifndef MAP_FAILED +#define MAP_FAILED ((void *)-1) +#endif + +#ifdef __linux__ +#include <sys/sysmacros.h> /* for makedev() */ +#endif +#include "xf86drm.h" +#include "xf86drmCompat.h" +#include "drm.h" +#include "i810_drm.h" +#include "mga_drm.h" +#include "r128_drm.h" +#include "radeon_drm.h" +#include "sis_drm.h" +#include "i830_drm.h" + + +/* WARNING: Do not change, or add, anything to this file. It is only provided + * for binary backwards compatability with the old driver specific DRM + * extensions used before XFree86 4.3. + */ + +/* I810 */ + +Bool drmI810CleanupDma(int driSubFD) +{ + drm_i810_init_t init; + + memset(&init, 0, sizeof(drm_i810_init_t)); + init.func = I810_CLEANUP_DMA; + + if(ioctl(driSubFD, DRM_IOCTL_I810_INIT, &init)) { + return 0; /* FALSE */ + } + + return 1; /* TRUE */ +} + +Bool drmI810InitDma(int driSubFD, drmCompatI810Init *info) +{ + drm_i810_init_t init; + + memset(&init, 0, sizeof(drm_i810_init_t)); + + init.func = I810_INIT_DMA; + init.mmio_offset = info->mmio_offset; + init.buffers_offset = info->buffers_offset; + init.ring_start = info->start; + init.ring_end = info->end; + init.ring_size = info->size; + init.sarea_priv_offset = info->sarea_off; + init.front_offset = info->front_offset; + init.back_offset = info->back_offset; + init.depth_offset = info->depth_offset; + init.overlay_offset = info->overlay_offset; + init.overlay_physical = info->overlay_physical; + init.w = info->w; + init.h = info->h; + init.pitch = info->pitch; + init.pitch_bits = info->pitch_bits; + + if(ioctl(driSubFD, DRM_IOCTL_I810_INIT, &init)) { + return 0; /* FALSE */ + } + return 1; /* TRUE */ +} + +/* Mga */ + +#define MGA_IDLE_RETRY 2048 + +int drmMGAInitDMA( int fd, drmCompatMGAInit *info ) +{ + drm_mga_init_t init; + + memset( &init, 0, sizeof(drm_mga_init_t) ); + + init.func = MGA_INIT_DMA; + + init.sarea_priv_offset = info->sarea_priv_offset; + init.sgram = info->sgram; + init.chipset = info->chipset; + init.maccess = info->maccess; + + init.fb_cpp = info->fb_cpp; + init.front_offset = info->front_offset; + init.front_pitch = info->front_pitch; + init.back_offset = info->back_offset; + init.back_pitch = info->back_pitch; + + init.depth_cpp = info->depth_cpp; + init.depth_offset = info->depth_offset; + init.depth_pitch = info->depth_pitch; + + init.texture_offset[0] = info->texture_offset[0]; + init.texture_size[0] = info->texture_size[0]; + init.texture_offset[1] = info->texture_offset[1]; + init.texture_size[1] = info->texture_size[1]; + + init.fb_offset = info->fb_offset; + init.mmio_offset = info->mmio_offset; + init.status_offset = info->status_offset; + init.warp_offset = info->warp_offset; + init.primary_offset = info->primary_offset; + init.buffers_offset = info->buffers_offset; + + if ( ioctl( fd, DRM_IOCTL_MGA_INIT, &init ) ) { + return -errno; + } else { + return 0; + } +} + +int drmMGACleanupDMA( int fd ) +{ + drm_mga_init_t init; + + memset( &init, 0, sizeof(drm_mga_init_t) ); + + init.func = MGA_CLEANUP_DMA; + + if ( ioctl( fd, DRM_IOCTL_MGA_INIT, &init ) ) { + return -errno; + } else { + return 0; + } +} + +int drmMGAFlushDMA( int fd, drmLockFlags flags ) +{ + drm_lock_t lock; + int ret, i = 0; + + memset( &lock, 0, sizeof(drm_lock_t) ); + + if ( flags & DRM_LOCK_QUIESCENT ) lock.flags |= _DRM_LOCK_QUIESCENT; + if ( flags & DRM_LOCK_FLUSH ) lock.flags |= _DRM_LOCK_FLUSH; + if ( flags & DRM_LOCK_FLUSH_ALL ) lock.flags |= _DRM_LOCK_FLUSH_ALL; + + do { + ret = ioctl( fd, DRM_IOCTL_MGA_FLUSH, &lock ); + } while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY ); + + if ( ret == 0 ) + return 0; + if ( errno != EBUSY ) + return -errno; + + if ( lock.flags & _DRM_LOCK_QUIESCENT ) { + /* Only keep trying if we need quiescence. + */ + lock.flags &= ~(_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL); + + do { + ret = ioctl( fd, DRM_IOCTL_MGA_FLUSH, &lock ); + } while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY ); + } + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmMGAEngineReset( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_MGA_RESET, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmMGAFullScreen( int fd, int enable ) +{ + return -EINVAL; +} + +int drmMGASwapBuffers( int fd ) +{ + int ret, i = 0; + + do { + ret = ioctl( fd, DRM_IOCTL_MGA_SWAP, NULL ); + } while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmMGAClear( int fd, unsigned int flags, + unsigned int clear_color, unsigned int clear_depth, + unsigned int color_mask, unsigned int depth_mask ) +{ + drm_mga_clear_t clear; + int ret, i = 0; + + clear.flags = flags; + clear.clear_color = clear_color; + clear.clear_depth = clear_depth; + clear.color_mask = color_mask; + clear.depth_mask = depth_mask; + + do { + ret = ioctl( fd, DRM_IOCTL_MGA_CLEAR, &clear ); + } while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmMGAFlushVertexBuffer( int fd, int index, int used, int discard ) +{ + drm_mga_vertex_t vertex; + + vertex.idx = index; + vertex.used = used; + vertex.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_MGA_VERTEX, &vertex ) ) { + return -errno; + } else { + return 0; + } +} + +int drmMGAFlushIndices( int fd, int index, int start, int end, int discard ) +{ + drm_mga_indices_t indices; + + indices.idx = index; + indices.start = start; + indices.end = end; + indices.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_MGA_INDICES, &indices ) ) { + return -errno; + } else { + return 0; + } +} + +int drmMGATextureLoad( int fd, int index, + unsigned int dstorg, unsigned int length ) +{ + drm_mga_iload_t iload; + int ret, i = 0; + + iload.idx = index; + iload.dstorg = dstorg; + iload.length = length; + + do { + ret = ioctl( fd, DRM_IOCTL_MGA_ILOAD, &iload ); + } while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmMGAAgpBlit( int fd, unsigned int planemask, + unsigned int src_offset, int src_pitch, + unsigned int dst_offset, int dst_pitch, + int delta_sx, int delta_sy, + int delta_dx, int delta_dy, + int height, int ydir ) +{ + drm_mga_blit_t blit; + int ret, i = 0; + + blit.planemask = planemask; + blit.srcorg = src_offset; + blit.dstorg = dst_offset; + blit.src_pitch = src_pitch; + blit.dst_pitch = dst_pitch; + blit.delta_sx = delta_sx; + blit.delta_sy = delta_sy; + blit.delta_dx = delta_dx; + blit.delta_dx = delta_dx; + blit.height = height; + blit.ydir = ydir; + + do { + ret = ioctl( fd, DRM_IOCTL_MGA_BLIT, &blit ); + } while ( ret && errno == EBUSY && i++ < MGA_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +/* R128 */ + +#define R128_BUFFER_RETRY 32 +#define R128_IDLE_RETRY 32 + +int drmR128InitCCE( int fd, drmCompatR128Init *info ) +{ + drm_r128_init_t init; + + memset( &init, 0, sizeof(drm_r128_init_t) ); + + init.func = R128_INIT_CCE; + init.sarea_priv_offset = info->sarea_priv_offset; + init.is_pci = info->is_pci; + init.cce_mode = info->cce_mode; + init.cce_secure = info->cce_secure; + init.ring_size = info->ring_size; + init.usec_timeout = info->usec_timeout; + + init.fb_bpp = info->fb_bpp; + init.front_offset = info->front_offset; + init.front_pitch = info->front_pitch; + init.back_offset = info->back_offset; + init.back_pitch = info->back_pitch; + + init.depth_bpp = info->depth_bpp; + init.depth_offset = info->depth_offset; + init.depth_pitch = info->depth_pitch; + init.span_offset = info->span_offset; + + init.fb_offset = info->fb_offset; + init.mmio_offset = info->mmio_offset; + init.ring_offset = info->ring_offset; + init.ring_rptr_offset = info->ring_rptr_offset; + init.buffers_offset = info->buffers_offset; + init.agp_textures_offset = info->agp_textures_offset; + + if ( ioctl( fd, DRM_IOCTL_R128_INIT, &init ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128CleanupCCE( int fd ) +{ + drm_r128_init_t init; + + memset( &init, 0, sizeof(drm_r128_init_t) ); + + init.func = R128_CLEANUP_CCE; + + if ( ioctl( fd, DRM_IOCTL_R128_INIT, &init ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128StartCCE( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_R128_CCE_START, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128StopCCE( int fd ) +{ + drm_r128_cce_stop_t stop; + int ret, i = 0; + + stop.flush = 1; + stop.idle = 1; + + ret = ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop ); + + if ( ret == 0 ) { + return 0; + } else if ( errno != EBUSY ) { + return -errno; + } + + stop.flush = 0; + + do { + ret = ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop ); + } while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else if ( errno != EBUSY ) { + return -errno; + } + + stop.idle = 0; + + if ( ioctl( fd, DRM_IOCTL_R128_CCE_STOP, &stop ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128ResetCCE( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_R128_CCE_RESET, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128WaitForIdleCCE( int fd ) +{ + int ret, i = 0; + + do { + ret = ioctl( fd, DRM_IOCTL_R128_CCE_IDLE, NULL ); + } while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmR128EngineReset( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_R128_RESET, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128FullScreen( int fd, int enable ) +{ + drm_r128_fullscreen_t fs; + + if ( enable ) { + fs.func = R128_INIT_FULLSCREEN; + } else { + fs.func = R128_CLEANUP_FULLSCREEN; + } + + if ( ioctl( fd, DRM_IOCTL_R128_FULLSCREEN, &fs ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128SwapBuffers( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_R128_SWAP, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmR128Clear( int fd, unsigned int flags, + unsigned int clear_color, unsigned int clear_depth, + unsigned int color_mask, unsigned int depth_mask ) +{ + drm_r128_clear_t clear; + + clear.flags = flags; + clear.clear_color = clear_color; + clear.clear_depth = clear_depth; + clear.color_mask = color_mask; + clear.depth_mask = depth_mask; + + if ( ioctl( fd, DRM_IOCTL_R128_CLEAR, &clear ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128FlushVertexBuffer( int fd, int prim, int index, + int count, int discard ) +{ + drm_r128_vertex_t v; + + v.prim = prim; + v.idx = index; + v.count = count; + v.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_R128_VERTEX, &v ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128FlushIndices( int fd, int prim, int index, + int start, int end, int discard ) +{ + drm_r128_indices_t elts; + + elts.prim = prim; + elts.idx = index; + elts.start = start; + elts.end = end; + elts.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_R128_INDICES, &elts ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128TextureBlit( int fd, int index, + int offset, int pitch, int format, + int x, int y, int width, int height ) +{ + drm_r128_blit_t blit; + + blit.idx = index; + blit.offset = offset; + blit.pitch = pitch; + blit.format = format; + blit.x = x; + blit.y = y; + blit.width = width; + blit.height = height; + + if ( ioctl( fd, DRM_IOCTL_R128_BLIT, &blit ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128WriteDepthSpan( int fd, int n, int x, int y, + const unsigned int depth[], + const unsigned char mask[] ) +{ + drm_r128_depth_t d; + + d.func = R128_WRITE_SPAN; + d.n = n; + d.x = &x; + d.y = &y; + d.buffer = (unsigned int *)depth; + d.mask = (unsigned char *)mask; + + if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128WriteDepthPixels( int fd, int n, + const int x[], const int y[], + const unsigned int depth[], + const unsigned char mask[] ) +{ + drm_r128_depth_t d; + + d.func = R128_WRITE_PIXELS; + d.n = n; + d.x = (int *)x; + d.y = (int *)y; + d.buffer = (unsigned int *)depth; + d.mask = (unsigned char *)mask; + + if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128ReadDepthSpan( int fd, int n, int x, int y ) +{ + drm_r128_depth_t d; + + d.func = R128_READ_SPAN; + d.n = n; + d.x = &x; + d.y = &y; + d.buffer = NULL; + d.mask = NULL; + + if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128ReadDepthPixels( int fd, int n, + const int x[], const int y[] ) +{ + drm_r128_depth_t d; + + d.func = R128_READ_PIXELS; + d.n = n; + d.x = (int *)x; + d.y = (int *)y; + d.buffer = NULL; + d.mask = NULL; + + if ( ioctl( fd, DRM_IOCTL_R128_DEPTH, &d ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128PolygonStipple( int fd, unsigned int *mask ) +{ + drm_r128_stipple_t stipple; + + stipple.mask = mask; + + if ( ioctl( fd, DRM_IOCTL_R128_STIPPLE, &stipple ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmR128FlushIndirectBuffer( int fd, int index, + int start, int end, int discard ) +{ + drm_r128_indirect_t ind; + + ind.idx = index; + ind.start = start; + ind.end = end; + ind.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_R128_INDIRECT, &ind ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +/* Radeon */ + +#define RADEON_BUFFER_RETRY 32 +#define RADEON_IDLE_RETRY 16 + +int drmRadeonInitCP( int fd, drmCompatRadeonInit *info ) +{ + drm_radeon_init_t init; + + memset( &init, 0, sizeof(drm_radeon_init_t) ); + + init.func = RADEON_INIT_CP; + init.sarea_priv_offset = info->sarea_priv_offset; + init.is_pci = info->is_pci; + init.cp_mode = info->cp_mode; + init.agp_size = info->agp_size; + init.ring_size = info->ring_size; + init.usec_timeout = info->usec_timeout; + + init.fb_bpp = info->fb_bpp; + init.front_offset = info->front_offset; + init.front_pitch = info->front_pitch; + init.back_offset = info->back_offset; + init.back_pitch = info->back_pitch; + + init.depth_bpp = info->depth_bpp; + init.depth_offset = info->depth_offset; + init.depth_pitch = info->depth_pitch; + + init.fb_offset = info->fb_offset; + init.mmio_offset = info->mmio_offset; + init.ring_offset = info->ring_offset; + init.ring_rptr_offset = info->ring_rptr_offset; + init.buffers_offset = info->buffers_offset; + init.agp_textures_offset = info->agp_textures_offset; + + if ( ioctl( fd, DRM_IOCTL_RADEON_CP_INIT, &init ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonCleanupCP( int fd ) +{ + drm_radeon_init_t init; + + memset( &init, 0, sizeof(drm_radeon_init_t) ); + + init.func = RADEON_CLEANUP_CP; + + if ( ioctl( fd, DRM_IOCTL_RADEON_CP_INIT, &init ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonStartCP( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_RADEON_CP_START, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonStopCP( int fd ) +{ + drm_radeon_cp_stop_t stop; + int ret, i = 0; + + stop.flush = 1; + stop.idle = 1; + + ret = ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop ); + + if ( ret == 0 ) { + return 0; + } else if ( errno != EBUSY ) { + return -errno; + } + + stop.flush = 0; + + do { + ret = ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop ); + } while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else if ( errno != EBUSY ) { + return -errno; + } + + stop.idle = 0; + + if ( ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonResetCP( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_RADEON_CP_RESET, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonWaitForIdleCP( int fd ) +{ + int ret, i = 0; + + do { + ret = ioctl( fd, DRM_IOCTL_RADEON_CP_IDLE, NULL ); + } while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmRadeonEngineReset( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_RADEON_RESET, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonFullScreen( int fd, int enable ) +{ + drm_radeon_fullscreen_t fs; + + if ( enable ) { + fs.func = RADEON_INIT_FULLSCREEN; + } else { + fs.func = RADEON_CLEANUP_FULLSCREEN; + } + + if ( ioctl( fd, DRM_IOCTL_RADEON_FULLSCREEN, &fs ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonSwapBuffers( int fd ) +{ + if ( ioctl( fd, DRM_IOCTL_RADEON_SWAP, NULL ) ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonClear( int fd, unsigned int flags, + unsigned int clear_color, unsigned int clear_depth, + unsigned int color_mask, unsigned int stencil, + void *b, int nbox ) +{ + drm_radeon_clear_t clear; + drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; + drm_clip_rect_t *boxes = (drm_clip_rect_t *)b; + int i; + + clear.flags = flags; + clear.clear_color = clear_color; + clear.clear_depth = clear_depth; + clear.color_mask = color_mask; + clear.depth_mask = stencil; /* misnamed field in ioctl */ + clear.depth_boxes = depth_boxes; + + /* We can remove this when we do real depth clears, instead of + * rendering a rectangle into the depth buffer. This prevents + * floating point calculations being done in the kernel. + */ + for ( i = 0 ; i < nbox ; i++ ) { + depth_boxes[i].f[CLEAR_X1] = (float)boxes[i].x1; + depth_boxes[i].f[CLEAR_Y1] = (float)boxes[i].y1; + depth_boxes[i].f[CLEAR_X2] = (float)boxes[i].x2; + depth_boxes[i].f[CLEAR_Y2] = (float)boxes[i].y2; + depth_boxes[i].f[CLEAR_DEPTH] = (float)clear_depth; + } + + if ( ioctl( fd, DRM_IOCTL_RADEON_CLEAR, &clear ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonFlushVertexBuffer( int fd, int prim, int index, + int count, int discard ) +{ + drm_radeon_vertex_t v; + + v.prim = prim; + v.idx = index; + v.count = count; + v.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_RADEON_VERTEX, &v ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonFlushIndices( int fd, int prim, int index, + int start, int end, int discard ) +{ + drm_radeon_indices_t elts; + + elts.prim = prim; + elts.idx = index; + elts.start = start; + elts.end = end; + elts.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_RADEON_INDICES, &elts ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonLoadTexture( int fd, int offset, int pitch, int format, int width, + int height, drmCompatRadeonTexImage *image ) +{ + drm_radeon_texture_t tex; + drm_radeon_tex_image_t tmp; + int ret; + + tex.offset = offset; + tex.pitch = pitch; + tex.format = format; + tex.width = width; + tex.height = height; + tex.image = &tmp; + + /* This gets updated by the kernel when a multipass blit is needed. + */ + memcpy( &tmp, image, sizeof(drm_radeon_tex_image_t) ); + + do { + ret = ioctl( fd, DRM_IOCTL_RADEON_TEXTURE, &tex ); + } while ( ret && errno == EAGAIN ); + + if ( ret == 0 ) { + return 0; + } else { + return -errno; + } +} + +int drmRadeonPolygonStipple( int fd, unsigned int *mask ) +{ + drm_radeon_stipple_t stipple; + + stipple.mask = mask; + + if ( ioctl( fd, DRM_IOCTL_RADEON_STIPPLE, &stipple ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +int drmRadeonFlushIndirectBuffer( int fd, int index, + int start, int end, int discard ) +{ + drm_radeon_indirect_t ind; + + ind.idx = index; + ind.start = start; + ind.end = end; + ind.discard = discard; + + if ( ioctl( fd, DRM_IOCTL_RADEON_INDIRECT, &ind ) < 0 ) { + return -errno; + } else { + return 0; + } +} + +/* SiS */ + +Bool drmSiSAgpInit(int driSubFD, int offset, int size) +{ + drm_sis_agp_t agp; + + agp.offset = offset; + agp.size = size; + ioctl(driSubFD, SIS_IOCTL_AGP_INIT, &agp); + + return 1; /* TRUE */ +} + +/* I830 */ + +Bool drmI830CleanupDma(int driSubFD) +{ + drm_i830_init_t init; + + memset(&init, 0, sizeof(drm_i830_init_t)); + init.func = I810_CLEANUP_DMA; + + if(ioctl(driSubFD, DRM_IOCTL_I830_INIT, &init)) { + return 0; /* FALSE */ + } + + return 1; /* TRUE */ +} + +Bool drmI830InitDma(int driSubFD, drmCompatI830Init *info) +{ + drm_i830_init_t init; + + memset(&init, 0, sizeof(drm_i830_init_t)); + + init.func = I810_INIT_DMA; + init.mmio_offset = info->mmio_offset; + init.buffers_offset = info->buffers_offset; + init.ring_start = info->start; + init.ring_end = info->end; + init.ring_size = info->size; + init.sarea_priv_offset = info->sarea_off; + init.front_offset = info->front_offset; + init.back_offset = info->back_offset; + init.depth_offset = info->depth_offset; + init.w = info->w; + init.h = info->h; + init.pitch = info->pitch; + init.pitch_bits = info->pitch_bits; + init.back_pitch = info->pitch; + init.depth_pitch = info->pitch; + init.cpp = info->cpp; + + if(ioctl(driSubFD, DRM_IOCTL_I830_INIT, &init)) { + return 0; /* FALSE */ + } + return 1; /* TRUE */ +} + +/* WARNING: Do not change, or add, anything to this file. It is only provided + * for binary backwards compatability with the old driver specific DRM + * extensions used before XFree86 4.3. + */ diff --git a/linux-core/i810_dma.c b/linux-core/i810_dma.c index 4f434199..815633b6 100644 --- a/linux-core/i810_dma.c +++ b/linux-core/i810_dma.c @@ -33,6 +33,8 @@ #define __NO_VERSION__ #include "i810.h" #include "drmP.h" +#include "drm.h" +#include "i810_drm.h" #include "i810_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux-core/i810_drm.h b/linux-core/i810_drm.h index bff61637..6b865d40 100644 --- a/linux-core/i810_drm.h +++ b/linux-core/i810_drm.h @@ -168,14 +168,34 @@ typedef struct _drm_i810_sarea { } drm_i810_sarea_t; +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmMga.h) + */ + +/* i810 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) +#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) +#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) +#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) +#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) +#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) +#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) +#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) +#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) +#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) +#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) +#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) +#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) +#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) + typedef struct _drm_i810_clear { int clear_color; int clear_depth; int flags; } drm_i810_clear_t; - - /* These may be placeholders if we have more cliprects than * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a diff --git a/linux-core/i810_drv.c b/linux-core/i810_drv.c index f792e378..d1a92e2a 100644 --- a/linux-core/i810_drv.c +++ b/linux-core/i810_drv.c @@ -33,6 +33,8 @@ #include <linux/config.h> #include "i810.h" #include "drmP.h" +#include "drm.h" +#include "i810_drm.h" #include "i810_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/linux-core/i830_dma.c b/linux-core/i830_dma.c index 69b1c8a3..fbdc9523 100644 --- a/linux-core/i830_dma.c +++ b/linux-core/i830_dma.c @@ -34,6 +34,8 @@ #define __NO_VERSION__ #include "i830.h" #include "drmP.h" +#include "drm.h" +#include "i830_drm.h" #include "i830_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux-core/i830_drm.h b/linux-core/i830_drm.h index e4a2a257..725ad369 100644 --- a/linux-core/i830_drm.h +++ b/linux-core/i830_drm.h @@ -201,6 +201,19 @@ typedef struct _drm_i830_sarea { int vertex_prim; } drm_i830_sarea_t; +/* I830 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) +#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) +#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) +#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) +#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) +#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) +#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) +#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) +#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) + typedef struct _drm_i830_clear { int clear_color; int clear_depth; diff --git a/linux-core/i830_drv.c b/linux-core/i830_drv.c index 904f3660..ad31d1ef 100644 --- a/linux-core/i830_drv.c +++ b/linux-core/i830_drv.c @@ -34,6 +34,8 @@ #include <linux/config.h> #include "i830.h" #include "drmP.h" +#include "drm.h" +#include "i830_drm.h" #include "i830_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/linux-core/mga_drv.c b/linux-core/mga_drv.c index 91216d24..cc8d728e 100644 --- a/linux-core/mga_drv.c +++ b/linux-core/mga_drv.c @@ -32,6 +32,8 @@ #include <linux/config.h> #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." diff --git a/linux-core/r128_drv.c b/linux-core/r128_drv.c index d8d7be4f..32180a30 100644 --- a/linux-core/r128_drv.c +++ b/linux-core/r128_drv.c @@ -32,6 +32,8 @@ #include <linux/config.h> #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" #include "ati_pcigart.h" diff --git a/linux-core/radeon_drv.c b/linux-core/radeon_drv.c index 847c71c9..4dea95f6 100644 --- a/linux-core/radeon_drv.c +++ b/linux-core/radeon_drv.c @@ -30,6 +30,8 @@ #include <linux/config.h> #include "radeon.h" #include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" #include "radeon_drv.h" #include "ati_pcigart.h" diff --git a/linux/drm.h b/linux/drm.h index 79dd5814..d116f375 100644 --- a/linux/drm.h +++ b/linux/drm.h @@ -99,15 +99,6 @@ typedef struct drm_tex_region { unsigned int age; } drm_tex_region_t; -/* Seperate include files for the i810/mga/r128 specific structures */ -#include "mga_drm.h" -#include "i810_drm.h" -#include "r128_drm.h" -#include "radeon_drm.h" -#include "sis_drm.h" -#include "i830_drm.h" -#include "gamma_drm.h" - typedef struct drm_version { int version_major; /* Major version */ int version_minor; /* Minor version */ @@ -428,92 +419,8 @@ typedef struct drm_scatter_gather { #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) -/* MGA specific ioctls */ -#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) -#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) -#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) - -/* i810 specific ioctls */ -#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) -#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) -#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) -#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) -#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) -#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) -#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) -#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) -#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) -#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) -#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) -#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) -#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) -#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) - - -/* Rage 128 specific ioctls */ -#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) -#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) - -/* Radeon specific ioctls */ -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t) - -/* Gamma specific ioctls */ -#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) -#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) - -/* SiS specific ioctls */ -#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) -#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) -#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) -#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) -#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) -#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) -#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) - -/* I830 specific ioctls */ -#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) -#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) -#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) -#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) -#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) -#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) -#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) -#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) -#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) +/* Device specfic ioctls should only be in their respective headers + * The device specific ioctl range is 0x40 to 0x79. */ +#define DRM_COMMAND_BASE 0x40 #endif diff --git a/linux/gamma_dma.c b/linux/gamma_dma.c index 094f51d6..e18a577c 100644 --- a/linux/gamma_dma.c +++ b/linux/gamma_dma.c @@ -32,6 +32,8 @@ #define __NO_VERSION__ #include "gamma.h" #include "drmP.h" +#include "drm.h" +#include "gamma_drm.h" #include "gamma_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux/gamma_drm.h b/linux/gamma_drm.h index d06763ae..0d58b07b 100644 --- a/linux/gamma_drm.h +++ b/linux/gamma_drm.h @@ -48,6 +48,16 @@ typedef struct _drm_gamma_sarea { int vertex_prim; } drm_gamma_sarea_t; +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmGamma.h) + */ + +/* Gamma specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) +#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) + typedef struct drm_gamma_copy { unsigned int DMAOutputAddress; unsigned int DMAOutputCount; diff --git a/linux/gamma_drv.c b/linux/gamma_drv.c index 58cea241..3d37a5fc 100644 --- a/linux/gamma_drv.c +++ b/linux/gamma_drv.c @@ -32,6 +32,8 @@ #include <linux/config.h> #include "gamma.h" #include "drmP.h" +#include "drm.h" +#include "gamma_drm.h" #include "gamma_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/linux/i810_dma.c b/linux/i810_dma.c index 4f434199..815633b6 100644 --- a/linux/i810_dma.c +++ b/linux/i810_dma.c @@ -33,6 +33,8 @@ #define __NO_VERSION__ #include "i810.h" #include "drmP.h" +#include "drm.h" +#include "i810_drm.h" #include "i810_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux/i810_drm.h b/linux/i810_drm.h index bff61637..6b865d40 100644 --- a/linux/i810_drm.h +++ b/linux/i810_drm.h @@ -168,14 +168,34 @@ typedef struct _drm_i810_sarea { } drm_i810_sarea_t; +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmMga.h) + */ + +/* i810 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) +#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) +#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) +#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) +#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) +#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) +#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) +#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) +#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) +#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) +#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) +#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) +#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) +#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) + typedef struct _drm_i810_clear { int clear_color; int clear_depth; int flags; } drm_i810_clear_t; - - /* These may be placeholders if we have more cliprects than * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a diff --git a/linux/i810_drv.c b/linux/i810_drv.c index f792e378..d1a92e2a 100644 --- a/linux/i810_drv.c +++ b/linux/i810_drv.c @@ -33,6 +33,8 @@ #include <linux/config.h> #include "i810.h" #include "drmP.h" +#include "drm.h" +#include "i810_drm.h" #include "i810_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/linux/i830_dma.c b/linux/i830_dma.c index 69b1c8a3..fbdc9523 100644 --- a/linux/i830_dma.c +++ b/linux/i830_dma.c @@ -34,6 +34,8 @@ #define __NO_VERSION__ #include "i830.h" #include "drmP.h" +#include "drm.h" +#include "i830_drm.h" #include "i830_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux/i830_drm.h b/linux/i830_drm.h index e4a2a257..725ad369 100644 --- a/linux/i830_drm.h +++ b/linux/i830_drm.h @@ -201,6 +201,19 @@ typedef struct _drm_i830_sarea { int vertex_prim; } drm_i830_sarea_t; +/* I830 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) +#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) +#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) +#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) +#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) +#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) +#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) +#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) +#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) + typedef struct _drm_i830_clear { int clear_color; int clear_depth; diff --git a/linux/i830_drv.c b/linux/i830_drv.c index 904f3660..ad31d1ef 100644 --- a/linux/i830_drv.c +++ b/linux/i830_drv.c @@ -34,6 +34,8 @@ #include <linux/config.h> #include "i830.h" #include "drmP.h" +#include "drm.h" +#include "i830_drm.h" #include "i830_drv.h" #define DRIVER_AUTHOR "VA Linux Systems Inc." diff --git a/linux/mga_dma.c b/linux/mga_dma.c index 2a151361..525975a8 100644 --- a/linux/mga_dma.c +++ b/linux/mga_dma.c @@ -36,6 +36,8 @@ #define __NO_VERSION__ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux/mga_drm.h b/linux/mga_drm.h index 4af2ca2e..8f56beed 100644 --- a/linux/mga_drm.h +++ b/linux/mga_drm.h @@ -38,6 +38,7 @@ /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (mga_sarea.h) */ + #ifndef __MGA_SAREA_DEFINES__ #define __MGA_SAREA_DEFINES__ @@ -225,6 +226,20 @@ typedef struct _drm_mga_sarea { /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmMga.h) */ + +/* MGA specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) +#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) +#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) +#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) +#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) +#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) +#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) +#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) + typedef struct _drm_mga_warp_index { int installed; unsigned long phys_addr; diff --git a/linux/mga_drv.c b/linux/mga_drv.c index 91216d24..cc8d728e 100644 --- a/linux/mga_drv.c +++ b/linux/mga_drv.c @@ -32,6 +32,8 @@ #include <linux/config.h> #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." diff --git a/linux/mga_state.c b/linux/mga_state.c index 16919514..17cbc855 100644 --- a/linux/mga_state.c +++ b/linux/mga_state.c @@ -35,6 +35,8 @@ #define __NO_VERSION__ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #include "drm.h" diff --git a/linux/mga_warp.c b/linux/mga_warp.c index fba691b1..4dd998b3 100644 --- a/linux/mga_warp.c +++ b/linux/mga_warp.c @@ -30,6 +30,8 @@ #define __NO_VERSION__ #include "mga.h" #include "drmP.h" +#include "drm.h" +#include "mga_drm.h" #include "mga_drv.h" #include "mga_ucode.h" diff --git a/linux/r128_cce.c b/linux/r128_cce.c index ef11a497..72b8d767 100644 --- a/linux/r128_cce.c +++ b/linux/r128_cce.c @@ -31,6 +31,8 @@ #define __NO_VERSION__ #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux/r128_drm.h b/linux/r128_drm.h index 0fc6a6cd..a8d23008 100644 --- a/linux/r128_drm.h +++ b/linux/r128_drm.h @@ -170,6 +170,27 @@ typedef struct drm_r128_sarea { /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmR128.h) */ + +/* Rage 128 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) +#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) +#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) +#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) +#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) +#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) +#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) +#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) +#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) +#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) +#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) +#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) +#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) +#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) +#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) +#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) + typedef struct drm_r128_init { enum { R128_INIT_CCE = 0x01, diff --git a/linux/r128_drv.c b/linux/r128_drv.c index d8d7be4f..32180a30 100644 --- a/linux/r128_drv.c +++ b/linux/r128_drv.c @@ -32,6 +32,8 @@ #include <linux/config.h> #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" #include "ati_pcigart.h" diff --git a/linux/r128_state.c b/linux/r128_state.c index 9de1b6b9..a5b925f5 100644 --- a/linux/r128_state.c +++ b/linux/r128_state.c @@ -30,6 +30,8 @@ #define __NO_VERSION__ #include "r128.h" #include "drmP.h" +#include "drm.h" +#include "r128_drm.h" #include "r128_drv.h" #include "drm.h" #include <linux/delay.h> diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c index 0acaca8e..0823edd0 100644 --- a/linux/radeon_cp.c +++ b/linux/radeon_cp.c @@ -31,6 +31,8 @@ #define __NO_VERSION__ #include "radeon.h" #include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" #include "radeon_drv.h" #include <linux/interrupt.h> /* For task queue support */ diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h index 81e76b19..6774b2bc 100644 --- a/linux/radeon_drm.h +++ b/linux/radeon_drm.h @@ -236,7 +236,29 @@ typedef struct { /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) + * + * KW: actually it's illegal to change any of this (backwards compatibility). + */ + +/* Radeon specific ioctls + * The device specific ioctl range is 0x40 to 0x79. */ +#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) +#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) +#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) +#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) +#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) +#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) +#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) +#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) +#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) +#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) +#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) +#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) +#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) +#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) +#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t) + typedef struct drm_radeon_init { enum { RADEON_INIT_CP = 0x01, diff --git a/linux/radeon_drv.c b/linux/radeon_drv.c index 847c71c9..4dea95f6 100644 --- a/linux/radeon_drv.c +++ b/linux/radeon_drv.c @@ -30,6 +30,8 @@ #include <linux/config.h> #include "radeon.h" #include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" #include "radeon_drv.h" #include "ati_pcigart.h" diff --git a/linux/radeon_state.c b/linux/radeon_state.c index 2f7b7c14..79b29134 100644 --- a/linux/radeon_state.c +++ b/linux/radeon_state.c @@ -30,8 +30,9 @@ #define __NO_VERSION__ #include "radeon.h" #include "drmP.h" -#include "radeon_drv.h" #include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" #include <linux/delay.h> diff --git a/linux/sis_drm.h b/linux/sis_drm.h index 339ed5a0..8aaee224 100644 --- a/linux/sis_drm.h +++ b/linux/sis_drm.h @@ -2,6 +2,16 @@ #ifndef _sis_drm_public_h_ #define _sis_drm_public_h_ +/* SiS specific ioctls */ +#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) +#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) +#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) +#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) +#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) +#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) +#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) +#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) + typedef struct { int context; unsigned int offset; diff --git a/shared-core/drm.h b/shared-core/drm.h index 79dd5814..d116f375 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -99,15 +99,6 @@ typedef struct drm_tex_region { unsigned int age; } drm_tex_region_t; -/* Seperate include files for the i810/mga/r128 specific structures */ -#include "mga_drm.h" -#include "i810_drm.h" -#include "r128_drm.h" -#include "radeon_drm.h" -#include "sis_drm.h" -#include "i830_drm.h" -#include "gamma_drm.h" - typedef struct drm_version { int version_major; /* Major version */ int version_minor; /* Minor version */ @@ -428,92 +419,8 @@ typedef struct drm_scatter_gather { #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) -/* MGA specific ioctls */ -#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) -#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) -#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) - -/* i810 specific ioctls */ -#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) -#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) -#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) -#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) -#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) -#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) -#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) -#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) -#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) -#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) -#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) -#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) -#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) -#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) - - -/* Rage 128 specific ioctls */ -#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) -#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) - -/* Radeon specific ioctls */ -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t) - -/* Gamma specific ioctls */ -#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) -#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) - -/* SiS specific ioctls */ -#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) -#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) -#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) -#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) -#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) -#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) -#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) - -/* I830 specific ioctls */ -#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) -#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) -#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) -#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) -#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) -#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) -#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) -#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) -#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) +/* Device specfic ioctls should only be in their respective headers + * The device specific ioctl range is 0x40 to 0x79. */ +#define DRM_COMMAND_BASE 0x40 #endif diff --git a/shared/drm.h b/shared/drm.h index 79dd5814..d116f375 100644 --- a/shared/drm.h +++ b/shared/drm.h @@ -99,15 +99,6 @@ typedef struct drm_tex_region { unsigned int age; } drm_tex_region_t; -/* Seperate include files for the i810/mga/r128 specific structures */ -#include "mga_drm.h" -#include "i810_drm.h" -#include "r128_drm.h" -#include "radeon_drm.h" -#include "sis_drm.h" -#include "i830_drm.h" -#include "gamma_drm.h" - typedef struct drm_version { int version_major; /* Major version */ int version_minor; /* Minor version */ @@ -428,92 +419,8 @@ typedef struct drm_scatter_gather { #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) -/* MGA specific ioctls */ -#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) -#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) -#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) - -/* i810 specific ioctls */ -#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) -#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) -#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) -#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) -#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) -#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) -#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) -#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) -#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) -#define DRM_IOCTL_I810_OV0INFO DRM_IOR( 0x49, drm_i810_overlay_t) -#define DRM_IOCTL_I810_FSTATUS DRM_IO ( 0x4a) -#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( 0x4b) -#define DRM_IOCTL_I810_MC DRM_IOW( 0x4c, drm_i810_mc_t) -#define DRM_IOCTL_I810_RSTATUS DRM_IO ( 0x4d ) - - -/* Rage 128 specific ioctls */ -#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) -#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) - -/* Radeon specific ioctls */ -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) -#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex_t) - -/* Gamma specific ioctls */ -#define DRM_IOCTL_GAMMA_INIT DRM_IOW( 0x40, drm_gamma_init_t) -#define DRM_IOCTL_GAMMA_COPY DRM_IOW( 0x41, drm_gamma_copy_t) - -/* SiS specific ioctls */ -#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) -#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) -#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) -#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) -#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) -#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) -#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) - -/* I830 specific ioctls */ -#define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) -#define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) -#define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) -#define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) -#define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) -#define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) -#define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) -#define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) -#define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) +/* Device specfic ioctls should only be in their respective headers + * The device specific ioctl range is 0x40 to 0x79. */ +#define DRM_COMMAND_BASE 0x40 #endif |