diff options
| author | Marek Olšák <maraeo@gmail.com> | 2012-07-29 15:20:15 +0200 |
|---|---|---|
| committer | Marek Olšák <maraeo@gmail.com> | 2012-08-09 16:37:20 +0200 |
| commit | 23372955730048bbcddafc74365d911f9a74fb13 (patch) | |
| tree | 9ebb2ef122e1a697612262627c649b2e5a9438ff /radeon | |
| parent | ad66c17209811acdae21e44290a449523882a734 (diff) | |
radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'radeon')
| -rw-r--r-- | radeon/radeon_surface.c | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 5800c334..874a0927 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -604,7 +604,11 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, } } - if (surf->flags & RADEON_SURF_SBUFFER) { + /* The depth and stencil buffers are in separate resources on evergreen. + * We allocate them in one buffer next to each other to simplify + * communication between the DDX and the Mesa driver. */ + if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == + (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4; } @@ -656,7 +660,8 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, } } - if (surf->flags & RADEON_SURF_SBUFFER) { + if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == + (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4; } @@ -752,14 +757,7 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; - /* for some reason eg need to have room for stencil right after depth */ - if (surf->flags & RADEON_SURF_ZBUFFER) { - surf->flags |= RADEON_SURF_SBUFFER; - } - if (surf->flags & RADEON_SURF_SBUFFER) { - surf->flags |= RADEON_SURF_ZBUFFER; - } - if (surf->flags & RADEON_SURF_ZBUFFER) { + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { /* zbuffer only support 1D or 2D tiled surface */ switch (mode) { case RADEON_SURF_MODE_1D: @@ -828,11 +826,6 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; - /* for some reason eg need to have room for stencil right after depth */ - if (surf->flags & RADEON_SURF_ZBUFFER) { - surf->flags |= RADEON_SURF_SBUFFER; - } - /* set some default value to avoid sanity check choking on them */ surf->tile_split = 1024; surf->bankw = 1; |