Update to cache flushing, syncing. Add back some code that got removed

    accidentally, should fix some visual corruption problems.

4 files changed, 37 insertions, 14 deletions

diff --git a/linux/r128_cce.c b/linux/r128_cce.c
index d4035045..d2afabe9 100644
--- a/linux/r128_cce.c
+++ b/linux/r128_cce.c
@@ -262,7 +262,7 @@ static void r128_do_cce_start( drm_r128_private_t *dev_priv )
 }
 
 /* Reset the Concurrent Command Engine.  This will not flush any pending
- * commangs, so you must wait for the CCE command stream to complete
+ * commands, so you must wait for the CCE command stream to complete
  * before calling this routine.
  */
 static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
@@ -274,7 +274,7 @@ static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
 }
 
 /* Stop the Concurrent Command Engine.  This will not flush any pending
- * commangs, so you must flush the command stream and wait for the CCE
+ * commands, so you must flush the command stream and wait for the CCE
  * to go idle before calling this routine.
  */
 static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c
index 1af1aade..0aa0f780 100644
--- a/linux/radeon_cp.c
+++ b/linux/radeon_cp.c
@@ -451,10 +451,20 @@ static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
  */
 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 {
+	RING_LOCALS;
+
+	BEGIN_RING( 6 );
+
+	RADEON_PURGE_CACHE();
+	RADEON_PURGE_ZCACHE();
+	RADEON_WAIT_UNTIL_IDLE();
+
+	ADVANCE_RING();
+
 	return radeon_do_wait_for_idle( dev_priv );
 }
 
-/* Start the Concurrent Command Engine.
+/* Start the Command Processor.
  */
 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 {
@@ -468,15 +478,15 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 
 	BEGIN_RING( 6 );
 
-	RADEON_FLUSH_CACHE();
-	RADEON_FLUSH_ZCACHE();
+	RADEON_PURGE_CACHE();
+	RADEON_PURGE_ZCACHE();
 	RADEON_WAIT_UNTIL_IDLE();
 
 	ADVANCE_RING();
 }
 
-/* Reset the Concurrent Command Engine.  This will not flush any pending
- * commangs, so you must wait for the CP command stream to complete
+/* Reset the Command Processor.  This will not flush any pending
+ * commands, so you must wait for the CP command stream to complete
  * before calling this routine.
  */
 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
@@ -489,8 +499,8 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 	dev_priv->ring.tail = cur_read_ptr;
 }
 
-/* Stop the Concurrent Command Engine.  This will not flush any pending
- * commangs, so you must flush the command stream and wait for the CP
+/* Stop the Command Processor.  This will not flush any pending
+ * commands, so you must flush the command stream and wait for the CP
  * to go idle before calling this routine.
  */
 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
index d97aa4b8..d6afd13d 100644
--- a/linux/radeon_drv.h
+++ b/linux/radeon_drv.h
@@ -310,6 +310,7 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_RB3D_ZCACHE_CTLSTAT	0x3254
 #	define RADEON_RB3D_ZC_FLUSH		(1 << 0)
 #	define RADEON_RB3D_ZC_FREE		(1 << 2)
+#	define RADEON_RB3D_ZC_FLUSH_ALL		0x5
 #	define RADEON_RB3D_ZC_BUSY		(1 << 31)
 #define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
 #	define RADEON_Z_TEST_MASK		(7 << 4)
@@ -597,6 +598,12 @@ do {									\
 	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
 } while (0)
 
+#define RADEON_PURGE_ZCACHE()						\
+do {									\
+	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
+	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
+} while (0)
+
 
 /* ================================================================
  * Misc helper macros
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
index 01918de7..57021f41 100644
--- a/linux/radeon_state.c
+++ b/linux/radeon_state.c
@@ -662,7 +662,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			/* FIXME: Render a rectangle to clear the depth
 			 * buffer.  So much for those "fast Z clears"...
 			 */
-			BEGIN_RING( 20 );
+			BEGIN_RING( 50 );
+
+			RADEON_WAIT_UNTIL_IDLE();
+			RADEON_PURGE_CACHE();
+			RADEON_PURGE_ZCACHE();
+			RADEON_WAIT_UNTIL_IDLE();
 
 			OUT_RING( CP_PACKET0( RADEON_RB3D_CNTL, 0 ) );
 			OUT_RING( rb3d_cntl );
@@ -692,8 +697,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			OUT_RING( clear->rect.ui[CLEAR_X2] );
 			OUT_RING( clear->rect.ui[CLEAR_Y2] );
 			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
-
-			ADVANCE_RING();
 		}
 	}
 
@@ -706,7 +709,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 	BEGIN_RING( 4 );
 
 	RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
-	RADEON_WAIT_UNTIL_2D_IDLE();
+	RADEON_WAIT_UNTIL_IDLE();
 
 	ADVANCE_RING();
 }
@@ -743,6 +746,9 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 		break;
 	}
 
+	/* Wait for the 3D stream to idle before dispatching the bitblt.
+	 * This will prevent data corruption between the two streams.
+	 */
 	BEGIN_RING( 2 );
 
 	RADEON_WAIT_UNTIL_3D_IDLE();
@@ -1098,7 +1104,7 @@ static int radeon_cp_dispatch_blit( drm_device_t *dev,
 	BEGIN_RING( 4 );
 
 	RADEON_FLUSH_CACHE();
-	RADEON_WAIT_UNTIL_3D_IDLE();
+	RADEON_WAIT_UNTIL_IDLE();
 
 	ADVANCE_RING();