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2016-11-22libdrm: random typo fixesGrazvydas Ignotas2-5/+5
Just some trivial boring typo fixes all over the tree. READMEs and comments only. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-11-22intel: Add drm_intel_gem_context_get_id to intel-symbols-checkMichel Dänzer1-0/+1
Fixes make check. Trivial.
2016-11-21intel: Add a getter for the intel_context ctx_idRobert Bragg2-0/+13
Exposing the u32 context ID makes it possible to define new drm kernel interfaces based on the same IDs that e.g. execbuf uses to identify a gem context, that aren't themselves abstracted by libdrm but need to be used by libdrm/drm_intel_context based clients such as (parts of) i-g-t or Mesa. For example this can be used to configure an i915-perf stream to collect metrics for a specific context. v2: s/drm_intel_gem_context_get_context_id/drm_intel_gem_context_get_id/ Signed-off-by: Robert Bragg <robert@sixbynine.org> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
2016-11-18intel: Add Geminilake PCI IDsBen Widawsky1-3/+10
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-11-14intel: Add uthash.h to Makefile.sources.Matt Turner1-1/+2
2016-11-14intel: Allow some codenames in INTEL_DEVID_OVERRIDENeil Roberts1-1/+29
As well as allowing a hexadecimal PCI ID number, the INTEL_DEVID_OVERRIDE environment variable can now contain one of a few short codenames. The codenames are stored in a small table to map them to a corresponding PCI ID. This makes it easier to use without having to look up the PCI IDs manually. The PCI IDs used are the same as those chosen for the -p option of run.c in shader-db but SKL has been added as well. Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-10-24intel: Look prime handle up in handle hash tableChris Wilson1-1/+1
A slightly confused copy'n'paste from the open path where we pass in handle but use it as a global name, in the prime handle-from-fd pass we pass in handle and do mean handle! References: https://bugs.freedesktop.org/show_bug.cgi?id=98416 Fixes: 2f23bf1b7b89 ("intel: Migrate handle/name lookups from linear lists...") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-24intel: Add new symbols to intel-symbol-checkMichel Dänzer1-0/+3
Fixes make check. Trivial.
2016-10-22intel: Migrate handle/name lookups from linear lists to hashtablesChris Wilson2-101/+1181
Walking a linear list to find a matching PRIME handle or flinked name does not scale and becomes a major burden with just a few objects. That said, the fixed size hash is not much better, it just buckets the look into a few separate chains rather than one long one. References: https://bugs.freedesktop.org/show_bug.cgi?id=94631 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-22intel: Export raw GEM mmap interfacesChris Wilson2-0/+158
Export a set of interfaces to allow the caller to have precise control over mapping the buffer - but still provide caching of the mmaps between callers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-08intel: Add new symbols to intel-symbol-checkMichel Dänzer1-0/+2
Fixes make check. Trivial.
2016-09-07intel: Export pooled EU and min no. of eus in a pool.Yang Rong2-0/+33
Update kernel interface with new I915_GETPARAM ioctl entries for pooled EU and min no. of eus in a pool. Add a wrapping function for each parameter. Userspace drivers need these values when decide the thread count. This kernel enabled pooled eu by default for BXT and for fused down 2x6 parts it is advised to turn it off. But there is another HW issue in these parts (fused down 2x6 parts) before C0 that requires Pooled EU to be enabled as a workaround. In this case the pool configuration changes depending upon which subslice is disabled and the no. of eus in a pool is different, So userspace need to know min no. of eus in a pool. V2: use return value as the query results. ret < 0 when error, ret = 0 when not support, and ret > 0 indicate query results.(Chris) V3: Correct V2 errors. Signed-off-by: Yang Rong <rong.r.yang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-07-23automake: Don't include Android Makefiles in the release tarballAndreas Boll1-1/+0
Currently only some Android Makefiles are included in the release tarball. To be more consistent one could either add the remaining files or don't ship Android Makefiles altogether. According to Emil the Android folk doesn't use our release tarballs. Thus it makes sense to remove those files from distribution which also means less work for maintenance in the future. Suggested-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-07-06Android: strip out header files from sources listRob Herring1-1/+1
AOSP master now errors if LOCAL_SRC_FILES contains headers, so filter out header files from the source lists. Signed-off-by: Rob Herring <robh@kernel.org>
2016-06-29intel: Removing PCI IDs that are no longer listed as Kabylake.Rodrigo Vivi1-13/+3
This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. v2: Rebase. Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-06-29intel: Add more Kabylake PCI IDs.Rodrigo Vivi1-4/+10
The spec has been updated adding new PCI IDs. v2: Avoid using "H" instead of HALO to keep names uniform - DK. Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-04-27intel/skl: Add missing SKL PCI IDsMichał Winiarski1-8/+16
Used by production devices: Intel(R) HD Graphics 510 Intel(R) HD Graphics 535 Intel(R) Iris(TM) Graphics 550 Intel(R) Iris(TM) Graphics P555 Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-07intel: Fix spelling mistakesEric Engestrom5-5/+5
Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-03-02intel: Adding missing Broxton PCI IDs.Rodrigo Vivi1-1/+5
These IDs were already part of the kernel since: kernel commit 985dd4360fdf2533fe48a33a4a2094f2e4718dc0 Author: Imre Deak <imre.deak@intel.com> Date: Thu Jan 28 16:04:12 2016 +0200 drm/i915/bxt: update list of PCIIDs Cc: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
2016-01-20configure.ac: disable annoying warning -Wmissing-field-initializersMarek Olšák1-2/+0
It warns for all "{}" initializers. Reviewed-by: David Herrmann <dh.herrmann@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-06intel/kbl: Add Kabylake PCI idsRodrigo Vivi1-1/+56
Also, following kernel definition Kabylake is skylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2015-12-22intel: Restore formatting of offsets in debug statementslibdrm-2.4.66Michał Winiarski1-9/+14
Using lower_32_bits and upper_32_bits macros was accidentally dropped in: commit 8b4d57e7b75cb0bd01d11ad7f597909034a316aa Author: Michał Winiarski <michal.winiarski@intel.com> Date: Wed Sep 9 16:07:10 2015 +0200 intel: Add support for softpin Let's restore previous, more readable format. Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-14intel: Add drm_intel_bo_set_softpin_offset to intel-symbol-checkKristian Høgsberg Kristensen1-0/+1
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14intel: Add support for softpinMichał Winiarski4-27/+169
Softpin allows userspace to take greater control of GPU virtual address space and eliminates the need of relocations. It can also be used to mirror addresses between GPU and CPU (shared virtual memory). Calls to drm_intel_bo_emit_reloc are still required to build the list of drm_i915_gem_exec_objects at exec time, but no entries in relocs are created. Self-relocs don't make any sense for softpinned objects and can indicate a programming errors, thus are forbidden. Softpinned objects are marked by asterisk in debug dumps. Cc: Thomas Daniel <thomas.daniel@intel.com> Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: Zou Nanhai <nanhai.zou@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2015-12-14intel: add drm_intel_bo_use_48b_address_range to symbol-check testMichel Thierry1-0/+1
Signed-off-by: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)Michel Thierry4-19/+95
Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x00000000-0xfffff000) General State Heap (GSH) or Instruction State Heap (ISH) must be in a 32-bit range, because the General State Offset and Instruction State Offset are limited to 32-bits. The i915 driver has been modified to provide a flag to set when the 4GB limit is not necessary in a given bo (EXEC_OBJECT_SUPPORTS_48B_ADDRESS). 48-bit range will only be used when explicitly requested. Callers to the existing drm_intel_bo_emit_reloc function should set the use_48b_address_range flag beforehand, in order to use full ppgtt range. v2: Make set/clear functions nops on pre-gen8 platforms, and use them internally in emit_reloc functions (Ben) s/48BADDRESS/48B_ADDRESS/ (Dave) v3: Keep set/clear functions internal, no-one needs to use them directly. v4: Don't set 48bit-support flag in emit reloc, check for ppgtt type before enabling set/clear function, print full offsets in debug statements, using port of lower_32_bits and upper_32_bits from linux kernel (Michał) References: http://lists.freedesktop.org/archives/intel-gfx/2015-July/072612.html Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-01intel: add the missing <strings.h> includeChih-Wei Huang1-0/+1
It defines the prototype of ffs that fixes the building error on Android 6.0 64-bit image. Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-11-03intel: Cleanup SKL PCI ID definitions.Ben Widawsky1-18/+22
This removes ones which aren't used, and adds some new ones. I kept the original names where possible. Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-11-03intel: Add SKL GT4 PCI IDsBen Widawsky1-4/+14
Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-09-04intel: ignore missing-field-initializers warningsEmil Velikov1-0/+3
We're about to remove the -Wno flag from configure.ac which will lead to a lot of unnecessary spam. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-09-04intel: introduce to_bo_gem() helperEmil Velikov1-6/+9
...to minimise misuse of bo_gem. If the variable is declared at the top of the function and then used for two (or more) different contexts this can cause confusion and errors. Just introduce a wrapper, which can be used in a once off situations. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by Chris Wilson <chris@chris-wilson.co.uk>
2015-09-04intel: error out on has_error in exec2Emil Velikov1-2/+5
Just like we do for the original exec() v2: move bo_gem declaration to the top of the function. Cc: intel-gfx@lists.freedesktop.org Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by Chris Wilson <chris@chris-wilson.co.uk>
2015-09-04intel: resolve shadowing warningsEmil Velikov3-10/+6
v2: keep the bo_gem declaration in exec2() within the loop (Chris) Cc: intel-gfx@lists.freedesktop.org Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by Chris Wilson <chris@chris-wilson.co.uk>
2015-08-21intel: Serialize drmPrimeFDToHandle with struct_mutexRafał Sapała1-7/+7
It is possible to hit a race condition in create_from_prime, when trying to import a BO that's currently being freed. In case of prime sharing we'll succesfully get a handle, but fail on get_tiling call, potentially confusing the caller (and requiring different locking scheme than with sharing using flink). Wrap fd_to_handle with struct_mutex to force a more consistent behaviour between prime/flink, convert fprintf to DBG when handling errors. (From Chris: The race is that the kernel returns us the same file-private handle as the first thread, but that first thread is about to call gem_close (thereby removing the handle from the file completely) and does so between us acquiring the handle and taking the mutex. If we take the mutex, then we acquire the refcnt on the bo prior to the first thread completing its unref (and so preventing the early close). Or we acquire the handle after the earlier close, in which case we are the new owner. ) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Testcase: igt/drm_import_export/import-close-race-prime Signed-off-by: Rafał Sapała <rafal.a.sapala@intel.com> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2015-08-10intel: wrap intel_bufmgr.h C code for C++ compilation/linkingTapani Pälli1-0/+8
We need this include in porting changes for the OpenGL ES conformance suite. v2: remove c_plusplus usage Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-03intel: Drop aub dumping functionalityKristian Høgsberg Kristensen1-370/+5
We now have a separate tool for this in intel-gpu-tools and we don't need to clutter up libdrm with this feature. We leave the entry points in there to avoid breaking API/ABI. Install intel-gpu-tools, then run (for example) $ intel_aubdump --output=trace.aub glxgears -geometry 500x500 See the intel_aubdump man page for more details. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-07-16Consistently check the fd valueEmil Velikov1-1/+1
Follow the approach used through the rest of the project. Suggested-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2015-07-06Set alignment value in drm_intel_add_validate_buffer()Anuj Phogat1-2/+2
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-07-06i965/gen9: Pass alignment as function parameter in ↵Anuj Phogat1-14/+21
drm_intel_gem_bo_alloc_internal() In case of YF/YS tiled buffers libdrm need not know about the tiling format because these buffers don't have hardware support to be tiled or detiled through a fenced region. But, libdrm still need to know about buffer alignment restrictions because kernel uses it when resolving the relocation. Mesa uses drm_intel_gem_bo_alloc_for_render() to allocate Yf/Ys buffers. So, use the passed alignment value in this function to initialize the align variable in drm_intel_bo. Note that we continue ignoring the alignment value passed to drm_intel_gem_bo_alloc() to follow the previous behavior. V2: Add a condition to avoid allocation from cache. (Ben) V3: Make no changes in cache allocation strategy. Just update the alignment. Update the aperture size estimate including the alignment. (Ben, Chris) V4: Move aperture size adjustments inside drm_intel_bo_gem_set_in_aperture_size() Don't split sentences across the one-line header and the changelog. (Chris) Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-05-18intel: Add the Broxton PCI IDsDamien Lespiau1-1/+10
Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2015-04-29intel: Leak the userptr test boTvrtko Ursulin1-11/+28
In order to use userptr, the kernel tracks the owner's mm with a mmu_notifier. Setting that is very expensive - it involves taking all mm_locks and a stop_machine(). This tracking lives only for as long as the client is using userptr objects - so if the client allocates then frees a userptr in a loop, we will be executing that heavyweight setup everytime. To ammoritize this cost, just leak the test bo and the single backing page we use for detecting userptr. v2: Free the object and memory when bufmgr is destroyed. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2015-04-28drm: use c99 __func__ over __FUNCTION__Emil Velikov1-12/+7
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28configure: request/set the compiler in C99 modeEmil Velikov1-2/+0
Required by intel and drmstat at least. Considering that every compiler used to build libdrm is C99 compatible, just enable it for the whole build. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28drm: remove drm_public macroEmil Velikov4-71/+71
Some compilers (like the Oracle Studio), require that the function declaration must be annotated with the same visibility attribute as the definition. As annotating functions with drm_public is no longer required just remove the macro. Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28drm: remove no longer needed VISIBILITY_CFLAGSEmil Velikov1-1/+0
With earlier commits we've annotated the private symbols, thus we no longer require the -fvisibility=hidden CFLAGS. Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28drm: rename libdrm{,_macros}.hEmil Velikov7-7/+7
Provide a more meaningful name, considering what it does. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28intel: add symbols testEmil Velikov2-2/+92
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28intel: annotate the private symbolsEmil Velikov2-12/+24
They are less and easier to track than the public ones. The macro drm_public will be going away by the end of the series. Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28intel: remove unused mmFindBlockEmil Velikov2-19/+0
The function was never part of the public API and a release or so back was hidden from the global name-space (list of exported symbols). According to git log this function was never used internally. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28intel: remove the drm_mm* symbol workaroundsEmil Velikov1-10/+0
Added with commit 57b4c4c32d3(Move the renaming of mm.c symbols to symbol duplication/collision with ones that are available elsewhere. As the public/private symbols of libdrm are properly annotated neither one of the symbols will end up in the global name-space, thus should no longer be required. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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