// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2017 Microsemi Corporation */ / { #address-cells = <1>; #size-cells = <1>; compatible = "mscc,ocelot"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "mips,mips24KEc"; device_type = "cpu"; clocks = <&cpu_clk>; reg = <0>; }; }; aliases { serial0 = &uart0; }; cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; compatible = "mti,cpu-interrupt-controller"; }; cpu_clk: cpu-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <500000000>; }; ahb_clk: ahb-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clocks = <&cpu_clk>; clock-div = <2>; clock-mult = <1>; }; ahb@70000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x70000000 0x2000000>; interrupt-parent = <&intc>; cpu_ctrl: syscon@0 { compatible = "mscc,ocelot-cpu-syscon", "syscon"; reg = <0x0 0x2c>; }; intc: interrupt-controller@70 { compatible = "mscc,ocelot-icpu-intr"; reg = <0x70 0x70>; #interrupt-cells = <1>; interrupt-controller; interrupt-parent = <&cpuintc>; interrupts = <2>; }; uart0: serial@100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x100000 0x20>; interrupts = <6>; clocks = <&ahb_clk>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; uart2: serial@100800 { pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x100800 0x20>; interrupts = <7>; clocks = <&ahb_clk>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; reset@1070008 { compatible = "mscc,ocelot-chip-reset"; reg = <0x1070008 0x4>; }; gpio: pinctrl@1070034 { compatible = "mscc,ocelot-pinctrl"; reg = <0x1070034 0x68>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 22>; uart_pins: uart-pins { pins = "GPIO_6", "GPIO_7"; function = "uart"; }; uart2_pins: uart2-pins { pins = "GPIO_12", "GPIO_13"; function = "uart2"; }; }; }; };