From 2902ba682ae1b59687b5ae8794202a4649e62954 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 29 Sep 2023 16:26:07 +0200 Subject: clk: versaclock5: Convert to use maple tree register cache The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-3-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-versaclock5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/clk-versaclock5.c') diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 17cbb30d20ad..6d31cd54d7cf 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -217,7 +217,7 @@ static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) static const struct regmap_config vc5_regmap_config = { .reg_bits = 8, .val_bits = 8, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, .max_register = 0x76, .writeable_reg = vc5_regmap_is_writeable, }; -- cgit v1.2.3