From 55e9741a323fb77a11c368de51f8a4fa757311df Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 19 Jun 2013 19:25:06 +0200 Subject: MIPS: Sibyte: Fix build for SIBYTE_BW_TRACE on BCM1x55 and BCM1x80. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CC arch/mips/mm/cerr-sb1.o arch/mips/mm/cerr-sb1.c: In function ‘sb1_cache_error’: arch/mips/mm/cerr-sb1.c:186:98: error: ‘M_BCM1480_SCD_TRACE_CFG_FREEZE’ undeclared (first use in this function) arch/mips/mm/cerr-sb1.c:186:98: note: each undeclared identifier is reported only once for each function it appears in make[1]: *** [arch/mips/mm/cerr-sb1.o] Error 1 This happens because 8deab1144b553548fb2f1b51affdd36dcd652aaa [[MIPS] Updated Sibyte headers] changed the headers but not all the users. Signed-off-by: Ralf Baechle Reported-by: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/5511/ --- arch/mips/mm/cerr-sb1.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 576add33bf5b..ee5c1ff861ae 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -182,11 +182,7 @@ asmlinkage void sb1_cache_error(void) #ifdef CONFIG_SIBYTE_BW_TRACE /* Freeze the trace buffer now */ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) - csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); -#else csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); -#endif printk("Trace buffer frozen\n"); #endif -- cgit v1.2.3 From 73acc7df534ff458a81435178dab3ea037ed6d78 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 20 Jun 2013 14:56:17 +0200 Subject: MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers MIPS R2 documents state that an execution hazard barrier is needed after a TLBR before reading EntryLo. Original patch by Leonid Yegoshin . Signed-off-by: Ralf Baechle Patchwork: https://patchwork.linux-mips.org/patch/5526/ --- arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index afeef93f81a7..f0f4dc44f394 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_i_nop(&p); uasm_i_tlbr(&p); + + switch (current_cpu_type()) { + default: + if (cpu_has_mips_r2) { + uasm_i_ehb(&p); + + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + break; + } + } + /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); @@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_load_handler(void) uasm_i_nop(&p); uasm_i_tlbr(&p); + + switch (current_cpu_type()) { + default: + if (cpu_has_mips_r2) { + uasm_i_ehb(&p); + + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + break; + } + } + /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); -- cgit v1.2.3 From a3d9086bb121a6459c9ed0452e3c58891a504785 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Fri, 21 Jun 2013 17:48:48 +0000 Subject: MIPS: Flush TLB handlers directly after writing them When having enabled MIPS_PGD_C0_CONTEXT, trap_init() might call the generated tlbmiss_handler_setup_pgd before it was committed to memory, causing boot failures: trap_init() |- per_cpu_trap_init() | |- TLBMISS_HANDLER_SETUP() | |- tlbmiss_handler_setup_pgd() |- flush_tlb_handlers() To avoid this, move flush_tlb_handlers() into build_tlb_refill_handler() right after they were generated. We can do this as the cache handling is initialized just before creating the tlb handlers. This issue was introduced in 3d8bfdd0307223de678962f1c1907a7cec549136 ("MIPS: Use C0_KScratch (if present) to hold PGD pointer."). Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: Steven J. Hill Cc: Jayachandran C Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/5539/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 2 -- arch/mips/mm/tlbex.c | 30 ++++++++++++++++-------------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/mips/mm') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a75ae40184aa..8ef484c6b9d8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1627,7 +1627,6 @@ void *set_vi_handler(int n, vi_handler_t addr) } extern void tlb_init(void); -extern void flush_tlb_handlers(void); /* * Timer interrupt @@ -1956,7 +1955,6 @@ void __init trap_init(void) set_handler(0x080, &except_vec3_generic, 0x80); local_flush_icache_range(ebase, ebase + 0x400); - flush_tlb_handlers(); sort_extable(__start___dbe_table, __stop___dbe_table); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f0f4dc44f394..7f6cd461dac5 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2181,6 +2181,20 @@ static void __cpuinit build_r4000_tlb_modify_handler(void) dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); } +static void __cpuinit flush_tlb_handlers(void) +{ + local_flush_icache_range((unsigned long)handle_tlbl, + (unsigned long)handle_tlbl + sizeof(handle_tlbl)); + local_flush_icache_range((unsigned long)handle_tlbs, + (unsigned long)handle_tlbs + sizeof(handle_tlbs)); + local_flush_icache_range((unsigned long)handle_tlbm, + (unsigned long)handle_tlbm + sizeof(handle_tlbm)); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, + (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); +#endif +} + void __cpuinit build_tlb_refill_handler(void) { /* @@ -2213,6 +2227,7 @@ void __cpuinit build_tlb_refill_handler(void) build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); + flush_tlb_handlers(); run_once++; } #else @@ -2240,23 +2255,10 @@ void __cpuinit build_tlb_refill_handler(void) build_r4000_tlb_modify_handler(); if (!cpu_has_local_ebase) build_r4000_tlb_refill_handler(); + flush_tlb_handlers(); run_once++; } if (cpu_has_local_ebase) build_r4000_tlb_refill_handler(); } } - -void __cpuinit flush_tlb_handlers(void) -{ - local_flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + sizeof(handle_tlbl)); - local_flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + sizeof(handle_tlbs)); - local_flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + sizeof(handle_tlbm)); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, - (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); -#endif -} -- cgit v1.2.3 From 3f90b82df110ef9cb33761b56ca85ae0d0372d4a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 27 Jun 2013 02:04:25 +0200 Subject: MIPS: tlbex: Fix size of area to be flushed. Signed-off-by: Ralf Baechle --- arch/mips/mm/tlbex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 7f6cd461dac5..2f88fd3a64cf 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2191,7 +2191,7 @@ static void __cpuinit flush_tlb_handlers(void) (unsigned long)handle_tlbm + sizeof(handle_tlbm)); #ifdef CONFIG_MIPS_PGD_C0_CONTEXT local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, - (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); + (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(tlbmiss_handler_setup_pgd_array)); #endif } -- cgit v1.2.3