From c20e9e7675137d92bca071305e79fcc10364ebf5 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sun, 6 Dec 2020 17:51:28 +0100 Subject: ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controller The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. Its address follows the system controller block, which was previously incorrectly described as spanning over 0x1000 address bytes. Even though this is what the Allwinner documentation indicates, precedence from other SoCs such as the R40 suggests that this is not actually the case. This reduces the system controller address span up to the NMI controller and adds a node for the controller, with its dedicated compatible. While the interrupt number was found in Allwinner's documentation, the address for the controller is specified in any Allwinner SDK supporting sun8iw8 (V3/V3s) at: drivers/power/axp_power/axp20/axp20-board.c It was tested to work on a V3 board with an AXP209 connected to the NMI interrupt line. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201206165131.1041983-3-contact@paulk.fr --- arch/arm/boot/dts/sun8i-v3s.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/sun8i-v3s.dtsi') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index f8f19d8fa795..b7b0e685e26b 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -157,12 +157,21 @@ syscon: system-control@1c00000 { compatible = "allwinner,sun8i-v3s-system-control", "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x1000>; + reg = <0x01c00000 0xd0>; #address-cells = <1>; #size-cells = <1>; ranges; }; + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-v3s-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = ; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; -- cgit v1.2.3 From b67b3c9b66372c9d3d5ff20738dd2212ccb38f86 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 18 Dec 2020 20:50:33 +0100 Subject: ARM: dts: sun8i-v3s: Add CSI0 MCLK pin definition This adds a device-tree definition for the CSI0 MCLK pin, which can be used for feeding MIPI CSI-2 sensors. Signed-off-by: Paul Kocialkowski Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts/sun8i-v3s.dtsi') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index b7b0e685e26b..eb4cb63fef13 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -337,6 +337,12 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE20"; + function = "csi_mipi"; + }; + /omit-if-no-ref/ csi1_8bit_pins: csi1-8bit-pins { pins = "PE0", "PE2", "PE3", "PE8", "PE9", -- cgit v1.2.3