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path: root/drivers/clk
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2017-09-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds114-1037/+8040
2017-09-10Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds4-210/+21
2017-09-01clk: si5351: fix PLL resetRussell King1-7/+5
2017-09-01clk: at91: clk-generated: make gclk determine audio_pll rateQuentin Schulz1-6/+57
2017-09-01clk: at91: clk-generated: create function to find best_diffQuentin Schulz1-14/+27
2017-09-01clk: at91: add audio pll clock driversQuentin Schulz2-0/+537
2017-09-01clk: at91: clk-generated: remove useless divisor loopQuentin Schulz1-13/+12
2017-09-01clk: mb86s7x: Drop non-building driverAndreas Färber2-391/+0
2017-08-31clk: ti: check for null return in strrchr to avoid null dereferencingColin Ian King1-1/+1
2017-08-31clk: Don't write error code into divider registerAlex Frid1-2/+4
2017-08-31clk: uniphier: add video input subsystem clockKatsuhiro Suzuki1-0/+6
2017-08-31clk: uniphier: add audio system clockKatsuhiro Suzuki1-0/+12
2017-08-31clk: stm32h7: Add stm32h743 clock driverGabriel Fernandez2-0/+1411
2017-08-31clk: gate: expose clk_gate_ops::is_enabledGabriel Fernandez1-1/+2
2017-08-31clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()Gabriel Fernandez1-6/+6
2017-08-31clk: uniphier: add PXs3 clock dataMasahiro Yamada3-0/+43
2017-08-31clk: hi6220: change watchdog clock sourceLeo Yan1-3/+3
2017-08-31clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808Elaine Zhang1-2/+2
2017-08-31clk: cs2000: Add cs2000_set_saved_rateGaku Inami1-4/+10
2017-08-31clk: imx51: propagate rate across ipu_di*_selLucas Stach1-4/+4
2017-08-31Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd4-0/+1531
2017-08-30clk: sunxi: fix uninitialized accessArnd Bergmann1-0/+4
2017-08-30clk: versatile: make clk_ops constBhumika Goyal1-1/+1
2017-08-30ARC: clk: introduce HSDK pll driverEugeniy Paltsev3-0/+439
2017-08-30clk: zte: constify clk_div_tableArvind Yadav1-3/+3
2017-08-30clk: imx: constify clk_div_tableArvind Yadav5-12/+12
2017-08-30clk: uniphier: add ethernet clock control supportKunihiko Hayashi1-0/+10
2017-08-30clk: gemini: hands off PCI OE bitLinus Walleij1-7/+0
2017-08-30clk: ux500: prcc: constify clk_ops.Arvind Yadav1-3/+3
2017-08-30clk: ux500: sysctrl: constify clk_ops.Arvind Yadav1-4/+4
2017-08-30clk: ux500: prcmu: constify clk_ops.Arvind Yadav1-7/+7
2017-08-30clk: sunxi-ng: Provide a default reset hookMaxime Ripard1-0/+12
2017-08-30clk: sunxi-ng: a83t: Support new timing mode for mmc2 clockChen-Yu Tsai1-8/+2
2017-08-30clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switchingChen-Yu Tsai2-0/+110
2017-08-30clk: sunxi-ng: Add interface to query or configure MMC timing modes.Chen-Yu Tsai3-0/+75
2017-08-24clk: sunxi-ng: Add sun4i/sun7i CCU driverPriit Laes4-0/+1531
2017-08-23clk: msm8996-gcc: add missing smmu clksSrinivas Kandagatla1-0/+28
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid1-2/+4
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid1-3/+3
2017-08-23clk: tegra: Fix T210 PLLRE registrationAlex Frid1-20/+1
2017-08-23clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid1-39/+9
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid4-49/+10
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver1-2/+4
2017-08-23clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver1-1/+1
2017-08-23clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid1-1/+2
2017-08-23clk: tegra: Fix T210 effective NDIV calculationAlex Frid1-4/+5
2017-08-23clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver1-0/+2
2017-08-23clk: tegra210: remove non-existing VFIR clockPeter De Schrijver1-1/+0
2017-08-23clk: tegra: disable SSC for PLL_D2Peter De Schrijver1-1/+1
2017-08-23clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver1-1/+1