Merge tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

RISC-V SoC drivers for v6.3-mw0

It's all StarFive stuff this time:
Their new JH7110 SoC uses a SiFive core complex, and therefore a
SiFive cache controller too. That needed a compatible added to both the
binding and driver.
The JH7110 also has power domains, which are supported by a new driver
and a corresponding dt-binding.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  soc: starfive: Add StarFive JH71XX pmu driver
  dt-bindings: power: Add starfive,jh7110-pmu
  soc: sifive: ccache: Add StarFive JH7110 support
  dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC

Link: https://lore.kernel.org/r/Y9LNIm9pkr+Owv/e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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