diff options
author | Arnd Bergmann <arnd@arndb.de> | 2023-01-30 16:08:36 +0100 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2023-01-30 16:08:36 +0100 |
commit | 75dae633c9c0c8d106e97bcf17bec79f652feb2c (patch) | |
tree | df078f9e7a6e83762ace244a035cd487891691e5 /include/dt-bindings/pinctrl/rzg2l-pinctrl.h | |
parent | 0d01e09022c558c54fa2d5fb7fe7e32b7a9a8554 (diff) | |
parent | f3460326e38d6a084fb5b3348125a802567a3690 (diff) |
Merge tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V SoC drivers for v6.3-mw0
It's all StarFive stuff this time:
Their new JH7110 SoC uses a SiFive core complex, and therefore a
SiFive cache controller too. That needed a compatible added to both the
binding and driver.
The JH7110 also has power domains, which are supported by a new driver
and a corresponding dt-binding.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
soc: starfive: Add StarFive JH71XX pmu driver
dt-bindings: power: Add starfive,jh7110-pmu
soc: sifive: ccache: Add StarFive JH7110 support
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
Link: https://lore.kernel.org/r/Y9LNIm9pkr+Owv/e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/dt-bindings/pinctrl/rzg2l-pinctrl.h')
0 files changed, 0 insertions, 0 deletions