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authorLinus Torvalds <torvalds@linux-foundation.org>2020-08-06 10:54:07 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2020-08-06 10:54:07 -0700
commitb62e419707ce082845c34161fe684d0c743b7953 (patch)
tree9ecad0aef86a55ca33a0a355c627ff2b4acc4756 /arch/mips/include
parent40ddad19131999161c39564815b8df2faff0fc7c (diff)
parent6c86a3029ce3b44597526909f2e39a77a497f640 (diff)
Merge tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS upates from Thomas Bogendoerfer: - improvements for Loongson64 - extended ingenic support - removal of not maintained paravirt system type - cleanups and fixes * tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (81 commits) MIPS: SGI-IP27: always enable NUMA in Kconfig MAINTAINERS: Update KVM/MIPS maintainers MIPS: Update default config file for Loongson-3 MIPS: KVM: Add kvm guest support for Loongson-3 dt-bindings: mips: Document Loongson kvm guest board MIPS: handle Loongson-specific GSExc exception MIPS: add definitions for Loongson-specific CP0.Diag1 register MIPS: only register FTLBPar exception handler for supported models MIPS: ingenic: Hardcode mem size for qi,lb60 board MIPS: DTS: ingenic/qi,lb60: Add model and memory node MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB MIPS: head.S: Init fw_passed_dtb to builtin DTB of: address: Fix parser address/size cells initialization of_address: Guard of_bus_pci_get_flags with CONFIG_PCI MIPS: DTS: Fix number of msi vectors for Loongson64G MIPS: Loongson64: Add ISA node for LS7A PCH MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCH MIPS: Loongson64: Enlarge IO_SPACE_LIMIT MIPS: Loongson64: Process ISA Node in DeviceTree of_address: Add bus type match for pci ranges parser ...
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/Kbuild1
-rw-r--r--arch/mips/include/asm/bootinfo.h23
-rw-r--r--arch/mips/include/asm/checksum.h4
-rw-r--r--arch/mips/include/asm/cpu-features.h8
-rw-r--r--arch/mips/include/asm/cpu.h8
-rw-r--r--arch/mips/include/asm/elf.h1
-rw-r--r--arch/mips/include/asm/io.h4
-rw-r--r--arch/mips/include/asm/kvm_para.h115
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/mangle-port.h12
-rw-r--r--arch/mips/include/asm/mach-dec/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-generic/mangle-port.h12
-rw-r--r--arch/mips/include/asm/mach-generic/spaces.h4
-rw-r--r--arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-ip27/mangle-port.h6
-rw-r--r--arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-ip30/mangle-port.h6
-rw-r--r--arch/mips/include/asm/mach-ip32/mangle-port.h6
-rw-r--r--arch/mips/include/asm/mach-loongson64/boot_param.h4
-rw-r--r--arch/mips/include/asm/mach-loongson64/builtin_dtbs.h7
-rw-r--r--arch/mips/include/asm/mach-loongson64/irq.h6
-rw-r--r--arch/mips/include/asm/mach-loongson64/spaces.h3
-rw-r--r--arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-tx39xx/mangle-port.h6
-rw-r--r--arch/mips/include/asm/mach-tx49xx/mangle-port.h6
-rw-r--r--arch/mips/include/asm/mips_machine.h46
-rw-r--r--arch/mips/include/asm/mipsregs.h39
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pip.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pko.h7
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow.h8
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/war.h2
-rw-r--r--arch/mips/include/uapi/asm/Kbuild2
-rw-r--r--arch/mips/include/uapi/asm/kvm_para.h5
34 files changed, 122 insertions, 243 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 8643d313890e..198b3bafdac9 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -5,6 +5,7 @@ generated-y += syscall_table_64_n32.h
generated-y += syscall_table_64_n64.h
generated-y += syscall_table_64_o32.h
generic-y += export.h
+generic-y += kvm_para.h
generic-y += local64.h
generic-y += mcs_spinlock.h
generic-y += parport.h
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index c3bd9b2d66e4..147c9327ce04 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -65,12 +65,23 @@ enum loongson2ef_machine_type {
/*
* Valid machtype for group INGENIC
*/
-#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
-#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
-#define MACH_INGENIC_JZ4770 2 /* JZ4770 SOC */
-#define MACH_INGENIC_JZ4780 3 /* JZ4780 SOC */
-#define MACH_INGENIC_X1000 4 /* X1000 SOC */
-#define MACH_INGENIC_X1830 5 /* X1830 SOC */
+enum ingenic_machine_type {
+ MACH_INGENIC_UNKNOWN,
+ MACH_INGENIC_JZ4720,
+ MACH_INGENIC_JZ4725,
+ MACH_INGENIC_JZ4725B,
+ MACH_INGENIC_JZ4730,
+ MACH_INGENIC_JZ4740,
+ MACH_INGENIC_JZ4750,
+ MACH_INGENIC_JZ4755,
+ MACH_INGENIC_JZ4760,
+ MACH_INGENIC_JZ4770,
+ MACH_INGENIC_JZ4775,
+ MACH_INGENIC_JZ4780,
+ MACH_INGENIC_X1000,
+ MACH_INGENIC_X1830,
+ MACH_INGENIC_X2000,
+};
extern char *system_type;
const char *get_system_type(void);
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index dcebaaf8c862..181f7d14efb9 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -113,9 +113,9 @@ static inline __sum16 csum_fold(__wsum csum)
u32 sum = (__force u32)csum;
sum += (sum << 16);
- csum = (sum < csum);
+ csum = (__force __wsum)(sum < (__force u32)csum);
sum >>= 16;
- sum += csum;
+ sum += (__force u32)csum;
return (__force __sum16)~sum;
}
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 724dfddcab92..78cf7e300f12 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -568,6 +568,14 @@
# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY)
#endif
+#ifndef cpu_has_ftlbparex
+# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX)
+#endif
+
+#ifndef cpu_has_gsexcex
+# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX)
+#endif
+
#ifdef CONFIG_SMP
/*
* Some systems share FTLB RAMs between threads within a core (siblings in
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 104a509312b3..388a82f28a87 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -46,6 +46,7 @@
#define PRID_COMP_NETLOGIC 0x0c0000
#define PRID_COMP_CAVIUM 0x0d0000
#define PRID_COMP_LOONGSON 0x140000
+#define PRID_COMP_INGENIC_13 0x130000 /* X2000 */
#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750, X1830 */
#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
@@ -185,8 +186,9 @@
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
*/
-#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst with MXU SIMD ISA */
-#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst with MXU2 SIMD ISA */
+#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
+#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
+#define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
/*
* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
@@ -425,6 +427,8 @@ enum cpu_type_enum {
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
+#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
+#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
/*
* CPU ASE encodings
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 5aa29ced6970..71c7622025d1 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -410,6 +410,7 @@ do { \
clear_thread_flag(TIF_32BIT_FPREGS); \
clear_thread_flag(TIF_HYBRID_FPREGS); \
clear_thread_flag(TIF_32BIT_ADDR); \
+ current->personality &= ~READ_IMPLIES_EXEC; \
\
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
__SET_PERSONALITY32(ex, state); \
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 346fffd9e972..78537aa23500 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -51,15 +51,13 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
-#define IO_SPACE_LIMIT 0xffff
-
/*
* On MIPS I/O ports are memory mapped, so we access them using normal
* load/store instructions. mips_io_port_base is the virtual address to
* which all ports are being mapped. For sake of efficiency some code
* assumes that this is an address that can be loaded with a single lui
* instruction, so the lower 16 bits must be zero. Should be true on
- * on any sane architecture; generic code does not use this assumption.
+ * any sane architecture; generic code does not use this assumption.
*/
extern unsigned long mips_io_port_base;
diff --git a/arch/mips/include/asm/kvm_para.h b/arch/mips/include/asm/kvm_para.h
deleted file mode 100644
index b57e978b0946..000000000000
--- a/arch/mips/include/asm/kvm_para.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_MIPS_KVM_PARA_H
-#define _ASM_MIPS_KVM_PARA_H
-
-#include <uapi/asm/kvm_para.h>
-
-#define KVM_HYPERCALL ".word 0x42000028"
-
-/*
- * Hypercalls for KVM.
- *
- * Hypercall number is passed in v0.
- * Return value will be placed in v0.
- * Up to 3 arguments are passed in a0, a1, and a2.
- */
-static inline unsigned long kvm_hypercall0(unsigned long num)
-{
- register unsigned long n asm("v0");
- register unsigned long r asm("v0");
-
- n = num;
- __asm__ __volatile__(
- KVM_HYPERCALL
- : "=r" (r) : "r" (n) : "memory"
- );
-
- return r;
-}
-
-static inline unsigned long kvm_hypercall1(unsigned long num,
- unsigned long arg0)
-{
- register unsigned long n asm("v0");
- register unsigned long r asm("v0");
- register unsigned long a0 asm("a0");
-
- n = num;
- a0 = arg0;
- __asm__ __volatile__(
- KVM_HYPERCALL
- : "=r" (r) : "r" (n), "r" (a0) : "memory"
- );
-
- return r;
-}
-
-static inline unsigned long kvm_hypercall2(unsigned long num,
- unsigned long arg0, unsigned long arg1)
-{
- register unsigned long n asm("v0");
- register unsigned long r asm("v0");
- register unsigned long a0 asm("a0");
- register unsigned long a1 asm("a1");
-
- n = num;
- a0 = arg0;
- a1 = arg1;
- __asm__ __volatile__(
- KVM_HYPERCALL
- : "=r" (r) : "r" (n), "r" (a0), "r" (a1) : "memory"
- );
-
- return r;
-}
-
-static inline unsigned long kvm_hypercall3(unsigned long num,
- unsigned long arg0, unsigned long arg1, unsigned long arg2)
-{
- register unsigned long n asm("v0");
- register unsigned long r asm("v0");
- register unsigned long a0 asm("a0");
- register unsigned long a1 asm("a1");
- register unsigned long a2 asm("a2");
-
- n = num;
- a0 = arg0;
- a1 = arg1;
- a2 = arg2;
- __asm__ __volatile__(
- KVM_HYPERCALL
- : "=r" (r) : "r" (n), "r" (a0), "r" (a1), "r" (a2) : "memory"
- );
-
- return r;
-}
-
-static inline bool kvm_check_and_clear_guest_paused(void)
-{
- return false;
-}
-
-static inline unsigned int kvm_arch_para_features(void)
-{
- return 0;
-}
-
-static inline unsigned int kvm_arch_para_hints(void)
-{
- return 0;
-}
-
-#ifdef CONFIG_MIPS_PARAVIRT
-static inline bool kvm_para_available(void)
-{
- return true;
-}
-#else
-static inline bool kvm_para_available(void)
-{
- return false;
-}
-#endif
-
-
-#endif /* _ASM_MIPS_KVM_PARA_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
index 8ff2cbdf2c3e..239fcc874b99 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -48,11 +48,17 @@ static inline bool __should_swizzle_addr(u64 p)
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
-# define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x)
+# define ioswabw(a, x) (__should_swizzle_bits(a) ? \
+ le16_to_cpu((__force __le16)(x)) : \
+ (x))
# define __mem_ioswabw(a, x) (x)
-# define ioswabl(a, x) (__should_swizzle_bits(a) ? le32_to_cpu(x) : x)
+# define ioswabl(a, x) (__should_swizzle_bits(a) ? \
+ le32_to_cpu((__force __le32)(x)) : \
+ (x))
# define __mem_ioswabl(a, x) (x)
-# define ioswabq(a, x) (__should_swizzle_bits(a) ? le64_to_cpu(x) : x)
+# define ioswabq(a, x) (__should_swizzle_bits(a) ? \
+ le64_to_cpu((__force __le64)(x)) : \
+ (x))
# define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index 00beb69bfab9..1896e88f6000 100644
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -43,7 +43,6 @@
#define cpu_has_dsp2 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
-#define cpu_hwrena_impl_bits 0
#define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0
#define cpu_has_fre 0
diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
index f49dc990214b..77c65c294db6 100644
--- a/arch/mips/include/asm/mach-generic/mangle-port.h
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
@@ -29,11 +29,11 @@
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
-# define ioswabw(a, x) le16_to_cpu(x)
+# define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
# define __mem_ioswabw(a, x) (x)
-# define ioswabl(a, x) le32_to_cpu(x)
+# define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
# define __mem_ioswabl(a, x) (x)
-# define ioswabq(a, x) le64_to_cpu(x)
+# define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
# define __mem_ioswabq(a, x) (x)
#else
@@ -41,11 +41,11 @@
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x)
-# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
# define ioswabl(a, x) (x)
-# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
# define ioswabq(a, x) (x)
-# define __mem_ioswabq(a, x) cpu_to_le32(x)
+# define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index ee5ebe98f6cf..c3ac06a6acd2 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -14,6 +14,10 @@
#include <asm/mipsregs.h>
+#ifndef IO_SPACE_LIMIT
+#define IO_SPACE_LIMIT 0xffff
+#endif
+
/*
* This gives the physical RAM offset.
*/
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 136d6d464e32..58f829c9b6c7 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -25,8 +25,6 @@
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
-#define cpu_has_6k_cache 0
-#define cpu_has_8k_cache 0
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 1
#define cpu_has_nofpuex 0
@@ -67,7 +65,6 @@
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_inclusive_pcaches 1
-#define cpu_hwrena_impl_bits 0
#define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0
#define cpu_has_fre 0
diff --git a/arch/mips/include/asm/mach-ip27/mangle-port.h b/arch/mips/include/asm/mach-ip27/mangle-port.h
index 27c56efa519f..f71c38bbfc2f 100644
--- a/arch/mips/include/asm/mach-ip27/mangle-port.h
+++ b/arch/mips/include/asm/mach-ip27/mangle-port.h
@@ -16,10 +16,10 @@
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x)
-# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
# define ioswabl(a, x) (x)
-# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
# define ioswabq(a, x) (x)
-# define __mem_ioswabq(a, x) cpu_to_le64(x)
+# define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
index cfa02f3d25df..49a93e82c252 100644
--- a/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
@@ -28,8 +28,6 @@
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
-#define cpu_has_6k_cache 0
-#define cpu_has_8k_cache 0
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 1
#define cpu_has_nofpuex 0
@@ -69,7 +67,6 @@
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_inclusive_pcaches 1
-#define cpu_hwrena_impl_bits 0
#define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0
#define cpu_has_fre 0
diff --git a/arch/mips/include/asm/mach-ip30/mangle-port.h b/arch/mips/include/asm/mach-ip30/mangle-port.h
index f3e1262a2d5e..439c6a601830 100644
--- a/arch/mips/include/asm/mach-ip30/mangle-port.h
+++ b/arch/mips/include/asm/mach-ip30/mangle-port.h
@@ -13,10 +13,10 @@
#define ioswabb(a, x) (x)
#define __mem_ioswabb(a, x) (x)
#define ioswabw(a, x) (x)
-#define __mem_ioswabw(a, x) cpu_to_le16(x)
+#define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
#define ioswabl(a, x) (x)
-#define __mem_ioswabl(a, x) cpu_to_le32(x)
+#define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
#define ioswabq(a, x) (x)
-#define __mem_ioswabq(a, x) cpu_to_le64(x)
+#define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif /* __ASM_MACH_IP30_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip32/mangle-port.h b/arch/mips/include/asm/mach-ip32/mangle-port.h
index f1d0f1756a9f..4bc3d20e8293 100644
--- a/arch/mips/include/asm/mach-ip32/mangle-port.h
+++ b/arch/mips/include/asm/mach-ip32/mangle-port.h
@@ -17,10 +17,10 @@
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x)
-# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
# define ioswabl(a, x) (x)
-# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
# define ioswabq(a, x) (x)
-# define __mem_ioswabq(a, x) cpu_to_le32(x)
+# define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index b35be709f9da..afc92b7a61c6 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -194,7 +194,8 @@ struct boot_params {
enum loongson_bridge_type {
LS7A = 1,
- RS780E = 2
+ RS780E = 2,
+ VIRTUAL = 3
};
struct loongson_system_configuration {
@@ -230,5 +231,6 @@ extern struct loongson_system_configuration loongson_sysconf;
extern u32 node_id_offset;
extern void ls7a_early_config(void);
extern void rs780e_early_config(void);
+extern void virtual_early_config(void);
#endif
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
index 853c6d80887b..839410cda621 100644
--- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -8,6 +8,9 @@
#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
-extern u32 __dtb_loongson3_4core_rs780e_begin[];
-extern u32 __dtb_loongson3_8core_rs780e_begin[];
+extern u32 __dtb_loongson64c_4core_ls7a_begin[];
+extern u32 __dtb_loongson64c_4core_rs780e_begin[];
+extern u32 __dtb_loongson64c_8core_rs780e_begin[];
+extern u32 __dtb_loongson64g_4core_ls7a_begin[];
+extern u32 __dtb_loongson64v_4core_virtio_begin[];
#endif
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index d41dc4a76e6d..f5e362f79701 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -5,7 +5,11 @@
#include <boot_param.h>
/* cpu core interrupt numbers */
-#define MIPS_CPU_IRQ_BASE 56
+#define NR_IRQS_LEGACY 16
+#define NR_MIPS_CPU_IRQS 8
+#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
+
+#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
#include <asm/mach-generic/irq.h>
diff --git a/arch/mips/include/asm/mach-loongson64/spaces.h b/arch/mips/include/asm/mach-loongson64/spaces.h
index 3de0ac9d8829..ce04e998a37b 100644
--- a/arch/mips/include/asm/mach-loongson64/spaces.h
+++ b/arch/mips/include/asm/mach-loongson64/spaces.h
@@ -11,8 +11,7 @@
#define PCI_IOSIZE SZ_16M
#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
-/* Reserved at the start of PCI_IOBASE for legacy drivers */
-#define MMIO_LOWER_RESERVED 0x10000
+#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
#include <asm/mach-generic/spaces.h>
#endif
diff --git a/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h
index 725e1ed83f6a..23ecf816daa7 100644
--- a/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h
@@ -29,7 +29,6 @@
#define cpu_has_octeon_cache 1
#define cpu_has_4k_cache 0
#else
-#define cpu_has_octeon_cache 0
#define cpu_has_4k_cache 1
#endif
diff --git a/arch/mips/include/asm/mach-tx39xx/mangle-port.h b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
index ab7a70bd895e..95be459950f7 100644
--- a/arch/mips/include/asm/mach-tx39xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
@@ -14,11 +14,11 @@ extern unsigned long (*__swizzle_addr_b)(unsigned long port);
#define ioswabb(a, x) (x)
#define __mem_ioswabb(a, x) (x)
-#define ioswabw(a, x) le16_to_cpu(x)
+#define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
#define __mem_ioswabw(a, x) (x)
-#define ioswabl(a, x) le32_to_cpu(x)
+#define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
#define __mem_ioswabl(a, x) (x)
-#define ioswabq(a, x) le64_to_cpu(x)
+#define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
#define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
index e061ef38fb5f..98c7abf4484a 100644
--- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -16,12 +16,12 @@
extern u16 (*ioswabw)(volatile u16 *a, u16 x);
extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
#else
-#define ioswabw(a, x) le16_to_cpu(x)
+#define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
#define __mem_ioswabw(a, x) (x)
#endif
-#define ioswabl(a, x) le32_to_cpu(x)
+#define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
#define __mem_ioswabl(a, x) (x)
-#define ioswabq(a, x) le64_to_cpu(x)
+#define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
#define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h
deleted file mode 100644
index 4efecb70c24e..000000000000
--- a/arch/mips/include/asm/mips_machine.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#ifndef __ASM_MIPS_MACHINE_H
-#define __ASM_MIPS_MACHINE_H
-
-#include <linux/init.h>
-#include <linux/stddef.h>
-
-#include <asm/bootinfo.h>
-
-struct mips_machine {
- unsigned long mach_type;
- const char *mach_id;
- const char *mach_name;
- void (*mach_setup)(void);
-};
-
-#define MIPS_MACHINE(_type, _id, _name, _setup) \
-static const char machine_name_##_type[] __initconst \
- __aligned(1) = _name; \
-static const char machine_id_##_type[] __initconst \
- __aligned(1) = _id; \
-static struct mips_machine machine_##_type \
- __used __section(.mips.machines.init) = \
-{ \
- .mach_type = _type, \
- .mach_id = machine_id_##_type, \
- .mach_name = machine_name_##_type, \
- .mach_setup = _setup, \
-};
-
-extern long __mips_machines_start;
-extern long __mips_machines_end;
-
-#ifdef CONFIG_MIPS_MACHINE
-int mips_machtype_setup(char *id) __init;
-void mips_machine_setup(void) __init;
-#else
-static inline int mips_machtype_setup(char *id) { return 1; }
-static inline void mips_machine_setup(void) { }
-#endif /* CONFIG_MIPS_MACHINE */
-
-#endif /* __ASM_MIPS_MACHINE_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 20d6d40c59a4..4ddc12e4444a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -86,6 +86,7 @@
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
+#define CP0_DIAGNOSTIC1 $22, 1
#define CP0_DEBUG $23
#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
@@ -473,6 +474,9 @@
/* Implementation specific trap codes used by MIPS cores */
#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
+/* Implementation specific trap codes used by Loongson cores */
+#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
+
/*
* Bits in the coprocessor 0 config register.
*/
@@ -689,35 +693,35 @@
/* Config6 feature bits for proAptiv/P5600 */
/* Jump register cache prediction disable */
-#define MIPS_CONF6_MTI_JRCD (_ULCAST_(1) << 0)
+#define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
/* MIPSr6 extensions enable */
-#define MIPS_CONF6_MTI_R6 (_ULCAST_(1) << 2)
+#define MTI_CONF6_R6 (_ULCAST_(1) << 2)
/* IFU Performance Control */
-#define MIPS_CONF6_MTI_IFUPERFCTL (_ULCAST_(3) << 10)
-#define MIPS_CONF6_MTI_SYND (_ULCAST_(1) << 13)
+#define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
+#define MTI_CONF6_SYND (_ULCAST_(1) << 13)
/* Sleep state performance counter disable */
-#define MIPS_CONF6_MTI_SPCD (_ULCAST_(1) << 14)
+#define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
/* proAptiv FTLB on/off bit */
-#define MIPS_CONF6_MTI_FTLBEN (_ULCAST_(1) << 15)
+#define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
/* Disable load/store bonding */
-#define MIPS_CONF6_MTI_DLSB (_ULCAST_(1) << 21)
+#define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
/* FTLB probability bits */
-#define MIPS_CONF6_MTI_FTLBP_SHIFT (16)
+#define MTI_CONF6_FTLBP_SHIFT (16)
/* Config6 feature bits for Loongson-3 */
/* Loongson-3 internal timer bit */
-#define MIPS_CONF6_LOONGSON_INTIMER (_ULCAST_(1) << 6)
+#define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
/* Loongson-3 external timer bit */
-#define MIPS_CONF6_LOONGSON_EXTIMER (_ULCAST_(1) << 7)
+#define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
/* Loongson-3 SFB on/off bit, STFill in manual */
-#define MIPS_CONF6_LOONGSON_SFBEN (_ULCAST_(1) << 8)
+#define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
/* Loongson-3's LL on exclusive cacheline */
-#define MIPS_CONF6_LOONGSON_LLEXC (_ULCAST_(1) << 16)
+#define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
/* Loongson-3's SC has a random delay */
-#define MIPS_CONF6_LOONGSON_SCRAND (_ULCAST_(1) << 17)
+#define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
-#define MIPS_CONF6_LOONGSON_FTLBDIS (_ULCAST_(1) << 22)
+#define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
@@ -1051,6 +1055,13 @@
/* Flush FTLB */
#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
+/*
+ * Diag1 (GSCause in Loongson-speak) fields
+ */
+/* Loongson-specific exception code (GSExcCode) */
+#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
+#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
+
/* CvmCtl register field definitions */
#define CVMCTL_IPPCI_SHIFT 7
#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 02c4479a90c8..4459a32008b7 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -327,7 +327,7 @@ void cvmx_l2c_flush(void);
/**
*
- * Returns Returns the size of the L2 cache in bytes,
+ * Returns the size of the L2 cache in bytes,
* -1 on error (unrecognized model)
*/
int cvmx_l2c_get_cache_size_bytes(void);
diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
index c210154ad941..01ca7267a2ba 100644
--- a/arch/mips/include/asm/octeon/cvmx-pip.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
@@ -503,7 +503,7 @@ static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
* offsetof() to determine the offsets into packet headers.
* For example, offsetof(ethhdr, protocol) returns the offset
* of the ethernet protocol field. The bitmask selects which
- * bytes to include the the tag, with bit offset X selecting
+ * bytes to include the tag, with bit offset X selecting
* byte at offset X from the beginning of the packet data.
* @len: Number of bytes to include. Usually this is the sizeof()
* the field.
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index 5b0b982a36f7..03fb64b13fba 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -40,8 +40,7 @@
* generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
* with hand tuned fast path code.
*
- * Some of other SDK differences visible to the command command
- * queuing:
+ * Some of other SDK differences visible to the command queuing:
* - PKO indexes are no longer stored in the FAU. A large
* percentage of the FAU register block used to be tied up
* maintaining PKO queue pointers. These are now stored in a
@@ -413,7 +412,7 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
* CVMX_PKO_LOCK_CMD_QUEUE
*
- * Returns returns CVMX_PKO_SUCCESS on success, or error code on
+ * Returns: CVMX_PKO_SUCCESS on success, or error code on
* failure of output
*/
static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
@@ -456,7 +455,7 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
* CVMX_PKO_LOCK_CMD_QUEUE
*
- * Returns returns CVMX_PKO_SUCCESS on success, or error code on
+ * Returns: CVMX_PKO_SUCCESS on success, or error code on
* failure of output
*/
static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index ba366f4f3c3d..a3b23811e0c3 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -1345,7 +1345,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
* @wait: When set, call stalls until work becomes avaiable, or times out.
* If not set, returns immediately.
*
- * Returns Returns the WQE pointer from POW. Returns NULL if no work
+ * Returns: the WQE pointer from POW. Returns NULL if no work
* was available.
*/
static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
@@ -1379,7 +1379,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_
* @wait: When set, call stalls until work becomes avaiable, or times out.
* If not set, returns immediately.
*
- * Returns Returns the WQE pointer from POW. Returns NULL if no work
+ * Returns: the WQE pointer from POW. Returns NULL if no work
* was available.
*/
static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
@@ -1398,7 +1398,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
* This function waits for any previous tag switch to complete before
* requesting the null_rd.
*
- * Returns Returns the POW state of type cvmx_pow_tag_type_t.
+ * Returns: the POW state of type cvmx_pow_tag_type_t.
*/
static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
{
@@ -1482,7 +1482,7 @@ static inline void cvmx_pow_work_request_async(int scr_addr,
* @scr_addr: Scratch memory address to get result from Byte address,
* must be 8 byte aligned.
*
- * Returns Returns the WQE from the scratch register, or NULL if no
+ * Returns: the WQE from the scratch register, or NULL if no
* work was available.
*/
static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index a2e2876357ce..08d48f37c046 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -198,7 +198,7 @@ union octeon_cvmemctl {
* CvmMemCtl[DIDTTO] */
__BITFIELD_FIELD(uint64_t didtto2:1,
/* R/W If set, marked write-buffer entries time out
- * the same as as other entries; if clear, marked
+ * the same as other entries; if clear, marked
* write-buffer entries use the maximum timeout. */
__BITFIELD_FIELD(uint64_t dismarkwblongto:1,
/* R/W If set, a merged store does not clear the
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 1eedd596a064..e43f800e662d 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -121,7 +121,7 @@
* operate correctly if the internal data cache refill buffer is empty. These
* CACHE instructions should be separated from any potential data cache miss
* by a load instruction to an uncached address to empty the response buffer."
- * (Revision 2.0 device errata from IDT available on http://www.idt.com/
+ * (Revision 2.0 device errata from IDT available on https://www.idt.com/
* in .pdf format.)
*/
#ifndef R4600_V2_HIT_CACHEOP_WAR
diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild
index c21c87ecdcd0..6db08385d3d8 100644
--- a/arch/mips/include/uapi/asm/Kbuild
+++ b/arch/mips/include/uapi/asm/Kbuild
@@ -5,3 +5,5 @@ generated-y += unistd_o32.h
generated-y += unistd_nr_n32.h
generated-y += unistd_nr_n64.h
generated-y += unistd_nr_o32.h
+
+generic-y += kvm_para.h
diff --git a/arch/mips/include/uapi/asm/kvm_para.h b/arch/mips/include/uapi/asm/kvm_para.h
deleted file mode 100644
index 7e16d7c42e65..000000000000
--- a/arch/mips/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef _UAPI_ASM_MIPS_KVM_PARA_H
-#define _UAPI_ASM_MIPS_KVM_PARA_H
-
-
-#endif /* _UAPI_ASM_MIPS_KVM_PARA_H */