2024y-10m-18d-23h-21m-44s UTC: drm-tip rerere cache update

git version 2.45.2

8 files changed, 0 insertions, 3708 deletions

diff --git a/rr-cache/0cfe2eed46f73c4fbe7135d2e861faa120e53c0e/postimage b/rr-cache/0cfe2eed46f73c4fbe7135d2e861faa120e53c0e/postimage
deleted file mode 100644
index 540d38603f32..000000000000
--- a/rr-cache/0cfe2eed46f73c4fbe7135d2e861faa120e53c0e/postimage
+++ /dev/null
@@ -1,33 +0,0 @@
-22012773006	GRAPHICS_VERSION_RANGE(1200, 1250)
-14014475959	GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
-		PLATFORM(DG2)
-22011391025	PLATFORM(DG2)
-22012727170	SUBPLATFORM(DG2, G11)
-22012727685	SUBPLATFORM(DG2, G11)
-18020744125	PLATFORM(PVC)
-1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
-1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)
-14016763929	SUBPLATFORM(DG2, G10)
-		SUBPLATFORM(DG2, G12)
-16017236439	PLATFORM(PVC)
-22010954014	PLATFORM(DG2)
-14019821291	MEDIA_VERSION_RANGE(1300, 2000)
-14015076503	MEDIA_VERSION(1300)
-16020292621	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
-14018913170	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
-		MEDIA_VERSION(2000), GRAPHICS_STEP(A0, A1)
-		GRAPHICS_VERSION_RANGE(1270, 1274)
-		MEDIA_VERSION(1300)
-		PLATFORM(DG2)
-14018094691	GRAPHICS_VERSION(2004)
-14019882105	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
-18024947630	GRAPHICS_VERSION(2001)
-		GRAPHICS_VERSION(2004)
-		MEDIA_VERSION(2000)
-16022287689	GRAPHICS_VERSION(2001)
-		GRAPHICS_VERSION(2004)
-13011645652	GRAPHICS_VERSION(2004)
-22019338487	MEDIA_VERSION(2000)
-		GRAPHICS_VERSION(2001)
-22019338487_display	PLATFORM(LUNARLAKE)
-16023588340	GRAPHICS_VERSION(2001)
diff --git a/rr-cache/0cfe2eed46f73c4fbe7135d2e861faa120e53c0e/preimage b/rr-cache/0cfe2eed46f73c4fbe7135d2e861faa120e53c0e/preimage
deleted file mode 100644
index 2220ba23748c..000000000000
--- a/rr-cache/0cfe2eed46f73c4fbe7135d2e861faa120e53c0e/preimage
+++ /dev/null
@@ -1,36 +0,0 @@
-22012773006	GRAPHICS_VERSION_RANGE(1200, 1250)
-14014475959	GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
-		PLATFORM(DG2)
-22011391025	PLATFORM(DG2)
-22012727170	SUBPLATFORM(DG2, G11)
-22012727685	SUBPLATFORM(DG2, G11)
-18020744125	PLATFORM(PVC)
-1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
-1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)
-14016763929	SUBPLATFORM(DG2, G10)
-		SUBPLATFORM(DG2, G12)
-16017236439	PLATFORM(PVC)
-22010954014	PLATFORM(DG2)
-14019821291	MEDIA_VERSION_RANGE(1300, 2000)
-14015076503	MEDIA_VERSION(1300)
-16020292621	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
-14018913170	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
-		MEDIA_VERSION(2000), GRAPHICS_STEP(A0, A1)
-		GRAPHICS_VERSION_RANGE(1270, 1274)
-		MEDIA_VERSION(1300)
-		PLATFORM(DG2)
-14018094691	GRAPHICS_VERSION(2004)
-14019882105	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
-18024947630	GRAPHICS_VERSION(2001)
-		GRAPHICS_VERSION(2004)
-		MEDIA_VERSION(2000)
-16022287689	GRAPHICS_VERSION(2001)
-		GRAPHICS_VERSION(2004)
-13011645652	GRAPHICS_VERSION(2004)
-22019338487	MEDIA_VERSION(2000)
-		GRAPHICS_VERSION(2001)
-<<<<<<<
-=======
-22019338487_display	PLATFORM(LUNARLAKE)
->>>>>>>
-16023588340	GRAPHICS_VERSION(2001)
diff --git a/rr-cache/1ab34439cb1e3b81c7513b62c0d161208b67130e/preimage.1 b/rr-cache/1ab34439cb1e3b81c7513b62c0d161208b67130e/preimage.1
deleted file mode 100644
index a822b974678a..000000000000
--- a/rr-cache/1ab34439cb1e3b81c7513b62c0d161208b67130e/preimage.1
+++ /dev/null
@@ -1,601 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef _XE_GT_REGS_H_
-#define _XE_GT_REGS_H_
-
-#include "regs/xe_reg_defs.h"
-
-/*
- * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
- * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically
- * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
- */
-#define MEDIA_GT_GSI_OFFSET				0x380000
-#define MEDIA_GT_GSI_LENGTH				0x40000
-
-/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
-#define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)
-#define   MTL_CAGF_MASK					REG_GENMASK(8, 0)
-#define   MTL_CC_MASK					REG_GENMASK(12, 9)
-
-/* RPM unit config (Gen8+) */
-#define RPM_CONFIG0					XE_REG(0xd00)
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3
-#define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
-
-#define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)
-#define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)
-#define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)
-
-#define GMD_ID					XE_REG(0xd8c)
-#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
-#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
-#define   GMD_ID_REVID				REG_GENMASK(5, 0)
-
-#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
-#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)
-
-#define MCFG_MCR_SELECTOR			XE_REG(0xfd0)
-#define MTL_MCR_SELECTOR			XE_REG(0xfd4)
-#define SF_MCR_SELECTOR				XE_REG(0xfd8)
-#define MCR_SELECTOR				XE_REG(0xfdc)
-#define GAM_MCR_SELECTOR			XE_REG(0xfe0)
-#define   MCR_MULTICAST				REG_BIT(31)
-#define   MCR_SLICE_MASK			REG_GENMASK(30, 27)
-#define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
-#define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
-#define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
-#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
-#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
-
-#define PS_INVOCATION_COUNT			XE_REG(0x2348)
-
-#define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)
-#define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)
-#define   LE_SSE_MASK				REG_GENMASK(18, 17)
-#define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
-#define   LE_COS_MASK				REG_GENMASK(16, 15)
-#define   LE_COS(value)				REG_FIELD_PREP(LE_COS_MASK)
-#define   LE_SCF_MASK				REG_BIT(14)
-#define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
-#define   LE_PFM_MASK				REG_GENMASK(13, 11)
-#define   LE_PFM(value)				REG_FIELD_PREP(LE_PFM_MASK, value)
-#define   LE_SCC_MASK				REG_GENMASK(10, 8)
-#define   LE_SCC(value)				REG_FIELD_PREP(LE_SCC_MASK, value)
-#define   LE_RSC_MASK				REG_BIT(7)
-#define   LE_RSC(value)				REG_FIELD_PREP(LE_RSC_MASK, value)
-#define   LE_AOM_MASK				REG_BIT(6)
-#define   LE_AOM(value)				REG_FIELD_PREP(LE_AOM_MASK, value)
-#define   LE_LRUM_MASK				REG_GENMASK(5, 4)
-#define   LE_LRUM(value)			REG_FIELD_PREP(LE_LRUM_MASK, value)
-#define   LE_TGT_CACHE_MASK			REG_GENMASK(3, 2)
-#define   LE_TGT_CACHE(value)			REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
-#define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
-#define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
-
-<<<<<<<
-#define STATELESS_COMPRESSION_CTRL		XE_REG(0x4148)
-#define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)
-
-#define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)
-=======
-#define XE2_GAMREQSTRM_CTRL			XE_REG(0x4194)
->>>>>>>
-#define   CG_DIS_CNTLBUS			REG_BIT(6)
-
-#define CCS_AUX_INV				XE_REG(0x4208)
-
-#define VD0_AUX_INV				XE_REG(0x4218)
-#define VE0_AUX_INV				XE_REG(0x4238)
-
-#define VE1_AUX_INV				XE_REG(0x42b8)
-#define   AUX_INV				REG_BIT(0)
-
-#define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)
-#define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
-#define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
-
-#define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
-#define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
-
-#define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
-#define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
-
-#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
-#define   TBIMR_FAST_CLIP			REG_BIT(5)
-
-#define FF_MODE					XE_REG_MCR(0x6210)
-#define   DIS_TE_AUTOSTRIP			REG_BIT(31)
-#define   DIS_MESH_PARTIAL_AUTOSTRIP		REG_BIT(16)
-#define   DIS_MESH_AUTOSTRIP			REG_BIT(15)
-
-#define VFLSKPD					XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
-#define   DIS_PARTIAL_AUTOSTRIP			REG_BIT(9)
-#define   DIS_AUTOSTRIP				REG_BIT(6)
-#define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
-#define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
-
-#define FF_MODE2				XE_REG(0x6604)
-#define XEHP_FF_MODE2				XE_REG_MCR(0x6604)
-#define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)
-#define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
-#define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)
-#define   FF_MODE2_TDS_TIMER_128		REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-
-#define XEHPG_INSTDONE_GEOM_SVGUNIT		XE_REG_MCR(0x666c)
-
-#define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)
-#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)
-
-#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)
-#define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)
-
-#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)
-#define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
-#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE		REG_BIT(13)
-
-#define XEHP_PSS_MODE2				XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
-#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)
-
-#define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
-#define   FLSH_IGNORES_PSD			REG_BIT(10)
-#define   FD_END_COLLECT			REG_BIT(5)
-
-#define SC_INSTDONE				XE_REG(0x7100)
-#define SC_INSTDONE_EXTRA			XE_REG(0x7104)
-#define SC_INSTDONE_EXTRA2			XE_REG(0x7108)
-
-#define XEHPG_SC_INSTDONE			XE_REG_MCR(0x7100)
-#define XEHPG_SC_INSTDONE_EXTRA			XE_REG_MCR(0x7104)
-#define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)
-
-#define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)
-#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
-
-#define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)
-#define XEHP_COMMON_SLICE_CHICKEN3			XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)
-#define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
-#define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)
-#define   BLEND_EMB_FIX_DISABLE_IN_RCC			REG_BIT(11)
-#define   DISABLE_CPS_AWARE_COLOR_PIPE			REG_BIT(9)
-
-#define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
-#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)
-
-#define VF_PREEMPTION				XE_REG(0x83a4, XE_REG_OPTION_MASKED)
-#define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)
-
-#define VF_SCRATCHPAD				XE_REG(0x83a8, XE_REG_OPTION_MASKED)
-#define   XE2_VFG_TED_CREDIT_INTERFACE_DISABLE	REG_BIT(13)
-
-#define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4, XE_REG_OPTION_MASKED)
-#define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)
-
-#define SQCNT1					XE_REG_MCR(0x8718)
-#define XELPMP_SQCNT1				XE_REG(0x8718)
-#define   SQCNT1_PMON_ENABLE			REG_BIT(30)
-#define   SQCNT1_OABPC				REG_BIT(29)
-#define   ENFORCE_RAR				REG_BIT(23)
-
-#define XEHP_SQCM				XE_REG_MCR(0x8724)
-#define   EN_32B_ACCESS				REG_BIT(30)
-
-#define XE2_FLAT_CCS_BASE_RANGE_LOWER		XE_REG_MCR(0x8800)
-#define   XE2_FLAT_CCS_ENABLE			REG_BIT(0)
-#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK	REG_GENMASK(31, 6)
-
-#define XE2_FLAT_CCS_BASE_RANGE_UPPER		XE_REG_MCR(0x8804)
-#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK	REG_GENMASK(7, 0)
-
-#define GSCPSMI_BASE				XE_REG(0x880c)
-
-#define CCCHKNREG1				XE_REG_MCR(0x8828)
-#define   ENCOMPPERFFIX				REG_BIT(18)
-
-/* Fuse readout registers for GT */
-#define XEHP_FUSE4				XE_REG(0x9114)
-#define   CFEG_WMTP_DISABLE			REG_BIT(20)
-#define   CCS_EN_MASK				REG_GENMASK(19, 16)
-#define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
-
-#define	MIRROR_FUSE3				XE_REG(0x9118)
-#define   XE2_NODE_ENABLE_MASK			REG_GENMASK(31, 16)
-#define   L3BANK_PAIR_COUNT			4
-#define   XEHPC_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
-#define   XE2_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
-#define   L3BANK_MASK				REG_GENMASK(3, 0)
-#define   XELP_GT_L3_MODE_MASK			REG_GENMASK(7, 0)
-/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
-#define   MAX_MSLICES				4
-#define   MEML3_EN_MASK				REG_GENMASK(3, 0)
-
-#define MIRROR_FUSE1				XE_REG(0x911c)
-
-#define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */
-#define   XELP_EU_MASK				REG_GENMASK(7, 0)
-#define XELP_GT_SLICE_ENABLE			XE_REG(0x9138)
-#define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
-
-#define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)
-#define   GT_VEBOX_DISABLE_MASK			REG_GENMASK(19, 16)
-#define   GT_VDBOX_DISABLE_MASK			REG_GENMASK(7, 0)
-
-#define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)
-#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)
-#define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)
-#define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
-#define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
-
-#define GDRST					XE_REG(0x941c)
-#define   GRDOM_GUC				REG_BIT(3)
-#define   GRDOM_FULL				REG_BIT(0)
-
-#define MISCCPCTL				XE_REG(0x9424)
-#define   DOP_CLOCK_GATE_RENDER_ENABLE		REG_BIT(1)
-
-#define UNSLCGCTL9430				XE_REG(0x9430)
-#define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)
-
-#define UNSLICE_UNIT_LEVEL_CLKGATE		XE_REG(0x9434)
-#define   VFUNIT_CLKGATE_DIS			REG_BIT(20)
-#define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */
-#define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */
-#define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)
-#define   HSUNIT_CLKGATE_DIS			REG_BIT(8)
-#define   VSUNIT_CLKGATE_DIS			REG_BIT(3)
-
-#define UNSLCGCTL9440				XE_REG(0x9440)
-#define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)
-#define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)
-#define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)
-#define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)
-#define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)
-#define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)
-#define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)
-#define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)
-#define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)
-#define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)
-#define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)
-#define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)
-
-#define UNSLCGCTL9444				XE_REG(0x9444)
-#define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)
-#define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)
-#define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)
-#define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)
-#define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)
-#define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)
-#define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)
-#define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)
-#define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)
-#define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)
-#define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)
-#define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)
-#define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)
-#define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)
-#define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)
-#define   LTCDD_CLKGATE_DIS			REG_BIT(10)
-
-#define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)
-#define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)
-#define   L3_CLKGATE_DIS			REG_BIT(16)
-#define   NODEDSS_CLKGATE_DIS			REG_BIT(12)
-#define   MSCUNIT_CLKGATE_DIS			REG_BIT(10)
-#define   RCCUNIT_CLKGATE_DIS			REG_BIT(7)
-#define   SARBUNIT_CLKGATE_DIS			REG_BIT(5)
-#define   SBEUNIT_CLKGATE_DIS			REG_BIT(4)
-
-#define UNSLICE_UNIT_LEVEL_CLKGATE2		XE_REG(0x94e4)
-#define   VSUNIT_CLKGATE2_DIS			REG_BIT(19)
-
-#define SUBSLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x9524)
-#define   DSS_ROUTER_CLKGATE_DIS		REG_BIT(28)
-#define   GWUNIT_CLKGATE_DIS			REG_BIT(16)
-
-#define SUBSLICE_UNIT_LEVEL_CLKGATE2		XE_REG_MCR(0x9528)
-#define   CPSSUNIT_CLKGATE_DIS			REG_BIT(9)
-
-#define SSMCGCTL9530				XE_REG_MCR(0x9530)
-#define   RTFUNIT_CLKGATE_DIS			REG_BIT(18)
-
-#define DFR_RATIO_EN_AND_CHICKEN		XE_REG_MCR(0x9550)
-#define   DFR_DISABLE				REG_BIT(9)
-
-#define RPNSWREQ				XE_REG(0xa008)
-#define   REQ_RATIO_MASK			REG_GENMASK(31, 23)
-
-#define RP_CONTROL				XE_REG(0xa024)
-#define   RPSWCTL_MASK				REG_GENMASK(10, 9)
-#define   RPSWCTL_ENABLE			REG_FIELD_PREP(RPSWCTL_MASK, 2)
-#define   RPSWCTL_DISABLE			REG_FIELD_PREP(RPSWCTL_MASK, 0)
-#define RC_CONTROL				XE_REG(0xa090)
-#define   RC_CTL_HW_ENABLE			REG_BIT(31)
-#define   RC_CTL_TO_MODE			REG_BIT(28)
-#define   RC_CTL_RC6_ENABLE			REG_BIT(18)
-#define RC_STATE				XE_REG(0xa094)
-#define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)
-#define MEDIA_POWERGATE_IDLE_HYSTERESIS		XE_REG(0xa0c4)
-#define RENDER_POWERGATE_IDLE_HYSTERESIS	XE_REG(0xa0c8)
-
-#define PMINTRMSK				XE_REG(0xa168)
-#define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)
-#define   ARAT_EXPIRED_INTRMSK			REG_BIT(9)
-
-#define FORCEWAKE_GT				XE_REG(0xa188)
-
-#define POWERGATE_ENABLE			XE_REG(0xa210)
-#define   RENDER_POWERGATE_ENABLE		REG_BIT(0)
-#define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)
-#define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
-#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
-
-#define CTC_MODE				XE_REG(0xa26c)
-#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
-#define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
-
-#define FORCEWAKE_RENDER			XE_REG(0xa278)
-#define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)
-#define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
-#define FORCEWAKE_GSC				XE_REG(0xa618)
-
-#define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
-#define   XEHPC_OVRLSCCC			REG_BIT(0)
-
-/* L3 Cache Control */
-#define LNCFCMOCS_REG_COUNT			32
-#define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
-#define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
-#define   L3_UPPER_LKUP_MASK			REG_BIT(23)
-#define   L3_UPPER_GLBGO_MASK			REG_BIT(22)
-#define   L3_UPPER_IDX_CACHEABILITY_MASK	REG_GENMASK(21, 20)
-#define   L3_UPPER_IDX_SCC_MASK			REG_GENMASK(19, 17)
-#define   L3_UPPER_IDX_ESC_MASK			REG_BIT(16)
-#define   L3_LKUP_MASK				REG_BIT(7)
-#define   L3_LKUP(value)			REG_FIELD_PREP(L3_LKUP_MASK, value)
-#define   L3_GLBGO_MASK				REG_BIT(6)
-#define   L3_GLBGO(value)			REG_FIELD_PREP(L3_GLBGO_MASK, value)
-#define   L3_CACHEABILITY_MASK			REG_GENMASK(5, 4)
-#define   L3_CACHEABILITY(value)		REG_FIELD_PREP(L3_CACHEABILITY_MASK, value)
-#define   L3_SCC_MASK				REG_GENMASK(3, 1)
-#define   L3_SCC(value)				REG_FIELD_PREP(L3_SCC_MASK, value)
-#define   L3_ESC_MASK				REG_BIT(0)
-#define   L3_ESC(value)				REG_FIELD_PREP(L3_ESC_MASK, value)
-
-#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
-#define   XEHP_LNESPARE				REG_BIT(19)
-
-#define L3SQCREG3				XE_REG_MCR(0xb108)
-#define   COMPPWOVERFETCHEN			REG_BIT(28)
-
-#define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
-#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
-
-#define XEHP_L3SCQREG7				XE_REG_MCR(0xb188)
-#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
-
-#define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)
-
-#define XE2_GLOBAL_INVAL			XE_REG(0xb404)
-
-#define SCRATCH1LPFC				XE_REG(0xb474)
-#define   EN_L3_RW_CCS_CACHE_FLUSH		REG_BIT(0)
-
-#define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
-
-#define XE2_TDF_CTRL				XE_REG(0xb418)
-#define   TRANSIENT_FLUSH_REQUEST		REG_BIT(0)
-
-#define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)
-#define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
-#define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
-#define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)
-#define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)
-#define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)
-#define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)
-#define   FORCE_MISS_FTLB			REG_BIT(3)
-
-#define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
-#define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
-#define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
-#define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
-
-#define XEHP_GAMCNTRL_CTRL			XE_REG_MCR(0xcf54)
-#define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
-#define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
-
-#define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
-#define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
-
-#define SAMPLER_INSTDONE			XE_REG_MCR(0xe160)
-#define ROW_INSTDONE				XE_REG_MCR(0xe164)
-
-#define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
-#define   ENABLE_SMALLPL			REG_BIT(15)
-#define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
-#define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)
-#define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
-
-#define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
-#define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
-#define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
-
-#define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
-#define   DISABLE_ECC				REG_BIT(5)
-#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
-
-#define ROW_CHICKEN4				XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
-#define   DISABLE_GRF_CLEAR			REG_BIT(13)
-#define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)
-#define   DISABLE_TDL_PUSH			REG_BIT(9)
-#define   DIS_PICK_2ND_EU			REG_BIT(7)
-#define   DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)
-#define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)
-#define   THREAD_EX_ARB_MODE_RR_AFTER_DEP	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
-
-#define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
-#define   XE2_EUPEND_CHK_FLUSH_DIS		REG_BIT(14)
-#define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
-
-#define TDL_TSL_CHICKEN				XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
-#define   STK_ID_RESTRICT			REG_BIT(12)
-#define   SLM_WMTP_RESTORE			REG_BIT(11)
-
-#define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
-#define   UGM_BACKUP_MODE			REG_BIT(13)
-#define   MDQ_ARBITRATION_MODE			REG_BIT(12)
-#define   STALL_DOP_GATING_DISABLE		REG_BIT(5)
-#define   EARLY_EOT_DIS				REG_BIT(1)
-
-#define ROW_CHICKEN2				XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
-#define   DISABLE_READ_SUPPRESSION		REG_BIT(15)
-#define   DISABLE_EARLY_READ			REG_BIT(14)
-#define   ENABLE_LARGE_GRF_MODE			REG_BIT(12)
-#define   PUSH_CONST_DEREF_HOLD_DIS		REG_BIT(8)
-#define   DISABLE_TDL_SVHS_GATING		REG_BIT(1)
-#define   DISABLE_DOP_GATING			REG_BIT(0)
-
-#define RT_CTRL					XE_REG_MCR(0xe530)
-#define   DIS_NULL_QUERY			REG_BIT(10)
-
-#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
-#define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
-
-#define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
-#define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
-#define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
-
-#define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
-#define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
-#define   WR_REQ_CHAINING_DIS			REG_BIT(26)
-#define   TGM_WRITE_EOM_FORCE			REG_BIT(17)
-#define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)
-#define   SEQUENTIAL_ACCESS_UPGRADE_DISABLE	REG_BIT(13)
-
-#define LSC_CHICKEN_BIT_0_UDW			XE_REG_MCR(0xe7c8 + 4)
-#define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
-#define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
-#define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
-#define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
-#define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
-#define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
-#define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
-#define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
-
-#define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
-#define   COMP_CKN_IN				REG_GENMASK(30, 29)
-
-#define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
-#define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
-#define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
-
-/*
- * Total of 4 cslices, where each cslice is in the form:
- *   [0-3]     CCS ID
- *   [4-6]     RSVD
- *   [7]       Disabled
- */
-#define CCS_MODE				XE_REG(0x14804)
-#define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */
-#define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */
-#define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)
-#define   CCS_MODE_CSLICE(cslice, ccs) \
-	((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
-
-#define FORCEWAKE_ACK_GT			XE_REG(0x130044)
-
-/* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */
-#define   FORCEWAKE_KERNEL			0
-#define   FORCEWAKE_MT(bit)			BIT(bit)
-#define   FORCEWAKE_MT_MASK(bit)		BIT((bit) + 16)
-
-#define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)
-#define MTL_MEDIA_MC6				XE_REG(0x138048)
-
-#define GT_CORE_STATUS				XE_REG(0x138060)
-#define   RCN_MASK				REG_GENMASK(2, 0)
-#define   GT_C0					0
-#define   GT_C6					3
-
-#define GT_GFX_RC6_LOCKED			XE_REG(0x138104)
-#define GT_GFX_RC6				XE_REG(0x138108)
-
-#define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
-#define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
-#define   PROCHOT_MASK				REG_BIT(0)
-#define   THERMAL_LIMIT_MASK			REG_BIT(1)
-#define   RATL_MASK				REG_BIT(5)
-#define   VR_THERMALERT_MASK			REG_BIT(6)
-#define   VR_TDC_MASK				REG_BIT(7)
-#define   POWER_LIMIT_4_MASK			REG_BIT(8)
-#define   POWER_LIMIT_1_MASK			REG_BIT(10)
-#define   POWER_LIMIT_2_MASK			REG_BIT(11)
-
-#define GT_PERF_STATUS				XE_REG(0x1381b4)
-#define   VOLTAGE_MASK				REG_GENMASK(10, 0)
-
-/*
- * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
- *       On newer platforms, VFs are using memory-based interrupts instead.
- *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
- */
-
-#define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
-#define   INTR_GSC				REG_BIT(31)
-#define   INTR_GUC				REG_BIT(25)
-#define   INTR_MGUC				REG_BIT(24)
-#define   INTR_BCS8				REG_BIT(23)
-#define   INTR_BCS(x)				REG_BIT(15 - (x))
-#define   INTR_CCS(x)				REG_BIT(4 + (x))
-#define   INTR_RCS0				REG_BIT(0)
-#define   INTR_VECS(x)				REG_BIT(31 - (x))
-#define   INTR_VCS(x)				REG_BIT(x)
-
-#define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030, XE_REG_OPTION_VF)
-#define VCS_VECS_INTR_ENABLE			XE_REG(0x190034, XE_REG_OPTION_VF)
-#define GUC_SG_INTR_ENABLE			XE_REG(0x190038, XE_REG_OPTION_VF)
-#define   ENGINE1_MASK				REG_GENMASK(31, 16)
-#define   ENGINE0_MASK				REG_GENMASK(15, 0)
-#define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c, XE_REG_OPTION_VF)
-#define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044, XE_REG_OPTION_VF)
-#define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048, XE_REG_OPTION_VF)
-
-#define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
-#define   INTR_DATA_VALID			REG_BIT(31)
-#define   INTR_ENGINE_INSTANCE(x)		REG_FIELD_GET(GENMASK(25, 20), x)
-#define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)
-#define   INTR_ENGINE_INTR(x)			REG_FIELD_GET(GENMASK(15, 0), x)
-#define   OTHER_GUC_INSTANCE			0
-#define   OTHER_GSC_HECI2_INSTANCE		3
-#define   OTHER_GSC_INSTANCE			6
-
-#define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
-#define RCS0_RSVD_INTR_MASK			XE_REG(0x190090, XE_REG_OPTION_VF)
-#define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
-#define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
-#define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
-#define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
-#define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
-#define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
-#define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
-#define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4, XE_REG_OPTION_VF)
-#define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)
-#define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)
-#define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)
-#define XEHPC_BCS3_BCS4_INTR_MASK		XE_REG(0x190114)
-#define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)
-#define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)
-#define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
-#define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
-#define   GSC_ER_COMPLETE			REG_BIT(5)
-#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
-#define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
-#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
-
-#endif
diff --git a/rr-cache/7d9a83c9e4e63eac2b91d591ebc08fe660630185/postimage b/rr-cache/7d9a83c9e4e63eac2b91d591ebc08fe660630185/postimage
deleted file mode 100644
index 1ff9602a52f6..000000000000
--- a/rr-cache/7d9a83c9e4e63eac2b91d591ebc08fe660630185/postimage
+++ /dev/null
@@ -1,309 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the drm device driver.  This driver provides support for the
-# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-
-# Enable W=1 warnings not enabled in drm subsystem Makefile
-subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-
-# Enable -Werror in CI and development
-subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
-
-subdir-ccflags-y += -I$(obj) -I$(src)
-
-# generated sources
-
-hostprogs := xe_gen_wa_oob
-generated_oob := $(obj)/generated/xe_wa_oob.c $(obj)/generated/xe_wa_oob.h
-quiet_cmd_wa_oob = GEN     $(notdir $(generated_oob))
-      cmd_wa_oob = mkdir -p $(@D); $^ $(generated_oob)
-$(obj)/generated/%_wa_oob.c $(obj)/generated/%_wa_oob.h: $(obj)/xe_gen_wa_oob \
-		 $(src)/xe_wa_oob.rules
-	$(call cmd,wa_oob)
-
-# Please keep these build lists sorted!
-
-# core driver code
-
-xe-y += xe_bb.o \
-	xe_bo.o \
-	xe_bo_evict.o \
-	xe_debugfs.o \
-	xe_devcoredump.o \
-	xe_device.o \
-	xe_device_sysfs.o \
-	xe_dma_buf.o \
-	xe_drm_client.o \
-	xe_exec.o \
-	xe_execlist.o \
-	xe_exec_queue.o \
-	xe_force_wake.o \
-	xe_ggtt.o \
-	xe_gpu_scheduler.o \
-	xe_gsc.o \
-	xe_gsc_proxy.o \
-	xe_gsc_submit.o \
-	xe_gt.o \
-	xe_gt_ccs_mode.o \
-	xe_gt_clock.o \
-	xe_gt_debugfs.o \
-	xe_gt_freq.o \
-	xe_gt_idle.o \
-	xe_gt_mcr.o \
-	xe_gt_pagefault.o \
-	xe_gt_sysfs.o \
-	xe_gt_throttle.o \
-	xe_gt_tlb_invalidation.o \
-	xe_gt_topology.o \
-	xe_guc.o \
-	xe_guc_ads.o \
-	xe_guc_ct.o \
-	xe_guc_db_mgr.o \
-	xe_guc_debugfs.o \
-	xe_guc_hwconfig.o \
-	xe_guc_id_mgr.o \
-	xe_guc_klv_helpers.o \
-	xe_guc_log.o \
-	xe_guc_pc.o \
-	xe_guc_submit.o \
-	xe_heci_gsc.o \
-	xe_hw_engine.o \
-	xe_hw_engine_class_sysfs.o \
-	xe_hw_fence.o \
-	xe_huc.o \
-	xe_huc_debugfs.o \
-	xe_irq.o \
-	xe_lrc.o \
-	xe_migrate.o \
-	xe_mmio.o \
-	xe_mocs.o \
-	xe_module.o \
-	xe_oa.o \
-	xe_observation.o \
-	xe_pat.o \
-	xe_pci.o \
-	xe_pcode.o \
-	xe_pm.o \
-	xe_preempt_fence.o \
-	xe_pt.o \
-	xe_pt_walk.o \
-	xe_query.o \
-	xe_range_fence.o \
-	xe_reg_sr.o \
-	xe_reg_whitelist.o \
-	xe_rtp.o \
-	xe_ring_ops.o \
-	xe_sa.o \
-	xe_sched_job.o \
-	xe_step.o \
-	xe_sync.o \
-	xe_tile.o \
-	xe_tile_sysfs.o \
-	xe_trace.o \
-	xe_trace_bo.o \
-	xe_trace_guc.o \
-	xe_ttm_sys_mgr.o \
-	xe_ttm_stolen_mgr.o \
-	xe_ttm_vram_mgr.o \
-	xe_tuning.o \
-	xe_uc.o \
-	xe_uc_debugfs.o \
-	xe_uc_fw.o \
-	xe_vm.o \
-	xe_vram.o \
-	xe_vram_freq.o \
-	xe_wait_user_fence.o \
-	xe_wa.o \
-	xe_wopcm.o
-
-xe-$(CONFIG_HMM_MIRROR) += xe_hmm.o
-
-# graphics hardware monitoring (HWMON) support
-xe-$(CONFIG_HWMON) += xe_hwmon.o
-
-# graphics virtualization (SR-IOV) support
-xe-y += \
-	xe_gt_sriov_vf.o \
-	xe_gt_sriov_vf_debugfs.o \
-	xe_guc_relay.o \
-	xe_memirq.o \
-	xe_sriov.o
-
-xe-$(CONFIG_PCI_IOV) += \
-	xe_gt_sriov_pf.o \
-	xe_gt_sriov_pf_config.o \
-	xe_gt_sriov_pf_control.o \
-	xe_gt_sriov_pf_debugfs.o \
-	xe_gt_sriov_pf_monitor.o \
-	xe_gt_sriov_pf_policy.o \
-	xe_gt_sriov_pf_service.o \
-	xe_lmtt.o \
-	xe_lmtt_2l.o \
-	xe_lmtt_ml.o \
-	xe_pci_sriov.o \
-	xe_sriov_pf.o
-
-# include helpers for tests even when XE is built-in
-ifdef CONFIG_DRM_XE_KUNIT_TEST
-xe-y += tests/xe_kunit_helpers.o
-endif
-
-# i915 Display compat #defines and #includes
-subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
-	-I$(src)/display/ext \
-	-I$(src)/compat-i915-headers \
-	-I$(srctree)/drivers/gpu/drm/i915/display/ \
-	-Ddrm_i915_gem_object=xe_bo \
-	-Ddrm_i915_private=xe_device
-
-# Rule to build SOC code shared with i915
-$(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE
-	$(call cmd,force_checksrc)
-	$(call if_changed_rule,cc_o_c)
-
-# Rule to build display code shared with i915
-$(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
-	$(call cmd,force_checksrc)
-	$(call if_changed_rule,cc_o_c)
-
-# Display code specific to xe
-xe-$(CONFIG_DRM_XE_DISPLAY) += \
-	display/ext/i915_irq.o \
-	display/ext/i915_utils.o \
-	display/intel_fb_bo.o \
-	display/intel_fbdev_fb.o \
-	display/xe_display.o \
-	display/xe_display_misc.o \
-	display/xe_display_rps.o \
-	display/xe_display_wa.o \
-	display/xe_dsb_buffer.o \
-	display/xe_fb_pin.o \
-	display/xe_hdcp_gsc.o \
-	display/xe_plane_initial.o \
-	display/xe_tdf.o
-
-# SOC code shared with i915
-xe-$(CONFIG_DRM_XE_DISPLAY) += \
-	i915-soc/intel_dram.o \
-	i915-soc/intel_pch.o
-
-# Display code shared with i915
-xe-$(CONFIG_DRM_XE_DISPLAY) += \
-	i915-display/icl_dsi.o \
-	i915-display/intel_alpm.o \
-	i915-display/intel_atomic.o \
-	i915-display/intel_atomic_plane.o \
-	i915-display/intel_audio.o \
-	i915-display/intel_backlight.o \
-	i915-display/intel_bios.o \
-	i915-display/intel_bw.o \
-	i915-display/intel_cdclk.o \
-	i915-display/intel_color.o \
-	i915-display/intel_combo_phy.o \
-	i915-display/intel_connector.o \
-	i915-display/intel_crtc.o \
-	i915-display/intel_crtc_state_dump.o \
-	i915-display/intel_cursor.o \
-	i915-display/intel_cx0_phy.o \
-	i915-display/intel_ddi.o \
-	i915-display/intel_ddi_buf_trans.o \
-	i915-display/intel_display.o \
-	i915-display/intel_display_device.o \
-	i915-display/intel_display_driver.o \
-	i915-display/intel_display_irq.o \
-	i915-display/intel_display_params.o \
-	i915-display/intel_display_power.o \
-	i915-display/intel_display_power_map.o \
-	i915-display/intel_display_power_well.o \
-	i915-display/intel_display_trace.o \
-	i915-display/intel_display_wa.o \
-	i915-display/intel_dkl_phy.o \
-	i915-display/intel_dmc.o \
-	i915-display/intel_dp.o \
-	i915-display/intel_dp_aux.o \
-	i915-display/intel_dp_aux_backlight.o \
-	i915-display/intel_dp_hdcp.o \
-	i915-display/intel_dp_link_training.o \
-	i915-display/intel_dp_mst.o \
-	i915-display/intel_dpll.o \
-	i915-display/intel_dpll_mgr.o \
-	i915-display/intel_dpt_common.o \
-	i915-display/intel_drrs.o \
-	i915-display/intel_dsb.o \
-	i915-display/intel_dsi.o \
-	i915-display/intel_dsi_dcs_backlight.o \
-	i915-display/intel_dsi_vbt.o \
-	i915-display/intel_encoder.o \
-	i915-display/intel_fb.o \
-	i915-display/intel_fbc.o \
-	i915-display/intel_fdi.o \
-	i915-display/intel_fifo_underrun.o \
-	i915-display/intel_frontbuffer.o \
-	i915-display/intel_global_state.o \
-	i915-display/intel_gmbus.o \
-	i915-display/intel_hdcp.o \
-	i915-display/intel_hdcp_gsc_message.o \
-	i915-display/intel_hdmi.o \
-	i915-display/intel_hotplug.o \
-	i915-display/intel_hotplug_irq.o \
-	i915-display/intel_hti.o \
-	i915-display/intel_link_bw.o \
-	i915-display/intel_lspcon.o \
-	i915-display/intel_modeset_lock.o \
-	i915-display/intel_modeset_setup.o \
-	i915-display/intel_modeset_verify.o \
-	i915-display/intel_panel.o \
-	i915-display/intel_pmdemand.o \
-	i915-display/intel_pps.o \
-	i915-display/intel_psr.o \
-	i915-display/intel_qp_tables.o \
-	i915-display/intel_quirks.o \
-	i915-display/intel_snps_phy.o \
-	i915-display/intel_tc.o \
-	i915-display/intel_vblank.o \
-	i915-display/intel_vdsc.o \
-	i915-display/intel_vga.o \
-	i915-display/intel_vrr.o \
-	i915-display/intel_dmc_wl.o \
-	i915-display/intel_wm.o \
-	i915-display/skl_scaler.o \
-	i915-display/skl_universal_plane.o \
-	i915-display/skl_watermark.o
-
-ifeq ($(CONFIG_ACPI),y)
-	xe-$(CONFIG_DRM_XE_DISPLAY) += \
-		i915-display/intel_acpi.o \
-		i915-display/intel_opregion.o
-endif
-
-ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)
-	xe-$(CONFIG_DRM_XE_DISPLAY) += i915-display/intel_fbdev.o
-endif
-
-ifeq ($(CONFIG_DEBUG_FS),y)
-	xe-$(CONFIG_DRM_XE_DISPLAY) += \
-		i915-display/intel_display_debugfs.o \
-		i915-display/intel_display_debugfs_params.o \
-		i915-display/intel_pipe_crc.o
-endif
-
-obj-$(CONFIG_DRM_XE) += xe.o
-obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/
-
-# header test
-hdrtest_find_args := -not -path xe_rtp_helpers.h
-ifneq ($(CONFIG_DRM_XE_DISPLAY),y)
-	hdrtest_find_args += -not -path display/\* -not -path compat-i915-headers/\* -not -path xe_display.h
-endif
-
-always-$(CONFIG_DRM_XE_WERROR) += \
-	$(patsubst %.h,%.hdrtest, $(shell cd $(src) && find * -name '*.h' $(hdrtest_find_args)))
-
-quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
-      cmd_hdrtest = $(CC) -DHDRTEST $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@
-
-$(obj)/%.hdrtest: $(src)/%.h FORCE
-	$(call if_changed_dep,hdrtest)
-
-uses_generated_oob := $(addprefix $(obj)/, $(xe-y))
-$(uses_generated_oob): $(obj)/generated/xe_wa_oob.h
diff --git a/rr-cache/7d9a83c9e4e63eac2b91d591ebc08fe660630185/preimage b/rr-cache/7d9a83c9e4e63eac2b91d591ebc08fe660630185/preimage
deleted file mode 100644
index 2012afc9287e..000000000000
--- a/rr-cache/7d9a83c9e4e63eac2b91d591ebc08fe660630185/preimage
+++ /dev/null
@@ -1,329 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the drm device driver.  This driver provides support for the
-# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-
-# Enable W=1 warnings not enabled in drm subsystem Makefile
-subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-
-# Enable -Werror in CI and development
-subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
-
-subdir-ccflags-y += -I$(obj) -I$(src)
-
-# generated sources
-
-hostprogs := xe_gen_wa_oob
-generated_oob := $(obj)/generated/xe_wa_oob.c $(obj)/generated/xe_wa_oob.h
-quiet_cmd_wa_oob = GEN     $(notdir $(generated_oob))
-      cmd_wa_oob = mkdir -p $(@D); $^ $(generated_oob)
-$(obj)/generated/%_wa_oob.c $(obj)/generated/%_wa_oob.h: $(obj)/xe_gen_wa_oob \
-		 $(src)/xe_wa_oob.rules
-	$(call cmd,wa_oob)
-
-<<<<<<<
-=======
-uses_generated_oob := \
-	$(obj)/xe_ggtt.o \
-	$(obj)/xe_device.o \
-	$(obj)/xe_gsc.o \
-	$(obj)/xe_gt.o \
-	$(obj)/xe_guc.o \
-	$(obj)/xe_guc_ads.o \
-	$(obj)/xe_guc_pc.o \
-	$(obj)/xe_migrate.o \
-	$(obj)/xe_pat.o \
-	$(obj)/xe_ring_ops.o \
-	$(obj)/xe_vm.o \
-	$(obj)/xe_wa.o \
-	$(obj)/xe_ttm_stolen_mgr.o
-
-$(uses_generated_oob): $(generated_oob)
-
->>>>>>>
-# Please keep these build lists sorted!
-
-# core driver code
-
-xe-y += xe_bb.o \
-	xe_bo.o \
-	xe_bo_evict.o \
-	xe_debugfs.o \
-	xe_devcoredump.o \
-	xe_device.o \
-	xe_device_sysfs.o \
-	xe_dma_buf.o \
-	xe_drm_client.o \
-	xe_exec.o \
-	xe_execlist.o \
-	xe_exec_queue.o \
-	xe_force_wake.o \
-	xe_ggtt.o \
-	xe_gpu_scheduler.o \
-	xe_gsc.o \
-	xe_gsc_proxy.o \
-	xe_gsc_submit.o \
-	xe_gt.o \
-	xe_gt_ccs_mode.o \
-	xe_gt_clock.o \
-	xe_gt_debugfs.o \
-	xe_gt_freq.o \
-	xe_gt_idle.o \
-	xe_gt_mcr.o \
-	xe_gt_pagefault.o \
-	xe_gt_sysfs.o \
-	xe_gt_throttle.o \
-	xe_gt_tlb_invalidation.o \
-	xe_gt_topology.o \
-	xe_guc.o \
-	xe_guc_ads.o \
-	xe_guc_ct.o \
-	xe_guc_db_mgr.o \
-	xe_guc_debugfs.o \
-	xe_guc_hwconfig.o \
-	xe_guc_id_mgr.o \
-	xe_guc_klv_helpers.o \
-	xe_guc_log.o \
-	xe_guc_pc.o \
-	xe_guc_submit.o \
-	xe_heci_gsc.o \
-	xe_hw_engine.o \
-	xe_hw_engine_class_sysfs.o \
-	xe_hw_fence.o \
-	xe_huc.o \
-	xe_huc_debugfs.o \
-	xe_irq.o \
-	xe_lrc.o \
-	xe_migrate.o \
-	xe_mmio.o \
-	xe_mocs.o \
-	xe_module.o \
-	xe_oa.o \
-	xe_observation.o \
-	xe_pat.o \
-	xe_pci.o \
-	xe_pcode.o \
-	xe_pm.o \
-	xe_preempt_fence.o \
-	xe_pt.o \
-	xe_pt_walk.o \
-	xe_query.o \
-	xe_range_fence.o \
-	xe_reg_sr.o \
-	xe_reg_whitelist.o \
-	xe_rtp.o \
-	xe_ring_ops.o \
-	xe_sa.o \
-	xe_sched_job.o \
-	xe_step.o \
-	xe_sync.o \
-	xe_tile.o \
-	xe_tile_sysfs.o \
-	xe_trace.o \
-	xe_trace_bo.o \
-	xe_trace_guc.o \
-	xe_ttm_sys_mgr.o \
-	xe_ttm_stolen_mgr.o \
-	xe_ttm_vram_mgr.o \
-	xe_tuning.o \
-	xe_uc.o \
-	xe_uc_debugfs.o \
-	xe_uc_fw.o \
-	xe_vm.o \
-	xe_vram.o \
-	xe_vram_freq.o \
-	xe_wait_user_fence.o \
-	xe_wa.o \
-	xe_wopcm.o
-
-xe-$(CONFIG_HMM_MIRROR) += xe_hmm.o
-
-# graphics hardware monitoring (HWMON) support
-xe-$(CONFIG_HWMON) += xe_hwmon.o
-
-# graphics virtualization (SR-IOV) support
-xe-y += \
-	xe_gt_sriov_vf.o \
-	xe_gt_sriov_vf_debugfs.o \
-	xe_guc_relay.o \
-	xe_memirq.o \
-	xe_sriov.o
-
-xe-$(CONFIG_PCI_IOV) += \
-	xe_gt_sriov_pf.o \
-	xe_gt_sriov_pf_config.o \
-	xe_gt_sriov_pf_control.o \
-	xe_gt_sriov_pf_debugfs.o \
-	xe_gt_sriov_pf_monitor.o \
-	xe_gt_sriov_pf_policy.o \
-	xe_gt_sriov_pf_service.o \
-	xe_lmtt.o \
-	xe_lmtt_2l.o \
-	xe_lmtt_ml.o \
-	xe_pci_sriov.o \
-	xe_sriov_pf.o
-
-# include helpers for tests even when XE is built-in
-ifdef CONFIG_DRM_XE_KUNIT_TEST
-xe-y += tests/xe_kunit_helpers.o
-endif
-
-# i915 Display compat #defines and #includes
-subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
-	-I$(src)/display/ext \
-	-I$(src)/compat-i915-headers \
-	-I$(srctree)/drivers/gpu/drm/i915/display/ \
-	-Ddrm_i915_gem_object=xe_bo \
-	-Ddrm_i915_private=xe_device
-
-# Rule to build SOC code shared with i915
-$(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE
-	$(call cmd,force_checksrc)
-	$(call if_changed_rule,cc_o_c)
-
-# Rule to build display code shared with i915
-$(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
-	$(call cmd,force_checksrc)
-	$(call if_changed_rule,cc_o_c)
-
-# Display code specific to xe
-xe-$(CONFIG_DRM_XE_DISPLAY) += \
-	display/ext/i915_irq.o \
-	display/ext/i915_utils.o \
-	display/intel_fb_bo.o \
-	display/intel_fbdev_fb.o \
-	display/xe_display.o \
-	display/xe_display_misc.o \
-	display/xe_display_rps.o \
-	display/xe_display_wa.o \
-	display/xe_dsb_buffer.o \
-	display/xe_fb_pin.o \
-	display/xe_hdcp_gsc.o \
-	display/xe_plane_initial.o \
-	display/xe_tdf.o
-
-# SOC code shared with i915
-xe-$(CONFIG_DRM_XE_DISPLAY) += \
-	i915-soc/intel_dram.o \
-	i915-soc/intel_pch.o
-
-# Display code shared with i915
-xe-$(CONFIG_DRM_XE_DISPLAY) += \
-	i915-display/icl_dsi.o \
-	i915-display/intel_alpm.o \
-	i915-display/intel_atomic.o \
-	i915-display/intel_atomic_plane.o \
-	i915-display/intel_audio.o \
-	i915-display/intel_backlight.o \
-	i915-display/intel_bios.o \
-	i915-display/intel_bw.o \
-	i915-display/intel_cdclk.o \
-	i915-display/intel_color.o \
-	i915-display/intel_combo_phy.o \
-	i915-display/intel_connector.o \
-	i915-display/intel_crtc.o \
-	i915-display/intel_crtc_state_dump.o \
-	i915-display/intel_cursor.o \
-	i915-display/intel_cx0_phy.o \
-	i915-display/intel_ddi.o \
-	i915-display/intel_ddi_buf_trans.o \
-	i915-display/intel_display.o \
-	i915-display/intel_display_device.o \
-	i915-display/intel_display_driver.o \
-	i915-display/intel_display_irq.o \
-	i915-display/intel_display_params.o \
-	i915-display/intel_display_power.o \
-	i915-display/intel_display_power_map.o \
-	i915-display/intel_display_power_well.o \
-	i915-display/intel_display_trace.o \
-	i915-display/intel_display_wa.o \
-	i915-display/intel_dkl_phy.o \
-	i915-display/intel_dmc.o \
-	i915-display/intel_dp.o \
-	i915-display/intel_dp_aux.o \
-	i915-display/intel_dp_aux_backlight.o \
-	i915-display/intel_dp_hdcp.o \
-	i915-display/intel_dp_link_training.o \
-	i915-display/intel_dp_mst.o \
-	i915-display/intel_dpll.o \
-	i915-display/intel_dpll_mgr.o \
-	i915-display/intel_dpt_common.o \
-	i915-display/intel_drrs.o \
-	i915-display/intel_dsb.o \
-	i915-display/intel_dsi.o \
-	i915-display/intel_dsi_dcs_backlight.o \
-	i915-display/intel_dsi_vbt.o \
-	i915-display/intel_encoder.o \
-	i915-display/intel_fb.o \
-	i915-display/intel_fbc.o \
-	i915-display/intel_fdi.o \
-	i915-display/intel_fifo_underrun.o \
-	i915-display/intel_frontbuffer.o \
-	i915-display/intel_global_state.o \
-	i915-display/intel_gmbus.o \
-	i915-display/intel_hdcp.o \
-	i915-display/intel_hdcp_gsc_message.o \
-	i915-display/intel_hdmi.o \
-	i915-display/intel_hotplug.o \
-	i915-display/intel_hotplug_irq.o \
-	i915-display/intel_hti.o \
-	i915-display/intel_link_bw.o \
-	i915-display/intel_lspcon.o \
-	i915-display/intel_modeset_lock.o \
-	i915-display/intel_modeset_setup.o \
-	i915-display/intel_modeset_verify.o \
-	i915-display/intel_panel.o \
-	i915-display/intel_pmdemand.o \
-	i915-display/intel_pps.o \
-	i915-display/intel_psr.o \
-	i915-display/intel_qp_tables.o \
-	i915-display/intel_quirks.o \
-	i915-display/intel_snps_phy.o \
-	i915-display/intel_tc.o \
-	i915-display/intel_vblank.o \
-	i915-display/intel_vdsc.o \
-	i915-display/intel_vga.o \
-	i915-display/intel_vrr.o \
-	i915-display/intel_dmc_wl.o \
-	i915-display/intel_wm.o \
-	i915-display/skl_scaler.o \
-	i915-display/skl_universal_plane.o \
-	i915-display/skl_watermark.o
-
-ifeq ($(CONFIG_ACPI),y)
-	xe-$(CONFIG_DRM_XE_DISPLAY) += \
-		i915-display/intel_acpi.o \
-		i915-display/intel_opregion.o
-endif
-
-ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)
-	xe-$(CONFIG_DRM_XE_DISPLAY) += i915-display/intel_fbdev.o
-endif
-
-ifeq ($(CONFIG_DEBUG_FS),y)
-	xe-$(CONFIG_DRM_XE_DISPLAY) += \
-		i915-display/intel_display_debugfs.o \
-		i915-display/intel_display_debugfs_params.o \
-		i915-display/intel_pipe_crc.o
-endif
-
-obj-$(CONFIG_DRM_XE) += xe.o
-obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/
-
-# header test
-hdrtest_find_args := -not -path xe_rtp_helpers.h
-ifneq ($(CONFIG_DRM_XE_DISPLAY),y)
-	hdrtest_find_args += -not -path display/\* -not -path compat-i915-headers/\* -not -path xe_display.h
-endif
-
-always-$(CONFIG_DRM_XE_WERROR) += \
-	$(patsubst %.h,%.hdrtest, $(shell cd $(src) && find * -name '*.h' $(hdrtest_find_args)))
-
-quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
-      cmd_hdrtest = $(CC) -DHDRTEST $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@
-
-$(obj)/%.hdrtest: $(src)/%.h FORCE
-	$(call if_changed_dep,hdrtest)
-
-uses_generated_oob := $(addprefix $(obj)/, $(xe-y))
-$(uses_generated_oob): $(obj)/generated/xe_wa_oob.h
diff --git a/rr-cache/8e9c927d63e12b61d10da289a2f9008b4e38a67a/preimage b/rr-cache/8e9c927d63e12b61d10da289a2f9008b4e38a67a/preimage
deleted file mode 100644
index 0b507ba53f34..000000000000
--- a/rr-cache/8e9c927d63e12b61d10da289a2f9008b4e38a67a/preimage
+++ /dev/null
@@ -1,601 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef _XE_GT_REGS_H_
-#define _XE_GT_REGS_H_
-
-#include "regs/xe_reg_defs.h"
-
-/*
- * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
- * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically
- * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
- */
-#define MEDIA_GT_GSI_OFFSET				0x380000
-#define MEDIA_GT_GSI_LENGTH				0x40000
-
-/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
-#define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)
-#define   MTL_CAGF_MASK					REG_GENMASK(8, 0)
-#define   MTL_CC_MASK					REG_GENMASK(12, 9)
-
-/* RPM unit config (Gen8+) */
-#define RPM_CONFIG0					XE_REG(0xd00)
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
-#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3
-#define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
-
-#define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)
-#define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)
-#define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)
-
-#define GMD_ID					XE_REG(0xd8c)
-#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
-#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
-#define   GMD_ID_REVID				REG_GENMASK(5, 0)
-
-#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
-#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)
-
-#define MCFG_MCR_SELECTOR			XE_REG(0xfd0)
-#define MTL_MCR_SELECTOR			XE_REG(0xfd4)
-#define SF_MCR_SELECTOR				XE_REG(0xfd8)
-#define MCR_SELECTOR				XE_REG(0xfdc)
-#define GAM_MCR_SELECTOR			XE_REG(0xfe0)
-#define   MCR_MULTICAST				REG_BIT(31)
-#define   MCR_SLICE_MASK			REG_GENMASK(30, 27)
-#define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
-#define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
-#define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
-#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
-#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
-
-#define PS_INVOCATION_COUNT			XE_REG(0x2348)
-
-#define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)
-#define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)
-#define   LE_SSE_MASK				REG_GENMASK(18, 17)
-#define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
-#define   LE_COS_MASK				REG_GENMASK(16, 15)
-#define   LE_COS(value)				REG_FIELD_PREP(LE_COS_MASK)
-#define   LE_SCF_MASK				REG_BIT(14)
-#define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
-#define   LE_PFM_MASK				REG_GENMASK(13, 11)
-#define   LE_PFM(value)				REG_FIELD_PREP(LE_PFM_MASK, value)
-#define   LE_SCC_MASK				REG_GENMASK(10, 8)
-#define   LE_SCC(value)				REG_FIELD_PREP(LE_SCC_MASK, value)
-#define   LE_RSC_MASK				REG_BIT(7)
-#define   LE_RSC(value)				REG_FIELD_PREP(LE_RSC_MASK, value)
-#define   LE_AOM_MASK				REG_BIT(6)
-#define   LE_AOM(value)				REG_FIELD_PREP(LE_AOM_MASK, value)
-#define   LE_LRUM_MASK				REG_GENMASK(5, 4)
-#define   LE_LRUM(value)			REG_FIELD_PREP(LE_LRUM_MASK, value)
-#define   LE_TGT_CACHE_MASK			REG_GENMASK(3, 2)
-#define   LE_TGT_CACHE(value)			REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
-#define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
-#define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
-
-<<<<<<<
-#define STATELESS_COMPRESSION_CTRL		XE_REG_MCR(0x4148)
-#define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)
-
-#define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)
-=======
-#define XE2_GAMREQSTRM_CTRL			XE_REG(0x4194)
->>>>>>>
-#define   CG_DIS_CNTLBUS			REG_BIT(6)
-
-#define CCS_AUX_INV				XE_REG(0x4208)
-
-#define VD0_AUX_INV				XE_REG(0x4218)
-#define VE0_AUX_INV				XE_REG(0x4238)
-
-#define VE1_AUX_INV				XE_REG(0x42b8)
-#define   AUX_INV				REG_BIT(0)
-
-#define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)
-#define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
-#define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
-
-#define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
-#define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
-
-#define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
-#define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
-
-#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
-#define   TBIMR_FAST_CLIP			REG_BIT(5)
-
-#define FF_MODE					XE_REG_MCR(0x6210)
-#define   DIS_TE_AUTOSTRIP			REG_BIT(31)
-#define   DIS_MESH_PARTIAL_AUTOSTRIP		REG_BIT(16)
-#define   DIS_MESH_AUTOSTRIP			REG_BIT(15)
-
-#define VFLSKPD					XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
-#define   DIS_PARTIAL_AUTOSTRIP			REG_BIT(9)
-#define   DIS_AUTOSTRIP				REG_BIT(6)
-#define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
-#define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
-
-#define FF_MODE2				XE_REG(0x6604)
-#define XEHP_FF_MODE2				XE_REG_MCR(0x6604)
-#define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)
-#define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
-#define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)
-#define   FF_MODE2_TDS_TIMER_128		REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-
-#define XEHPG_INSTDONE_GEOM_SVGUNIT		XE_REG_MCR(0x666c)
-
-#define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)
-#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)
-
-#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)
-#define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)
-
-#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)
-#define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
-#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE		REG_BIT(13)
-
-#define XEHP_PSS_MODE2				XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
-#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)
-
-#define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
-#define   FLSH_IGNORES_PSD			REG_BIT(10)
-#define   FD_END_COLLECT			REG_BIT(5)
-
-#define SC_INSTDONE				XE_REG(0x7100)
-#define SC_INSTDONE_EXTRA			XE_REG(0x7104)
-#define SC_INSTDONE_EXTRA2			XE_REG(0x7108)
-
-#define XEHPG_SC_INSTDONE			XE_REG_MCR(0x7100)
-#define XEHPG_SC_INSTDONE_EXTRA			XE_REG_MCR(0x7104)
-#define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)
-
-#define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)
-#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
-
-#define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)
-#define XEHP_COMMON_SLICE_CHICKEN3			XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)
-#define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
-#define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)
-#define   BLEND_EMB_FIX_DISABLE_IN_RCC			REG_BIT(11)
-#define   DISABLE_CPS_AWARE_COLOR_PIPE			REG_BIT(9)
-
-#define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
-#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)
-
-#define VF_PREEMPTION				XE_REG(0x83a4, XE_REG_OPTION_MASKED)
-#define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)
-
-#define VF_SCRATCHPAD				XE_REG(0x83a8, XE_REG_OPTION_MASKED)
-#define   XE2_VFG_TED_CREDIT_INTERFACE_DISABLE	REG_BIT(13)
-
-#define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4, XE_REG_OPTION_MASKED)
-#define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)
-
-#define SQCNT1					XE_REG_MCR(0x8718)
-#define XELPMP_SQCNT1				XE_REG(0x8718)
-#define   SQCNT1_PMON_ENABLE			REG_BIT(30)
-#define   SQCNT1_OABPC				REG_BIT(29)
-#define   ENFORCE_RAR				REG_BIT(23)
-
-#define XEHP_SQCM				XE_REG_MCR(0x8724)
-#define   EN_32B_ACCESS				REG_BIT(30)
-
-#define XE2_FLAT_CCS_BASE_RANGE_LOWER		XE_REG_MCR(0x8800)
-#define   XE2_FLAT_CCS_ENABLE			REG_BIT(0)
-#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK	REG_GENMASK(31, 6)
-
-#define XE2_FLAT_CCS_BASE_RANGE_UPPER		XE_REG_MCR(0x8804)
-#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK	REG_GENMASK(7, 0)
-
-#define GSCPSMI_BASE				XE_REG(0x880c)
-
-#define CCCHKNREG1				XE_REG_MCR(0x8828)
-#define   ENCOMPPERFFIX				REG_BIT(18)
-
-/* Fuse readout registers for GT */
-#define XEHP_FUSE4				XE_REG(0x9114)
-#define   CFEG_WMTP_DISABLE			REG_BIT(20)
-#define   CCS_EN_MASK				REG_GENMASK(19, 16)
-#define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
-
-#define	MIRROR_FUSE3				XE_REG(0x9118)
-#define   XE2_NODE_ENABLE_MASK			REG_GENMASK(31, 16)
-#define   L3BANK_PAIR_COUNT			4
-#define   XEHPC_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
-#define   XE2_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
-#define   L3BANK_MASK				REG_GENMASK(3, 0)
-#define   XELP_GT_L3_MODE_MASK			REG_GENMASK(7, 0)
-/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
-#define   MAX_MSLICES				4
-#define   MEML3_EN_MASK				REG_GENMASK(3, 0)
-
-#define MIRROR_FUSE1				XE_REG(0x911c)
-
-#define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */
-#define   XELP_EU_MASK				REG_GENMASK(7, 0)
-#define XELP_GT_SLICE_ENABLE			XE_REG(0x9138)
-#define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
-
-#define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)
-#define   GT_VEBOX_DISABLE_MASK			REG_GENMASK(19, 16)
-#define   GT_VDBOX_DISABLE_MASK			REG_GENMASK(7, 0)
-
-#define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)
-#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)
-#define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)
-#define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
-#define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
-
-#define GDRST					XE_REG(0x941c)
-#define   GRDOM_GUC				REG_BIT(3)
-#define   GRDOM_FULL				REG_BIT(0)
-
-#define MISCCPCTL				XE_REG(0x9424)
-#define   DOP_CLOCK_GATE_RENDER_ENABLE		REG_BIT(1)
-
-#define UNSLCGCTL9430				XE_REG(0x9430)
-#define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)
-
-#define UNSLICE_UNIT_LEVEL_CLKGATE		XE_REG(0x9434)
-#define   VFUNIT_CLKGATE_DIS			REG_BIT(20)
-#define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */
-#define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */
-#define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)
-#define   HSUNIT_CLKGATE_DIS			REG_BIT(8)
-#define   VSUNIT_CLKGATE_DIS			REG_BIT(3)
-
-#define UNSLCGCTL9440				XE_REG(0x9440)
-#define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)
-#define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)
-#define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)
-#define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)
-#define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)
-#define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)
-#define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)
-#define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)
-#define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)
-#define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)
-#define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)
-#define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)
-
-#define UNSLCGCTL9444				XE_REG(0x9444)
-#define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)
-#define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)
-#define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)
-#define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)
-#define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)
-#define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)
-#define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)
-#define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)
-#define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)
-#define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)
-#define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)
-#define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)
-#define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)
-#define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)
-#define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)
-#define   LTCDD_CLKGATE_DIS			REG_BIT(10)
-
-#define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)
-#define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)
-#define   L3_CLKGATE_DIS			REG_BIT(16)
-#define   NODEDSS_CLKGATE_DIS			REG_BIT(12)
-#define   MSCUNIT_CLKGATE_DIS			REG_BIT(10)
-#define   RCCUNIT_CLKGATE_DIS			REG_BIT(7)
-#define   SARBUNIT_CLKGATE_DIS			REG_BIT(5)
-#define   SBEUNIT_CLKGATE_DIS			REG_BIT(4)
-
-#define UNSLICE_UNIT_LEVEL_CLKGATE2		XE_REG(0x94e4)
-#define   VSUNIT_CLKGATE2_DIS			REG_BIT(19)
-
-#define SUBSLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x9524)
-#define   DSS_ROUTER_CLKGATE_DIS		REG_BIT(28)
-#define   GWUNIT_CLKGATE_DIS			REG_BIT(16)
-
-#define SUBSLICE_UNIT_LEVEL_CLKGATE2		XE_REG_MCR(0x9528)
-#define   CPSSUNIT_CLKGATE_DIS			REG_BIT(9)
-
-#define SSMCGCTL9530				XE_REG_MCR(0x9530)
-#define   RTFUNIT_CLKGATE_DIS			REG_BIT(18)
-
-#define DFR_RATIO_EN_AND_CHICKEN		XE_REG_MCR(0x9550)
-#define   DFR_DISABLE				REG_BIT(9)
-
-#define RPNSWREQ				XE_REG(0xa008)
-#define   REQ_RATIO_MASK			REG_GENMASK(31, 23)
-
-#define RP_CONTROL				XE_REG(0xa024)
-#define   RPSWCTL_MASK				REG_GENMASK(10, 9)
-#define   RPSWCTL_ENABLE			REG_FIELD_PREP(RPSWCTL_MASK, 2)
-#define   RPSWCTL_DISABLE			REG_FIELD_PREP(RPSWCTL_MASK, 0)
-#define RC_CONTROL				XE_REG(0xa090)
-#define   RC_CTL_HW_ENABLE			REG_BIT(31)
-#define   RC_CTL_TO_MODE			REG_BIT(28)
-#define   RC_CTL_RC6_ENABLE			REG_BIT(18)
-#define RC_STATE				XE_REG(0xa094)
-#define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)
-#define MEDIA_POWERGATE_IDLE_HYSTERESIS		XE_REG(0xa0c4)
-#define RENDER_POWERGATE_IDLE_HYSTERESIS	XE_REG(0xa0c8)
-
-#define PMINTRMSK				XE_REG(0xa168)
-#define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)
-#define   ARAT_EXPIRED_INTRMSK			REG_BIT(9)
-
-#define FORCEWAKE_GT				XE_REG(0xa188)
-
-#define POWERGATE_ENABLE			XE_REG(0xa210)
-#define   RENDER_POWERGATE_ENABLE		REG_BIT(0)
-#define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)
-#define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
-#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
-
-#define CTC_MODE				XE_REG(0xa26c)
-#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
-#define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
-
-#define FORCEWAKE_RENDER			XE_REG(0xa278)
-#define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)
-#define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
-#define FORCEWAKE_GSC				XE_REG(0xa618)
-
-#define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
-#define   XEHPC_OVRLSCCC			REG_BIT(0)
-
-/* L3 Cache Control */
-#define LNCFCMOCS_REG_COUNT			32
-#define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
-#define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
-#define   L3_UPPER_LKUP_MASK			REG_BIT(23)
-#define   L3_UPPER_GLBGO_MASK			REG_BIT(22)
-#define   L3_UPPER_IDX_CACHEABILITY_MASK	REG_GENMASK(21, 20)
-#define   L3_UPPER_IDX_SCC_MASK			REG_GENMASK(19, 17)
-#define   L3_UPPER_IDX_ESC_MASK			REG_BIT(16)
-#define   L3_LKUP_MASK				REG_BIT(7)
-#define   L3_LKUP(value)			REG_FIELD_PREP(L3_LKUP_MASK, value)
-#define   L3_GLBGO_MASK				REG_BIT(6)
-#define   L3_GLBGO(value)			REG_FIELD_PREP(L3_GLBGO_MASK, value)
-#define   L3_CACHEABILITY_MASK			REG_GENMASK(5, 4)
-#define   L3_CACHEABILITY(value)		REG_FIELD_PREP(L3_CACHEABILITY_MASK, value)
-#define   L3_SCC_MASK				REG_GENMASK(3, 1)
-#define   L3_SCC(value)				REG_FIELD_PREP(L3_SCC_MASK, value)
-#define   L3_ESC_MASK				REG_BIT(0)
-#define   L3_ESC(value)				REG_FIELD_PREP(L3_ESC_MASK, value)
-
-#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
-#define   XEHP_LNESPARE				REG_BIT(19)
-
-#define L3SQCREG3				XE_REG_MCR(0xb108)
-#define   COMPPWOVERFETCHEN			REG_BIT(28)
-
-#define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
-#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
-
-#define XEHP_L3SCQREG7				XE_REG_MCR(0xb188)
-#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
-
-#define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)
-
-#define XE2_GLOBAL_INVAL			XE_REG(0xb404)
-
-#define SCRATCH1LPFC				XE_REG(0xb474)
-#define   EN_L3_RW_CCS_CACHE_FLUSH		REG_BIT(0)
-
-#define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
-
-#define XE2_TDF_CTRL				XE_REG(0xb418)
-#define   TRANSIENT_FLUSH_REQUEST		REG_BIT(0)
-
-#define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)
-#define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
-#define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
-#define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)
-#define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)
-#define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)
-#define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)
-#define   FORCE_MISS_FTLB			REG_BIT(3)
-
-#define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
-#define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
-#define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
-#define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
-
-#define XEHP_GAMCNTRL_CTRL			XE_REG_MCR(0xcf54)
-#define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
-#define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
-
-#define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
-#define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
-
-#define SAMPLER_INSTDONE			XE_REG_MCR(0xe160)
-#define ROW_INSTDONE				XE_REG_MCR(0xe164)
-
-#define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
-#define   ENABLE_SMALLPL			REG_BIT(15)
-#define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
-#define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)
-#define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
-
-#define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
-#define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
-#define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
-
-#define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
-#define   DISABLE_ECC				REG_BIT(5)
-#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
-
-#define ROW_CHICKEN4				XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
-#define   DISABLE_GRF_CLEAR			REG_BIT(13)
-#define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)
-#define   DISABLE_TDL_PUSH			REG_BIT(9)
-#define   DIS_PICK_2ND_EU			REG_BIT(7)
-#define   DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)
-#define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)
-#define   THREAD_EX_ARB_MODE_RR_AFTER_DEP	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
-
-#define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
-#define   XE2_EUPEND_CHK_FLUSH_DIS		REG_BIT(14)
-#define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
-
-#define TDL_TSL_CHICKEN				XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
-#define   STK_ID_RESTRICT			REG_BIT(12)
-#define   SLM_WMTP_RESTORE			REG_BIT(11)
-
-#define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
-#define   UGM_BACKUP_MODE			REG_BIT(13)
-#define   MDQ_ARBITRATION_MODE			REG_BIT(12)
-#define   STALL_DOP_GATING_DISABLE		REG_BIT(5)
-#define   EARLY_EOT_DIS				REG_BIT(1)
-
-#define ROW_CHICKEN2				XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
-#define   DISABLE_READ_SUPPRESSION		REG_BIT(15)
-#define   DISABLE_EARLY_READ			REG_BIT(14)
-#define   ENABLE_LARGE_GRF_MODE			REG_BIT(12)
-#define   PUSH_CONST_DEREF_HOLD_DIS		REG_BIT(8)
-#define   DISABLE_TDL_SVHS_GATING		REG_BIT(1)
-#define   DISABLE_DOP_GATING			REG_BIT(0)
-
-#define RT_CTRL					XE_REG_MCR(0xe530)
-#define   DIS_NULL_QUERY			REG_BIT(10)
-
-#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
-#define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
-
-#define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
-#define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
-#define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
-
-#define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
-#define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
-#define   WR_REQ_CHAINING_DIS			REG_BIT(26)
-#define   TGM_WRITE_EOM_FORCE			REG_BIT(17)
-#define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)
-#define   SEQUENTIAL_ACCESS_UPGRADE_DISABLE	REG_BIT(13)
-
-#define LSC_CHICKEN_BIT_0_UDW			XE_REG_MCR(0xe7c8 + 4)
-#define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
-#define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
-#define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
-#define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
-#define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
-#define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
-#define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
-#define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
-
-#define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
-#define   COMP_CKN_IN				REG_GENMASK(30, 29)
-
-#define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
-#define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
-#define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
-
-/*
- * Total of 4 cslices, where each cslice is in the form:
- *   [0-3]     CCS ID
- *   [4-6]     RSVD
- *   [7]       Disabled
- */
-#define CCS_MODE				XE_REG(0x14804)
-#define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */
-#define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */
-#define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)
-#define   CCS_MODE_CSLICE(cslice, ccs) \
-	((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
-
-#define FORCEWAKE_ACK_GT			XE_REG(0x130044)
-
-/* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */
-#define   FORCEWAKE_KERNEL			0
-#define   FORCEWAKE_MT(bit)			BIT(bit)
-#define   FORCEWAKE_MT_MASK(bit)		BIT((bit) + 16)
-
-#define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)
-#define MTL_MEDIA_MC6				XE_REG(0x138048)
-
-#define GT_CORE_STATUS				XE_REG(0x138060)
-#define   RCN_MASK				REG_GENMASK(2, 0)
-#define   GT_C0					0
-#define   GT_C6					3
-
-#define GT_GFX_RC6_LOCKED			XE_REG(0x138104)
-#define GT_GFX_RC6				XE_REG(0x138108)
-
-#define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
-#define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
-#define   PROCHOT_MASK				REG_BIT(0)
-#define   THERMAL_LIMIT_MASK			REG_BIT(1)
-#define   RATL_MASK				REG_BIT(5)
-#define   VR_THERMALERT_MASK			REG_BIT(6)
-#define   VR_TDC_MASK				REG_BIT(7)
-#define   POWER_LIMIT_4_MASK			REG_BIT(8)
-#define   POWER_LIMIT_1_MASK			REG_BIT(10)
-#define   POWER_LIMIT_2_MASK			REG_BIT(11)
-
-#define GT_PERF_STATUS				XE_REG(0x1381b4)
-#define   VOLTAGE_MASK				REG_GENMASK(10, 0)
-
-/*
- * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
- *       On newer platforms, VFs are using memory-based interrupts instead.
- *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
- */
-
-#define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
-#define   INTR_GSC				REG_BIT(31)
-#define   INTR_GUC				REG_BIT(25)
-#define   INTR_MGUC				REG_BIT(24)
-#define   INTR_BCS8				REG_BIT(23)
-#define   INTR_BCS(x)				REG_BIT(15 - (x))
-#define   INTR_CCS(x)				REG_BIT(4 + (x))
-#define   INTR_RCS0				REG_BIT(0)
-#define   INTR_VECS(x)				REG_BIT(31 - (x))
-#define   INTR_VCS(x)				REG_BIT(x)
-
-#define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030, XE_REG_OPTION_VF)
-#define VCS_VECS_INTR_ENABLE			XE_REG(0x190034, XE_REG_OPTION_VF)
-#define GUC_SG_INTR_ENABLE			XE_REG(0x190038, XE_REG_OPTION_VF)
-#define   ENGINE1_MASK				REG_GENMASK(31, 16)
-#define   ENGINE0_MASK				REG_GENMASK(15, 0)
-#define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c, XE_REG_OPTION_VF)
-#define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044, XE_REG_OPTION_VF)
-#define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048, XE_REG_OPTION_VF)
-
-#define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
-#define   INTR_DATA_VALID			REG_BIT(31)
-#define   INTR_ENGINE_INSTANCE(x)		REG_FIELD_GET(GENMASK(25, 20), x)
-#define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)
-#define   INTR_ENGINE_INTR(x)			REG_FIELD_GET(GENMASK(15, 0), x)
-#define   OTHER_GUC_INSTANCE			0
-#define   OTHER_GSC_HECI2_INSTANCE		3
-#define   OTHER_GSC_INSTANCE			6
-
-#define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
-#define RCS0_RSVD_INTR_MASK			XE_REG(0x190090, XE_REG_OPTION_VF)
-#define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
-#define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
-#define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
-#define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
-#define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
-#define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
-#define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
-#define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4, XE_REG_OPTION_VF)
-#define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)
-#define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)
-#define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)
-#define XEHPC_BCS3_BCS4_INTR_MASK		XE_REG(0x190114)
-#define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)
-#define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)
-#define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
-#define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
-#define   GSC_ER_COMPLETE			REG_BIT(5)
-#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
-#define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
-#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
-
-#endif
diff --git a/rr-cache/904beded4b558cf3bb988f8f0407391cdd760d66/postimage b/rr-cache/904beded4b558cf3bb988f8f0407391cdd760d66/postimage
deleted file mode 100644
index 28b7f95b6c2f..000000000000
--- a/rr-cache/904beded4b558cf3bb988f8f0407391cdd760d66/postimage
+++ /dev/null
@@ -1,893 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#include "xe_wa.h"
-
-#include <drm/drm_managed.h>
-#include <kunit/visibility.h>
-#include <linux/compiler_types.h>
-
-#include <generated/xe_wa_oob.h>
-
-#include "regs/xe_engine_regs.h"
-#include "regs/xe_gt_regs.h"
-#include "regs/xe_regs.h"
-#include "xe_device_types.h"
-#include "xe_force_wake.h"
-#include "xe_gt.h"
-#include "xe_hw_engine_types.h"
-#include "xe_mmio.h"
-#include "xe_platform_types.h"
-#include "xe_rtp.h"
-#include "xe_sriov.h"
-#include "xe_step.h"
-
-/**
- * DOC: Hardware workarounds
- *
- * Hardware workarounds are register programming documented to be executed in
- * the driver that fall outside of the normal programming sequences for a
- * platform. There are some basic categories of workarounds, depending on
- * how/when they are applied:
- *
- * - LRC workarounds: workarounds that touch registers that are
- *   saved/restored to/from the HW context image. The list is emitted (via Load
- *   Register Immediate commands) once when initializing the device and saved in
- *   the default context. That default context is then used on every context
- *   creation to have a "primed golden context", i.e. a context image that
- *   already contains the changes needed to all the registers.
- *
- * - Engine workarounds: the list of these WAs is applied whenever the specific
- *   engine is reset. It's also possible that a set of engine classes share a
- *   common power domain and they are reset together. This happens on some
- *   platforms with render and compute engines. In this case (at least) one of
- *   them need to keeep the workaround programming: the approach taken in the
- *   driver is to tie those workarounds to the first compute/render engine that
- *   is registered.  When executing with GuC submission, engine resets are
- *   outside of kernel driver control, hence the list of registers involved in
- *   written once, on engine initialization, and then passed to GuC, that
- *   saves/restores their values before/after the reset takes place. See
- *   ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
- *
- * - GT workarounds: the list of these WAs is applied whenever these registers
- *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
- *
- * - Register whitelist: some workarounds need to be implemented in userspace,
- *   but need to touch privileged registers. The whitelist in the kernel
- *   instructs the hardware to allow the access to happen. From the kernel side,
- *   this is just a special case of a MMIO workaround (as we write the list of
- *   these to/be-whitelisted registers to some special HW registers).
- *
- * - Workaround batchbuffers: buffers that get executed automatically by the
- *   hardware on every HW context restore. These buffers are created and
- *   programmed in the default context so the hardware always go through those
- *   programming sequences when switching contexts. The support for workaround
- *   batchbuffers is enabled these hardware mechanisms:
- *
- *   #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
- *      context, pointing the hardware to jump to that location when that offset
- *      is reached in the context restore. Workaround batchbuffer in the driver
- *      currently uses this mechanism for all platforms.
- *
- *   #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
- *      pointing the hardware to a buffer to continue executing after the
- *      engine registers are restored in a context restore sequence. This is
- *      currently not used in the driver.
- *
- * - Other/OOB:  There are WAs that, due to their nature, cannot be applied from
- *   a central place. Those are peppered around the rest of the code, as needed.
- *   Workarounds related to the display IP are the main example.
- *
- * .. [1] Technically, some registers are powercontext saved & restored, so they
- *    survive a suspend/resume. In practice, writing them again is not too
- *    costly and simplifies things, so it's the approach taken in the driver.
- *
- * .. note::
- *    Hardware workarounds in xe work the same way as in i915, with the
- *    difference of how they are maintained in the code. In xe it uses the
- *    xe_rtp infrastructure so the workarounds can be kept in tables, following
- *    a more declarative approach rather than procedural.
- */
-
-#undef XE_REG_MCR
-#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
-
-__diag_push();
-__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
-
-static const struct xe_rtp_entry_sr gt_was[] = {
-	{ XE_RTP_NAME("14011060649"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
-		       ENGINE_CLASS(VIDEO_DECODE),
-		       FUNC(xe_rtp_match_even_instance)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("14011059788"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-	  XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
-	},
-	{ XE_RTP_NAME("14015795083"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
-	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
-	},
-
-	/* DG1 */
-
-	{ XE_RTP_NAME("1409420604"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("1408615072"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
-	},
-
-	/* DG2 */
-
-	{ XE_RTP_NAME("22010523718"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
-	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("14011006942"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
-	  XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("14014830051"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
-	},
-	{ XE_RTP_NAME("18018781329"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
-	},
-	{ XE_RTP_NAME("1509235366"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
-			     INVALIDATION_BROADCAST_MODE_DIS |
-			     GLOBAL_INVALIDATION_MODE))
-	},
-
-	/* PVC */
-
-	{ XE_RTP_NAME("18018781329"),
-	  XE_RTP_RULES(PLATFORM(PVC)),
-	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
-	},
-	{ XE_RTP_NAME("16016694945"),
-	  XE_RTP_RULES(PLATFORM(PVC)),
-	  XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
-	},
-
-	/* Xe_LPG */
-
-	{ XE_RTP_NAME("14015795083"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
-	},
-	{ XE_RTP_NAME("14018575942"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
-	  XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
-	},
-	{ XE_RTP_NAME("22016670082"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
-	  XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
-	},
-
-	/* Xe_LPM+ */
-
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(1300),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("22016670082"),
-	  XE_RTP_RULES(MEDIA_VERSION(1300)),
-	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
-	},
-
-	/* Xe2_LPG */
-
-	{ XE_RTP_NAME("16020975621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("14018157293"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
-			 SET(XEHPC_L3CLOS_MASK(1), ~0),
-			 SET(XEHPC_L3CLOS_MASK(2), ~0),
-			 SET(XEHPC_L3CLOS_MASK(3), ~0))
-	},
-
-	/* Xe2_LPM */
-
-	{ XE_RTP_NAME("14017421178"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("14019449301"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-
-	/* Xe2_HPM */
-
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("14020316580"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301)),
-	  XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
-			     VDN_HCP_POWERGATE_ENABLE(0) |
-			     VDN_MFXVDENC_POWERGATE_ENABLE(0) |
-			     VDN_HCP_POWERGATE_ENABLE(2) |
-			     VDN_MFXVDENC_POWERGATE_ENABLE(2))),
-	},
-	{ XE_RTP_NAME("14019449301"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-
-	{}
-};
-
-static const struct xe_rtp_entry_sr engine_was[] = {
-	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
-			     FF_TESSELATION_DOP_GATE_DISABLE))
-	},
-	{ XE_RTP_NAME("1409804808"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200),
-		       ENGINE_CLASS(RENDER),
-		       IS_INTEGRATED),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
-	},
-	{ XE_RTP_NAME("14010229206, 1409085225"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200),
-		       ENGINE_CLASS(RENDER),
-		       IS_INTEGRATED),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
-	},
-	{ XE_RTP_NAME("1606931601"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
-	},
-	{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
-			     FF_DOP_CLOCK_GATE_DISABLE))
-	},
-	{ XE_RTP_NAME("1406941453"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
-	},
-	{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
-			     FFSC_PERCTX_PREEMPT_CTRL))
-	},
-
-	/* TGL */
-
-	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
-	  XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
-			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     RC_SEMA_IDLE_MSG_DISABLE))
-	},
-
-	/* RKL */
-
-	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
-	  XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
-			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     RC_SEMA_IDLE_MSG_DISABLE))
-	},
-
-	/* ADL-P */
-
-	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
-	  XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
-			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     RC_SEMA_IDLE_MSG_DISABLE))
-	},
-
-	/* DG2 */
-
-	{ XE_RTP_NAME("22013037850"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
-			     DISABLE_128B_EVICTION_COMMAND_UDW))
-	},
-	{ XE_RTP_NAME("22014226127"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
-	},
-	{ XE_RTP_NAME("18017747507"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
-			     POLYGON_TRIFAN_LINELOOP_DISABLE))
-	},
-	{ XE_RTP_NAME("22012826095, 22013059131"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
-				   MAXREQS_PER_BANK,
-				   REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
-	},
-	{ XE_RTP_NAME("22013059131"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
-	},
-	{ XE_RTP_NAME("14015227452"),
-	  XE_RTP_RULES(PLATFORM(DG2),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
-	},
-	{ XE_RTP_NAME("18028616096"),
-	  XE_RTP_RULES(PLATFORM(DG2),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
-	},
-	{ XE_RTP_NAME("22015475538"),
-	  XE_RTP_RULES(PLATFORM(DG2),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
-	},
-	{ XE_RTP_NAME("22012654132"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
-			     /*
-			      * Register can't be read back for verification on
-			      * DG2 due to Wa_14012342262
-			      */
-			     .read_mask = 0))
-	},
-	{ XE_RTP_NAME("1509727124"),
-	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
-	},
-	{ XE_RTP_NAME("22012856258"),
-	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
-	},
-	{ XE_RTP_NAME("22010960976, 14013347512"),
-	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
-			     LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
-	},
-	{ XE_RTP_NAME("14015150844"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
-			     XE_RTP_NOCHECK))
-	},
-
-	/* PVC */
-
-	{ XE_RTP_NAME("22014226127"),
-	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
-	},
-	{ XE_RTP_NAME("14015227452"),
-	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
-	},
-	{ XE_RTP_NAME("18020744125"),
-	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
-		       ENGINE_CLASS(COMPUTE)),
-	  XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
-	},
-	{ XE_RTP_NAME("14014999345"),
-	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
-		       GRAPHICS_STEP(B0, C0)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
-	},
-
-	/* Xe_LPG */
-
-	{ XE_RTP_NAME("14017856879"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
-	},
-	{ XE_RTP_NAME("14015150844"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
-			     XE_RTP_NOCHECK))
-	},
-	{ XE_RTP_NAME("14020495402"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
-	},
-
-	/* Xe2_LPG */
-
-	{ XE_RTP_NAME("18032247524"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
-	},
-	{ XE_RTP_NAME("16018712365"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
-	},
-	{ XE_RTP_NAME("14018957109"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
-	},
-	{ XE_RTP_NAME("14020338487"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
-	},
-	{ XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
-	},
-	{ XE_RTP_NAME("14019322943"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
-	},
-	{ XE_RTP_NAME("14018471104"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
-	},
-	{ XE_RTP_NAME("16018737384"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
-	},
-	/*
-	 * These two workarounds are the same, just applying to different
-	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on
-	 * all steppings, disabling these reports has no impact for our
-	 * driver or the GuC, so we go ahead and treat it the same as
-	 * Wa_16021639441 which does apply to all steppings.
-	 */
-	{ XE_RTP_NAME("18032095049, 16021639441"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-	{ XE_RTP_NAME("16018610683"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
-	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
-
-	/* Xe2_HPG */
-
-	{ XE_RTP_NAME("16018712365"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
-	},
-	{ XE_RTP_NAME("16018737384"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
-	},
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-	{ XE_RTP_NAME("14020338487"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
-	},
-	{ XE_RTP_NAME("18032247524"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
-	},
-	{ XE_RTP_NAME("14018471104"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
-	},
-	/*
-	 * Although this workaround isn't required for the RCS, disabling these
-	 * reports has no impact for our driver or the GuC, so we go ahead and
-	 * apply this to all engines for simplicity.
-	 */
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-	{ XE_RTP_NAME("14019811474"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
-	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
-	{ XE_RTP_NAME("14021821874"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
-	},
-
-	/* Xe2_LPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-
-	/* Xe2_HPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-
-	{}
-};
-
-static const struct xe_rtp_entry_sr lrc_was[] = {
-	{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
-			     DISABLE_CPS_AWARE_COLOR_PIPE))
-	},
-	{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-	  XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
-				   PREEMPT_GPGPU_LEVEL_MASK,
-				   PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
-	},
-	{ XE_RTP_NAME("1806527549"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
-	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
-	},
-	{ XE_RTP_NAME("1606376872"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
-	},
-
-	/* DG1 */
-
-	{ XE_RTP_NAME("1409044764"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
-			     DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
-	},
-	{ XE_RTP_NAME("22010493298"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
-			     DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
-	},
-
-	/* DG2 */
-
-	{ XE_RTP_NAME("16013271637"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
-			     MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
-	},
-	{ XE_RTP_NAME("14014947963"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
-				   PREEMPTION_VERTEX_COUNT,
-				   0x4000))
-	},
-	{ XE_RTP_NAME("18018764978"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
-			     SCOREBOARD_STALL_FLUSH_CONTROL))
-	},
-	{ XE_RTP_NAME("18019271663"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-
-	/* PVC */
-
-	{ XE_RTP_NAME("16017236439"),
-	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
-		       FUNC(xe_rtp_match_even_instance)),
-	  XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
-			     BCS_SWCTRL_DISABLE_256B,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE))),
-	},
-
-	/* Xe_LPG */
-
-	{ XE_RTP_NAME("18019271663"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-
-	/* Xe2_LPG */
-
-	{ XE_RTP_NAME("16020518922"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_MODE,
-			     DIS_TE_AUTOSTRIP |
-			     DIS_MESH_PARTIAL_AUTOSTRIP |
-			     DIS_MESH_AUTOSTRIP),
-			 SET(VFLSKPD,
-			     DIS_PARTIAL_AUTOSTRIP |
-			     DIS_AUTOSTRIP))
-	},
-	{ XE_RTP_NAME("14019386621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-	{ XE_RTP_NAME("14020013138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
-	},
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
-	{ XE_RTP_NAME("16020183090"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
-	},
-	{ XE_RTP_NAME("18033852989"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
-	},
-	{ XE_RTP_NAME("14021567978"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
-	},
-	{ XE_RTP_NAME("14020756599"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
-		       MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
-	},
-	{ XE_RTP_NAME("14021490052"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_MODE,
-			     DIS_MESH_PARTIAL_AUTOSTRIP |
-			     DIS_MESH_AUTOSTRIP),
-			 SET(VFLSKPD,
-			     DIS_PARTIAL_AUTOSTRIP |
-			     DIS_AUTOSTRIP))
-	},
-
-	/* Xe2_HPG */
-	{ XE_RTP_NAME("15010599737"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
-	},
-	{ XE_RTP_NAME("14019386621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
-	},
-	{ XE_RTP_NAME("14020756599"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
-	},
-	{ XE_RTP_NAME("14021490052"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_MODE,
-			     DIS_MESH_PARTIAL_AUTOSTRIP |
-			     DIS_MESH_AUTOSTRIP),
-			 SET(VFLSKPD,
-			     DIS_PARTIAL_AUTOSTRIP |
-			     DIS_AUTOSTRIP))
-	},
-
-	{}
-};
-
-static __maybe_unused const struct xe_rtp_entry oob_was[] = {
-#include <generated/xe_wa_oob.c>
-	{}
-};
-
-static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
-
-__diag_pop();
-
-/**
- * xe_wa_process_oob - process OOB workaround table
- * @gt: GT instance to process workarounds for
- *
- * Process OOB workaround table for this platform, marking in @gt the
- * workarounds that are active.
- */
-void xe_wa_process_oob(struct xe_gt *gt)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
-						  ARRAY_SIZE(oob_was));
-	gt->wa_active.oob_initialized = true;
-	xe_rtp_process(&ctx, oob_was);
-}
-
-/**
- * xe_wa_process_gt - process GT workaround table
- * @gt: GT instance to process workarounds for
- *
- * Process GT workaround table for this platform, saving in @gt all the
- * workarounds that need to be applied at the GT level.
- */
-void xe_wa_process_gt(struct xe_gt *gt)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
-						  ARRAY_SIZE(gt_was));
-	xe_rtp_process_to_sr(&ctx, gt_was, &gt->reg_sr);
-}
-EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
-
-/**
- * xe_wa_process_engine - process engine workaround table
- * @hwe: engine instance to process workarounds for
- *
- * Process engine workaround table for this platform, saving in @hwe all the
- * workarounds that need to be applied at the engine level that match this
- * engine.
- */
-void xe_wa_process_engine(struct xe_hw_engine *hwe)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
-						  ARRAY_SIZE(engine_was));
-	xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
-}
-
-/**
- * xe_wa_process_lrc - process context workaround table
- * @hwe: engine instance to process workarounds for
- *
- * Process context workaround table for this platform, saving in @hwe all the
- * workarounds that need to be applied on context restore. These are workarounds
- * touching registers that are part of the HW context image.
- */
-void xe_wa_process_lrc(struct xe_hw_engine *hwe)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
-						  ARRAY_SIZE(lrc_was));
-	xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
-}
-
-/**
- * xe_wa_init - initialize gt with workaround bookkeeping
- * @gt: GT instance to initialize
- *
- * Returns 0 for success, negative error code otherwise.
- */
-int xe_wa_init(struct xe_gt *gt)
-{
-	struct xe_device *xe = gt_to_xe(gt);
-	size_t n_oob, n_lrc, n_engine, n_gt, total;
-	unsigned long *p;
-
-	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
-	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
-	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
-	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
-	total = n_gt + n_engine + n_lrc + n_oob;
-
-	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
-	if (!p)
-		return -ENOMEM;
-
-	gt->wa_active.gt = p;
-	p += n_gt;
-	gt->wa_active.engine = p;
-	p += n_engine;
-	gt->wa_active.lrc = p;
-	p += n_lrc;
-	gt->wa_active.oob = p;
-
-	return 0;
-}
-
-void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
-{
-	size_t idx;
-
-	drm_printf(p, "GT Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
-		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
-
-	drm_printf(p, "\nEngine Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
-		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
-
-	drm_printf(p, "\nLRC Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
-		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
-
-	drm_printf(p, "\nOOB Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
-		if (oob_was[idx].name)
-			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
-}
-
-/*
- * Apply tile (non-GT, non-display) workarounds.  Think very carefully before
- * adding anything to this function; most workarounds should be implemented
- * elsewhere.  The programming here is primarily for sgunit/soc workarounds,
- * which are relatively rare.  Since the registers these workarounds target are
- * outside the GT, they should only need to be applied once at device
- * probe/resume; they will not lose their values on any kind of GT or engine
- * reset.
- *
- * TODO:  We may want to move this over to xe_rtp in the future once we have
- * enough workarounds to justify the work.
- */
-void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
-{
-	struct xe_gt *mmio = tile->primary_gt;
-
-	if (IS_SRIOV_VF(tile->xe))
-		return;
-
-	if (XE_WA(mmio, 22010954014))
-		xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
-}
diff --git a/rr-cache/904beded4b558cf3bb988f8f0407391cdd760d66/preimage b/rr-cache/904beded4b558cf3bb988f8f0407391cdd760d66/preimage
deleted file mode 100644
index f7005437f27d..000000000000
--- a/rr-cache/904beded4b558cf3bb988f8f0407391cdd760d66/preimage
+++ /dev/null
@@ -1,906 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright © 2022 Intel Corporation
- */
-
-#include "xe_wa.h"
-
-#include <drm/drm_managed.h>
-#include <kunit/visibility.h>
-#include <linux/compiler_types.h>
-
-#include <generated/xe_wa_oob.h>
-
-#include "regs/xe_engine_regs.h"
-#include "regs/xe_gt_regs.h"
-#include "regs/xe_regs.h"
-#include "xe_device_types.h"
-#include "xe_force_wake.h"
-#include "xe_gt.h"
-#include "xe_hw_engine_types.h"
-#include "xe_mmio.h"
-#include "xe_platform_types.h"
-#include "xe_rtp.h"
-#include "xe_sriov.h"
-#include "xe_step.h"
-
-/**
- * DOC: Hardware workarounds
- *
- * Hardware workarounds are register programming documented to be executed in
- * the driver that fall outside of the normal programming sequences for a
- * platform. There are some basic categories of workarounds, depending on
- * how/when they are applied:
- *
- * - LRC workarounds: workarounds that touch registers that are
- *   saved/restored to/from the HW context image. The list is emitted (via Load
- *   Register Immediate commands) once when initializing the device and saved in
- *   the default context. That default context is then used on every context
- *   creation to have a "primed golden context", i.e. a context image that
- *   already contains the changes needed to all the registers.
- *
- * - Engine workarounds: the list of these WAs is applied whenever the specific
- *   engine is reset. It's also possible that a set of engine classes share a
- *   common power domain and they are reset together. This happens on some
- *   platforms with render and compute engines. In this case (at least) one of
- *   them need to keeep the workaround programming: the approach taken in the
- *   driver is to tie those workarounds to the first compute/render engine that
- *   is registered.  When executing with GuC submission, engine resets are
- *   outside of kernel driver control, hence the list of registers involved in
- *   written once, on engine initialization, and then passed to GuC, that
- *   saves/restores their values before/after the reset takes place. See
- *   ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
- *
- * - GT workarounds: the list of these WAs is applied whenever these registers
- *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
- *
- * - Register whitelist: some workarounds need to be implemented in userspace,
- *   but need to touch privileged registers. The whitelist in the kernel
- *   instructs the hardware to allow the access to happen. From the kernel side,
- *   this is just a special case of a MMIO workaround (as we write the list of
- *   these to/be-whitelisted registers to some special HW registers).
- *
- * - Workaround batchbuffers: buffers that get executed automatically by the
- *   hardware on every HW context restore. These buffers are created and
- *   programmed in the default context so the hardware always go through those
- *   programming sequences when switching contexts. The support for workaround
- *   batchbuffers is enabled these hardware mechanisms:
- *
- *   #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
- *      context, pointing the hardware to jump to that location when that offset
- *      is reached in the context restore. Workaround batchbuffer in the driver
- *      currently uses this mechanism for all platforms.
- *
- *   #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
- *      pointing the hardware to a buffer to continue executing after the
- *      engine registers are restored in a context restore sequence. This is
- *      currently not used in the driver.
- *
- * - Other/OOB:  There are WAs that, due to their nature, cannot be applied from
- *   a central place. Those are peppered around the rest of the code, as needed.
- *   Workarounds related to the display IP are the main example.
- *
- * .. [1] Technically, some registers are powercontext saved & restored, so they
- *    survive a suspend/resume. In practice, writing them again is not too
- *    costly and simplifies things, so it's the approach taken in the driver.
- *
- * .. note::
- *    Hardware workarounds in xe work the same way as in i915, with the
- *    difference of how they are maintained in the code. In xe it uses the
- *    xe_rtp infrastructure so the workarounds can be kept in tables, following
- *    a more declarative approach rather than procedural.
- */
-
-#undef XE_REG_MCR
-#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
-
-__diag_push();
-__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
-
-static const struct xe_rtp_entry_sr gt_was[] = {
-	{ XE_RTP_NAME("14011060649"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
-		       ENGINE_CLASS(VIDEO_DECODE),
-		       FUNC(xe_rtp_match_even_instance)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("14011059788"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-	  XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
-	},
-	{ XE_RTP_NAME("14015795083"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
-	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
-	},
-
-	/* DG1 */
-
-	{ XE_RTP_NAME("1409420604"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("1408615072"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
-	},
-
-	/* DG2 */
-
-	{ XE_RTP_NAME("22010523718"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
-	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("14011006942"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
-	  XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("14014830051"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
-	},
-	{ XE_RTP_NAME("18018781329"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
-	},
-	{ XE_RTP_NAME("1509235366"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
-			     INVALIDATION_BROADCAST_MODE_DIS |
-			     GLOBAL_INVALIDATION_MODE))
-	},
-
-	/* PVC */
-
-	{ XE_RTP_NAME("18018781329"),
-	  XE_RTP_RULES(PLATFORM(PVC)),
-	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
-			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
-	},
-	{ XE_RTP_NAME("16016694945"),
-	  XE_RTP_RULES(PLATFORM(PVC)),
-	  XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
-	},
-
-	/* Xe_LPG */
-
-	{ XE_RTP_NAME("14015795083"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
-	},
-	{ XE_RTP_NAME("14018575942"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
-	  XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
-	},
-	{ XE_RTP_NAME("22016670082"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
-	  XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
-	},
-
-	/* Xe_LPM+ */
-
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(1300),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("22016670082"),
-	  XE_RTP_RULES(MEDIA_VERSION(1300)),
-	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
-	},
-
-	/* Xe2_LPG */
-
-	{ XE_RTP_NAME("16020975621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
-	},
-	{ XE_RTP_NAME("14018157293"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
-	  XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
-			 SET(XEHPC_L3CLOS_MASK(1), ~0),
-			 SET(XEHPC_L3CLOS_MASK(2), ~0),
-			 SET(XEHPC_L3CLOS_MASK(3), ~0))
-	},
-
-	/* Xe2_LPM */
-
-	{ XE_RTP_NAME("14017421178"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("14019449301"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-
-	/* Xe2_HPM */
-
-	{ XE_RTP_NAME("16021867713"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301),
-		       ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-	{ XE_RTP_NAME("14020316580"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301)),
-	  XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
-			     VDN_HCP_POWERGATE_ENABLE(0) |
-			     VDN_MFXVDENC_POWERGATE_ENABLE(0) |
-			     VDN_HCP_POWERGATE_ENABLE(2) |
-			     VDN_MFXVDENC_POWERGATE_ENABLE(2))),
-	},
-	{ XE_RTP_NAME("14019449301"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
-	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
-	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
-	},
-
-	{}
-};
-
-static const struct xe_rtp_entry_sr engine_was[] = {
-	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
-			     FF_TESSELATION_DOP_GATE_DISABLE))
-	},
-	{ XE_RTP_NAME("1409804808"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200),
-		       ENGINE_CLASS(RENDER),
-		       IS_INTEGRATED),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
-	},
-	{ XE_RTP_NAME("14010229206, 1409085225"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200),
-		       ENGINE_CLASS(RENDER),
-		       IS_INTEGRATED),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
-	},
-	{ XE_RTP_NAME("1606931601"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
-	},
-	{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
-			     FF_DOP_CLOCK_GATE_DISABLE))
-	},
-	{ XE_RTP_NAME("1406941453"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
-	},
-	{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
-			     FFSC_PERCTX_PREEMPT_CTRL))
-	},
-
-	/* TGL */
-
-	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
-	  XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
-			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     RC_SEMA_IDLE_MSG_DISABLE))
-	},
-
-	/* RKL */
-
-	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
-	  XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
-			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     RC_SEMA_IDLE_MSG_DISABLE))
-	},
-
-	/* ADL-P */
-
-	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
-	  XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
-			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     RC_SEMA_IDLE_MSG_DISABLE))
-	},
-
-	/* DG2 */
-
-	{ XE_RTP_NAME("22013037850"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
-			     DISABLE_128B_EVICTION_COMMAND_UDW))
-	},
-	{ XE_RTP_NAME("22014226127"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
-	},
-	{ XE_RTP_NAME("18017747507"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
-			     POLYGON_TRIFAN_LINELOOP_DISABLE))
-	},
-	{ XE_RTP_NAME("22012826095, 22013059131"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
-				   MAXREQS_PER_BANK,
-				   REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
-	},
-	{ XE_RTP_NAME("22013059131"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
-	},
-	{ XE_RTP_NAME("14015227452"),
-	  XE_RTP_RULES(PLATFORM(DG2),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
-	},
-	{ XE_RTP_NAME("18028616096"),
-	  XE_RTP_RULES(PLATFORM(DG2),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
-	},
-	{ XE_RTP_NAME("22015475538"),
-	  XE_RTP_RULES(PLATFORM(DG2),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
-	},
-	{ XE_RTP_NAME("22012654132"),
-	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
-			     /*
-			      * Register can't be read back for verification on
-			      * DG2 due to Wa_14012342262
-			      */
-			     .read_mask = 0))
-	},
-	{ XE_RTP_NAME("1509727124"),
-	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
-	},
-	{ XE_RTP_NAME("22012856258"),
-	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
-	},
-	{ XE_RTP_NAME("22010960976, 14013347512"),
-	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
-			     LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
-	},
-	{ XE_RTP_NAME("14015150844"),
-	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
-			     XE_RTP_NOCHECK))
-	},
-
-	/* PVC */
-
-	{ XE_RTP_NAME("22014226127"),
-	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
-	},
-	{ XE_RTP_NAME("14015227452"),
-	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
-	},
-	{ XE_RTP_NAME("18020744125"),
-	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
-		       ENGINE_CLASS(COMPUTE)),
-	  XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
-	},
-	{ XE_RTP_NAME("14014999345"),
-	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
-		       GRAPHICS_STEP(B0, C0)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
-	},
-
-	/* Xe_LPG */
-
-	{ XE_RTP_NAME("14017856879"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
-	},
-	{ XE_RTP_NAME("14015150844"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
-			     XE_RTP_NOCHECK))
-	},
-	{ XE_RTP_NAME("14020495402"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
-	},
-
-	/* Xe2_LPG */
-
-	{ XE_RTP_NAME("18032247524"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
-	},
-	{ XE_RTP_NAME("16018712365"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
-	},
-	{ XE_RTP_NAME("14018957109"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
-	},
-	{ XE_RTP_NAME("14020338487"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
-	},
-	{ XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
-	},
-	{ XE_RTP_NAME("14019322943"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
-	},
-	{ XE_RTP_NAME("14018471104"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
-	},
-	{ XE_RTP_NAME("16018737384"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
-	},
-	/*
-	 * These two workarounds are the same, just applying to different
-	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on
-	 * all steppings, disabling these reports has no impact for our
-	 * driver or the GuC, so we go ahead and treat it the same as
-	 * Wa_16021639441 which does apply to all steppings.
-	 */
-	{ XE_RTP_NAME("18032095049, 16021639441"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-	{ XE_RTP_NAME("16018610683"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
-	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
-
-	/* Xe2_HPG */
-
-	{ XE_RTP_NAME("16018712365"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
-	},
-	{ XE_RTP_NAME("16018737384"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
-	},
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-	{ XE_RTP_NAME("14020338487"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
-	},
-	{ XE_RTP_NAME("18032247524"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
-	},
-	{ XE_RTP_NAME("14018471104"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
-	},
-	/*
-	 * Although this workaround isn't required for the RCS, disabling these
-	 * reports has no impact for our driver or the GuC, so we go ahead and
-	 * apply this to all engines for simplicity.
-	 */
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-	{ XE_RTP_NAME("14019811474"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
-		       FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
-	},
-	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
-	},
-	{ XE_RTP_NAME("14021821874"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)),
-	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
-	},
-<<<<<<<
-=======
-
-	/* Xe2_LPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
->>>>>>>
-
-	/* Xe2_LPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(2000)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-
-	/* Xe2_HPM */
-
-	{ XE_RTP_NAME("16021639441"),
-	  XE_RTP_RULES(MEDIA_VERSION(1301)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
-			     GHWSP_CSB_REPORT_DIS |
-			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-	},
-
-	{}
-};
-
-static const struct xe_rtp_entry_sr lrc_was[] = {
-	{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
-			     DISABLE_CPS_AWARE_COLOR_PIPE))
-	},
-	{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-	  XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
-				   PREEMPT_GPGPU_LEVEL_MASK,
-				   PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
-	},
-	{ XE_RTP_NAME("1806527549"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
-	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
-	},
-	{ XE_RTP_NAME("1606376872"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
-	},
-
-	/* DG1 */
-
-	{ XE_RTP_NAME("1409044764"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
-			     DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
-	},
-	{ XE_RTP_NAME("22010493298"),
-	  XE_RTP_RULES(PLATFORM(DG1)),
-	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
-			     DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
-	},
-
-	/* DG2 */
-
-	{ XE_RTP_NAME("16013271637"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
-			     MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
-	},
-	{ XE_RTP_NAME("14014947963"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
-				   PREEMPTION_VERTEX_COUNT,
-				   0x4000))
-	},
-	{ XE_RTP_NAME("18018764978"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
-			     SCOREBOARD_STALL_FLUSH_CONTROL))
-	},
-	{ XE_RTP_NAME("18019271663"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(PLATFORM(DG2)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-
-	/* PVC */
-
-	{ XE_RTP_NAME("16017236439"),
-	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
-		       FUNC(xe_rtp_match_even_instance)),
-	  XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
-			     BCS_SWCTRL_DISABLE_256B,
-			     XE_RTP_ACTION_FLAG(ENGINE_BASE))),
-	},
-
-	/* Xe_LPG */
-
-	{ XE_RTP_NAME("18019271663"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
-	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-
-	/* Xe2_LPG */
-
-	{ XE_RTP_NAME("16020518922"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_MODE,
-			     DIS_TE_AUTOSTRIP |
-			     DIS_MESH_PARTIAL_AUTOSTRIP |
-			     DIS_MESH_AUTOSTRIP),
-			 SET(VFLSKPD,
-			     DIS_PARTIAL_AUTOSTRIP |
-			     DIS_AUTOSTRIP))
-	},
-	{ XE_RTP_NAME("14019386621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
-	{ XE_RTP_NAME("14020013138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
-	},
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
-	{ XE_RTP_NAME("16020183090"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
-	},
-	{ XE_RTP_NAME("18033852989"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
-	},
-	{ XE_RTP_NAME("14021567978"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
-		       ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
-	},
-	{ XE_RTP_NAME("14020756599"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
-		       MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
-	},
-	{ XE_RTP_NAME("14021490052"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_MODE,
-			     DIS_MESH_PARTIAL_AUTOSTRIP |
-			     DIS_MESH_AUTOSTRIP),
-			 SET(VFLSKPD,
-			     DIS_PARTIAL_AUTOSTRIP |
-			     DIS_AUTOSTRIP))
-	},
-
-	/* Xe2_HPG */
-	{ XE_RTP_NAME("15010599737"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
-	},
-	{ XE_RTP_NAME("14019386621"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
-	},
-	{ XE_RTP_NAME("14020756599"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
-	},
-	{ XE_RTP_NAME("14021490052"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(FF_MODE,
-			     DIS_MESH_PARTIAL_AUTOSTRIP |
-			     DIS_MESH_AUTOSTRIP),
-			 SET(VFLSKPD,
-			     DIS_PARTIAL_AUTOSTRIP |
-			     DIS_AUTOSTRIP))
-	},
-
-	{}
-};
-
-static __maybe_unused const struct xe_rtp_entry oob_was[] = {
-#include <generated/xe_wa_oob.c>
-	{}
-};
-
-static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
-
-__diag_pop();
-
-/**
- * xe_wa_process_oob - process OOB workaround table
- * @gt: GT instance to process workarounds for
- *
- * Process OOB workaround table for this platform, marking in @gt the
- * workarounds that are active.
- */
-void xe_wa_process_oob(struct xe_gt *gt)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
-						  ARRAY_SIZE(oob_was));
-	gt->wa_active.oob_initialized = true;
-	xe_rtp_process(&ctx, oob_was);
-}
-
-/**
- * xe_wa_process_gt - process GT workaround table
- * @gt: GT instance to process workarounds for
- *
- * Process GT workaround table for this platform, saving in @gt all the
- * workarounds that need to be applied at the GT level.
- */
-void xe_wa_process_gt(struct xe_gt *gt)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
-						  ARRAY_SIZE(gt_was));
-	xe_rtp_process_to_sr(&ctx, gt_was, &gt->reg_sr);
-}
-EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
-
-/**
- * xe_wa_process_engine - process engine workaround table
- * @hwe: engine instance to process workarounds for
- *
- * Process engine workaround table for this platform, saving in @hwe all the
- * workarounds that need to be applied at the engine level that match this
- * engine.
- */
-void xe_wa_process_engine(struct xe_hw_engine *hwe)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
-						  ARRAY_SIZE(engine_was));
-	xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
-}
-
-/**
- * xe_wa_process_lrc - process context workaround table
- * @hwe: engine instance to process workarounds for
- *
- * Process context workaround table for this platform, saving in @hwe all the
- * workarounds that need to be applied on context restore. These are workarounds
- * touching registers that are part of the HW context image.
- */
-void xe_wa_process_lrc(struct xe_hw_engine *hwe)
-{
-	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-
-	xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
-						  ARRAY_SIZE(lrc_was));
-	xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
-}
-
-/**
- * xe_wa_init - initialize gt with workaround bookkeeping
- * @gt: GT instance to initialize
- *
- * Returns 0 for success, negative error code otherwise.
- */
-int xe_wa_init(struct xe_gt *gt)
-{
-	struct xe_device *xe = gt_to_xe(gt);
-	size_t n_oob, n_lrc, n_engine, n_gt, total;
-	unsigned long *p;
-
-	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
-	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
-	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
-	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
-	total = n_gt + n_engine + n_lrc + n_oob;
-
-	p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
-	if (!p)
-		return -ENOMEM;
-
-	gt->wa_active.gt = p;
-	p += n_gt;
-	gt->wa_active.engine = p;
-	p += n_engine;
-	gt->wa_active.lrc = p;
-	p += n_lrc;
-	gt->wa_active.oob = p;
-
-	return 0;
-}
-
-void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
-{
-	size_t idx;
-
-	drm_printf(p, "GT Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
-		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
-
-	drm_printf(p, "\nEngine Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
-		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
-
-	drm_printf(p, "\nLRC Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
-		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
-
-	drm_printf(p, "\nOOB Workarounds\n");
-	for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
-		if (oob_was[idx].name)
-			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
-}
-
-/*
- * Apply tile (non-GT, non-display) workarounds.  Think very carefully before
- * adding anything to this function; most workarounds should be implemented
- * elsewhere.  The programming here is primarily for sgunit/soc workarounds,
- * which are relatively rare.  Since the registers these workarounds target are
- * outside the GT, they should only need to be applied once at device
- * probe/resume; they will not lose their values on any kind of GT or engine
- * reset.
- *
- * TODO:  We may want to move this over to xe_rtp in the future once we have
- * enough workarounds to justify the work.
- */
-void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
-{
-	struct xe_gt *mmio = tile->primary_gt;
-
-	if (IS_SRIOV_VF(tile->xe))
-		return;
-
-	if (XE_WA(mmio, 22010954014))
-		xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
-}