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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2020 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
*/
&esdhc {
status = "okay";
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0x5 0x80000000 0x08000000
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
cpld@3,0 {
reg = <0x3 0x0 0x10000>;
compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
};
};
&i2c0 {
status = "okay";
pca9547@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
idle-state = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
/* IRQ_RTC_B -> IRQ06, active low */
interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&i2c1 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
&dspi {
status = "okay";
dflash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
};
&qspi {
status = "okay";
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
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