From 1261a6626a08071b7c9fa3025deb569c91eb55ae Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Thu, 2 Feb 2023 20:22:07 +0530 Subject: mailbox: qcom-apcs-ipc: add IPQ5332 APSS clock support IPQ5332 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like other IPQ chipsets. Like IPQ6018, the same controller and driver is used, so utilize IPQ6018 match data for IPQ5332. Signed-off-by: Kathiravan T Reviewed-by: Konrad Dybcio Signed-off-by: Jassi Brar --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mailbox') diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index bd61dacb44ba..6bbf87c6d60b 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -141,6 +141,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) /* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { + { .compatible = "qcom,ipq5332-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, -- cgit v1.2.3