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path: root/include/asm-mips/cpu.h
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2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle1-267/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15[MIPS] modify the MIPS CPU classficationChen, Huacai1-2/+2
Signed-off-by: Huacai Chen <huacai.chen@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Move arch/mips/philips to arch/mips/nxpDaniel Laird1-1/+1
Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Add support for MIPS CMP platform.Ralf Baechle1-3/+4
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29[MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss1-2/+2
This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Convert list of CPU types from #define to enum.Ralf Baechle1-70/+49
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle1-18/+17
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno1-2/+10
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] PMC MSP71xx mips commonMarc St-Jean1-0/+2
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang1-1/+6
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle1-0/+1
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-06[MIPS] Add macros to encode processor revisions.Ralf Baechle1-0/+11
Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Treat R14000 like R10000.Kumba1-1/+3
Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Chris Dearman1-1/+3
Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14[MIPS] Fix CPU type bitmasks for MIPS III, IV and V.Maciej W. Rozycki1-3/+3
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle1-7/+10
Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
2006-01-10MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle1-1/+3
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle1-10/+7
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add support for SB1A CPU.Andrew Isaacson1-1/+3
Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle1-19/+21
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Move MIPS Technologies processor IDs to where they belong.Maciej W. Rozycki1-2/+7
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov1-1/+3
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle1-0/+4
options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the 34K.Ralf Baechle1-1/+3
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle1-0/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup decoding of MIPSxx config registers.Ralf Baechle1-1/+9
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Base Au1200 2.6 support.Pete Popov1-1/+2
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add a few more PrId vendor IDs.Ralf Baechle1-6/+11
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds1-0/+222
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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