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2014-06-12Merge branch 'for-linus' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs Pull vfs updates from Al Viro: "This the bunch that sat in -next + lock_parent() fix. This is the minimal set; there's more pending stuff. In particular, I really hope to get acct.c fixes merged this cycle - we need that to deal sanely with delayed-mntput stuff. In the next pile, hopefully - that series is fairly short and localized (kernel/acct.c, fs/super.c and fs/namespace.c). In this pile: more iov_iter work. Most of prereqs for ->splice_write with sane locking order are there and Kent's dio rewrite would also fit nicely on top of this pile" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (70 commits) lock_parent: don't step on stale ->d_parent of all-but-freed one kill generic_file_splice_write() ceph: switch to iter_file_splice_write() shmem: switch to iter_file_splice_write() nfs: switch to iter_splice_write_file() fs/splice.c: remove unneeded exports ocfs2: switch to iter_file_splice_write() ->splice_write() via ->write_iter() bio_vec-backed iov_iter optimize copy_page_{to,from}_iter() bury generic_file_aio_{read,write} lustre: get rid of messing with iovecs ceph: switch to ->write_iter() ceph_sync_direct_write: stop poking into iov_iter guts ceph_sync_read: stop poking into iov_iter guts new helper: copy_page_from_iter() fuse: switch to ->write_iter() btrfs: switch to ->write_iter() ocfs2: switch to ->write_iter() xfs: switch to ->write_iter() ...
2014-06-12Merge commit '9f12600fe425bc28f0ccba034a77783c09c15af4' into for-linusAl Viro1-0/+6
Backmerge of dcache.c changes from mainline. It's that, or complete rebase... Conflicts: fs/splice.c Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2014-05-28mtd: gpmi: add gpmi support for imx6sxHuang Shijie4-15/+28
The gpmi's IP for imx6sx is nearly the same as the gpmi's IP for imx6q, except the following two new features: (1) the new BCH contoller has 62-BIT correcting ECC strength (The BCH for imx6q only has 40-BIT ECC strength). (2) add the hardware Randomizer support. This patch does the follow changes: (1) add a new macro GPMI_IS_MX6SX to represent the imx6sx's gpmi. (2) add a new macro GPMI_IS_MX6. We use this macro to initialize the same registers for both imx6sx and imx6q, and so on. (3) add a new gpmi_devdata instance, the gpmi_devdata_imx6sx, for imx6sx. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-28mtd: bf5xx_nand: use the managed version of kzallocHimangi Saraogi1-9/+4
This patch moves data allocated using kzalloc to managed data allocated using devm_kzalloc and cleans now unnecessary kfrees in probe and remove functions. Also, the now unnecessary label out_err_hw_init is done away with and the label out_err_kzalloc is renamed to out_err. The following Coccinelle semantic patch was used for making the change: @platform@ identifier p, probefn, removefn; @@ struct platform_driver p = { .probe = probefn, .remove = removefn, }; @prb@ identifier platform.probefn, pdev; expression e, e1, e2; @@ probefn(struct platform_device *pdev, ...) { <+... - e = kzalloc(e1, e2) + e = devm_kzalloc(&pdev->dev, e1, e2) ... ?-kfree(e); ...+> } @rem depends on prb@ identifier platform.removefn; expression e; @@ removefn(...) { <... - kfree(e); ...> } Signed-off-by: Himangi Saraogi <himangi774@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-28mtd: pxa3xx_nand: make the driver work on big-endian systemsThomas Petazzoni1-2/+2
The pxa3xx_nand driver currently uses __raw_writel() and __raw_readl() to access I/O registers. However, those functions do not do any endianness swapping, which means that they won't work when the CPU runs in big-endian but the I/O registers are little endian, which is the common situation for ARM systems running big endian. Since __raw_writel() and __raw_readl() do not include any memory barriers and the pxa3xx_nand driver can only be compiled for ARM platforms, the closest I/o accessors functions that do endianess swapping are writel_relaxed() and readl_relaxed(). This patch has been verified to work on Armada XP GP: without the patch, the NAND is not detected when the kernel runs big endian while it is properly detected when the kernel runs little endian. With the patch applied, the NAND is properly detected in both situations (little and big endian). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.13+ Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-28mtd: nand: omap: fix omap_calculate_ecc_bch() for-loop errorTed Juan1-5/+5
Fixes: 2c9f2365d1e1d0e318b068f683f18c99515b80f8 mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in omap_calculate_ecc_bch Fixes: 7bcd1dca1d587ad29f9825ba4414620440e8c8da mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch8 in omap_calculate_ecc_bch Cc: <stable@vger.kernel.org> # 3.13.x+ Signed-off-by: Ted Juan <ted.juan@gmail.com> Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-28mtd: nand: r852: correct write_buf loop boundsBrian Norris1-2/+4
The two loops in r852_write_buf() are designed to handle 4-byte-aligned and then 1-byte-aligned portions, respectively. However, there are two issues: (1) The first loop will only terminate if 'len' is a multiple of 4 (2) The second loop will never terminate if it runs at least once Rewrite these loops as they were probably intended. Compile tested only. Issues pointed out by Coverity Scan. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Maxim Levitsky <maximlevitsky@gmail.com>
2014-05-28mtd: nand_bbt: handle error case for nand_create_badblock_pattern()Brian Norris1-2/+6
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-28mtd: nand_bbt: remove unused variableBrian Norris1-4/+1
Set, but unused, variable. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-21mtd: nand: pxa3xx: Use ECC strength and step size devicetree bindingEzequiel Garcia1-2/+15
This commit adds support for the user to specify the ECC strength and step size through the devicetree. We keep the previous behavior, when there is no DT parameter provided. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-21mtd: nand: pxa3xx: Clean pxa_ecc_init() error handlingEzequiel Garcia1-11/+10
Let's make pxa_ecc_init() return a negative errno on error or zero if succesful, which is standard kernel practice. Also, report the selected ECC strength and step size, which is important information. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-21mtd: nand: Warn the user if the selected ECC strength is too weakEzequiel Garcia1-0/+36
This commit makes use of the chip->ecc_strength_ds and chip->ecc_step_ds which contain the datasheet minimum requested ECC strength to produce a noisy warning if the configured ECC strength is weaker. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: nand: omap: add support for BCH16_ECC - NAND driver updatespekon gupta1-0/+94
This patch add support for BCH16 ecc-scheme in OMAP NAND driver, by extending following functions: - omap_enable_hwecc (nand_chip->ecc.hwctl): configure GPMC controller - omap_calculate_ecc_bch (nand_chip->ecc.calculate): fetch ECC signature from GPMC controller - omap_elm_correct_data (nand_chip->ecc.correct): detect and correct ECC errors using ELM (a) BCH16 ecc-scheme can detect and correct 16 bit-flips per 512Bytes of data. (b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy the relation: "OOBsize per page >= 26 * (page-size / 512)" Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20NAND_ECC_SOFT_BCH can support subpage reads tooRon Lee1-2/+10
Signed-off-by: Ron Lee <ron@debian.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: fsl_ifc_nand: Workaround bogus WP on 16-bit NANDJoe Schultz1-1/+4
A workaround was already in place that set the WP bit in the IFC_CSPR0 register after a STATUS command, however it used an 8-bit write method. As a result, the WP bit was never set on 16-bit devices, and these devices would eventually be incorrectly marked as write-protected. This patch checks the chip options for a 16-bit device and uses the appropriate write method to set the WP bit after a STATUS command. Signed-off-by: Joe Schultz <jschultz@xes-inc.com> Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: fsl_ifc_nand: Use void type for IFC bufferAaron Sierra1-7/+9
The IFC buffer is accessed via 8-bit and 16-bit accessors. Changing the 'addr' member of 'struct fsl_ifc_nand_ctrl' from 'u8 __iomem *' to 'void __iomem *' eliminates the need for explicit casts when the 16-bit accessors are used. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: nand: Add support to use nand_base poi databuf as bounce bufferKamal Dasu1-6/+31
nand_base can be passed a kmap()'d buffers from highmem by filesystems like jffs2. This results in failure to map the physical address of the DMA buffer on various contoller driver on different platforms. This change adds a chip option to use preallocated databuf as bounce buffers used in nand_do_read_ops() and nand_do_write_ops(). This allows for specific nand controller driver to set this option as needed. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: eLBC NAND: fix subpage write supportPekon Gupta1-0/+14
As subpage write is enabled by default for all drivers, nand_write_subpage_hwecc causes a crash if the driver did not register ecc->hwctl or ecc->calculate. This behavior was introduced in commit 837a6ba4f3b6d23026674e6af6b6849a4634fff9 "mtd: nand: subpage write support for hardware based ECC schemes". This fixes a crash by emulating subpage write support by padding sub-page data with 0xff on either sides to make it full page compatible. Reported-by: Helmut Schaa <helmut.schaa@googlemail.com> Tested-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Cc: <stable@vger.kernel.org> # 3.10.x+ Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: orion_nand: Make of_device_id array constJingoo Han1-1/+1
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: nand: pxa3xx: Make of_device_id array constJingoo Han1-1/+1
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-20mtd: nand: omap: fix BCHx ecc.correct to return detected bit-flips in ↵pekon gupta1-1/+1
erased-page fixes: commit 62116e5171e00f85a8d53f76e45b84423c89ff34 mtd: nand: omap2: Support for hardware BCH error correction. In omap_elm_correct_data(), if bitflip_count in an erased-page is within the correctable limit (< ecc.strength), then it is not indicated back to the caller ecc->read_page(). This mis-guides upper layers like MTD and UBIFS layer to assume erased-page as perfectly clean and use it for writing even if actual bitflip_count was dangerously high (bitflip_count > mtd->bitflip_threshold). This patch fixes this above issue, by returning 'stats' to caller ecc->read_page() under all scenarios. Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Pekon Gupta <pekon@ti.com> Cc: <stable@vger.kernel.org> # 3.9.x+ Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-05-09mtd: nand: refactor erase_cmd() to return chip statusBrian Norris3-13/+14
The nand_chip::erase_cmd callback previously served a dual purpose; for one, it allowed a per-flash-chip override, so that AG-AND devices could use a different erase command than other NAND. These AND devices were dropped in commit 14c6578683367b1e7af0c3c09e872b45a45183a7 (mtd: nand: remove AG-AND support). On the other hand, some drivers (denali and doc-g4) need to use this sort of callback to implement controller-specific erase operations. To make the latter operation easier for some drivers (e.g., ST's new BCH NAND driver), it helps if the command dispatch and wait functions can be lumped together, rather than called separately. This patch does two things: 1. Pull the call to chip->waitfunc() into chip->erase_cmd(), and return the status from this callback 2. Rename erase_cmd() to just erase(), since this callback does a little more than just send a command Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Lee Jones <lee.jones@linaro.org>
2014-05-06replace checking for ->read/->aio_read presence with check in ->f_modeAl Viro1-2/+2
Since we are about to introduce new methods (read_iter/write_iter), the tests in a bunch of places would have to grow inconveniently. Check once (at open() time) and store results in ->f_mode as FMODE_CAN_READ and FMODE_CAN_WRITE resp. It might end up being a temporary measure - once everything switches from ->aio_{read,write} to ->{read,write}_iter it might make sense to return to open-coded checks. We'll see... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2014-04-30mtd: davinci-nand: disable subpage write for keystone-nandMurali Karicheri1-0/+6
Sub page write doesn't work because of hw issue in controller found on Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which don't seems to have any issue. So add "ti,keysone-nand" compatible to nand driver in order to set NAND_NO_SUBPAGE_WRITE option. Cc: Warner Losh <imp@bsdimp.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-29mtd: nand: fix a typo in a comment lineMasahiro Yamada1-1/+1
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-16mtd: gpmi: add gpmi_devdata{} to simplify the codeHuang Shijie3-40/+46
More and more chips use the GPMI controller, but these chips may use different version of the IPs for GPMI and BCH. Different IPs have different features, such as the BCH's maximum ECC strength: imx23/imx28 -- the BCH's maximum ECC strength is 20 imx6q -- the BCH's maximum ECC strength is 40 imx6sx -- the BCH's maximum ECC strength is 62 This patch does the following things: [1] add a new data structure, gpmi_devdata{}, to store the information for each IP. Besides the IP version, we store the following information: <1> BCH's maximum ECC strength. <2> the maximum chain delay in ns used by the EDO mode. but we may add more information in future. [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids. [3] simplify the code by using the ECC strength from gpmi_devdata, such as gpmi_check_ecc() and legacy_set_geometry(); [4] use the maximum chain delay to initialize the EDO mode, see gpmi_compute_edo_timing(). [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-16mtd: nand: add line feed to pr_errRaphaël Poggi1-1/+1
Add line feed to pr_err. Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15mtd: davinci-nand: disable subpage write for keystone-nandMurali Karicheri1-0/+6
Sub page write doesn't work because of hw issue in controller found on Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which don't seems to have any issue. So add "ti,keysone-nand" compatible to nand driver in order to set NAND_NO_SUBPAGE_WRITE option. Cc: Warner Losh <imp@bsdimp.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15mtd: nand: use the nand_read_subpage index everywhereRon1-2/+1
Now that the index variable is correctly set earlier in this function we can use it in other places that compute the same thing too. Signed-off-by: Ron Lee <ron@debian.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-15mtd: nand: omap: fix compile warning on ‘erased_sector_bitflips’Christian Engelmayer1-1/+1
Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in omap_calculate_ecc_bch) introduced minor compile warning "‘erased_sector_bitflips’ defined but not used [-Wunused-function]" when compiling without CONFIG_MTD_NAND_OMAP_BCH. Move function erased_sector_bitflips() into the same ifdef section as the only caller. Signed-off-by: Christian Engelmayer <cengelma@gmx.at> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-07Merge tag 'for-linus-20140405' of git://git.infradead.org/linux-mtdLinus Torvalds22-407/+527
Pull MTD updates from Brian Norris: - A few SPI NOR ID definitions - Kill the NAND "max pagesize" restriction - Fix some x16 bus-width NAND support - Add NAND JEDEC parameter page support - DT bindings for NAND ECC - GPMI NAND updates (subpage reads) - More OMAP NAND refactoring - New STMicro SPI NOR driver (now in 40 patches!) - A few other random bugfixes * tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd: (120 commits) Fix index regression in nand_read_subpage mtd: diskonchip: mem resource name is not optional mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCH mtd: nand: fix GET/SET_FEATURES address on 16-bit devices mtd: omap2: Use devm_ioremap_resource() mtd: denali_dt: Use devm_ioremap_resource() mtd: devices: elm: update DRIVER_NAME as "omap-elm" mtd: devices: elm: configure parallel channels based on ecc_steps mtd: devices: elm: clean elm_load_syndrome mtd: devices: elm: check for hardware engine's design constraints mtd: st_spi_fsm: Succinctly reorganise .remove() mtd: st_spi_fsm: Allow loop to run at least once before giving up CPU mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M" mtd: st_spi_fsm: Avoid duplicating MTD core code mtd: st_spi_fsm: Remove useless consts from function arguments mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitions mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-back mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-back mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-back ...
2014-04-05Merge tag 'drivers-3.15' of ↵Linus Torvalds1-22/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
2014-04-04Fix index regression in nand_read_subpageRon1-3/+2
Commit 7351d3a5dbf42ba3299af71db3296be447bc1516 added an index variable as part of fixing checkpatch warnings, presumably as a tool to make some long lines shorter, however it only set that index in the case of there being no gaps in eccpos for the fragment being read. Which means the later step of filling ecccode from oob_poi will use the wrong indexing into eccpos in that case. This patch restores the behaviour that existed prior to that change. Signed-off-by: Ron Lee <ron@debian.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-01Merge tag 'char-misc-3.15-rc1' of ↵Linus Torvalds2-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver patches from Greg KH: "Here's the big char/misc driver updates for 3.15-rc1. Lots of various things here, including the new mcb driver subsystem. All of these have been in linux-next for a while" * tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (118 commits) extcon: Move OF helper function to extcon core and change function name extcon: of: Remove unnecessary function call by using the name of device_node extcon: gpio: Use SIMPLE_DEV_PM_OPS macro extcon: palmas: Use SIMPLE_DEV_PM_OPS macro mei: don't use deprecated DEFINE_PCI_DEVICE_TABLE macro mei: amthif: fix checkpatch error mei: client.h fix checkpatch errors mei: use cl_dbg where appropriate mei: fix Unnecessary space after function pointer name mei: report consistently copy_from/to_user failures mei: drop pr_fmt macros mei: make me hw headers private to me hw. mei: fix memory leak of pending write cb objects mei: me: do not reset when less than expected data is received drivers: mcb: Fix build error discovered by 0-day bot cs5535-mfgpt: Simplify dependencies spmi: pm: drop bus-level PM suspend/resume routines spmi: pmic_arb: make selectable on ARCH_QCOM Drivers: hv: vmbus: Increase the limit on the number of pfns we can handle pch_phub: Report error writing MAC back to user ...
2014-03-31mtd: diskonchip: mem resource name is not optionalSasha Levin1-1/+1
Passing a name to request_mem_region() isn't optional and can't just be NULL. Passing NULL causes a NULL ptr deref later in the boot process. Signed-off-by: Sasha Levin <sasha.levin@oracle.com> Tested-by: Alexander Shiyan <shc_work@mail.ru> Cc: <stable@vger.kernel.org> # 3.14 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-26mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCHErico Nunes1-1/+1
Mention to CONFIG_MTD_ECC_BCH in the warning message can be confusing as this doesn't match the exact name of the configuration option. This warning showed up once to me when I was starting to set up BCH. After checking my .config file, it took a moment before realizing it is CONFIG_MTD_NAND_ECC_BCH instead of CONFIG_MTD_ECC_BCH. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: omap2: Use devm_ioremap_resource()Jingoo Han1-20/+3
Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource() because the value is checked by devm_ioremap_resource(). Also, 'unsigned long mem_size' is removed from 'struct omap_nand_info', because the 'mem_size' variable is not necessary anymore. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: denali_dt: Use devm_ioremap_resource()Jingoo Han1-31/+8
Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource_byname() because the value is checked by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: devices: elm: check for hardware engine's design constraintsPekon Gupta1-3/+6
ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC errors. This patch adds the following checks for ELM hardware engine: - ELM internal buffers are of 1K, so it cannot process data with ecc-step-size > 1K. - ELM engine can execute upto maximum of 8 threads in parallel, so in *page-mode* (when complete page is processed in single iteration), ELM cannot support ecc-steps > 8. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20Merge branches 'pm-qos', 'pm-domains' and 'pm-drivers'Rafael J. Wysocki1-1/+1
* pm-qos: PM / QoS: Add type to dev_pm_qos_add_ancestor_request() arguments ACPI / LPSS: Support for device latency tolerance PM QoS ACPI / scan: Add bind/unbind callbacks to struct acpi_scan_handler PM / QoS: Introcuce latency tolerance device PM QoS type PM / QoS: Add no_constraints_value field to struct pm_qos_constraints PM / QoS: Rename device resume latency QoS items * pm-domains: PM / domains: Turn latency warning into debug message * pm-drivers: PM: Add pm_runtime_suspend|resume_force functions PM / runtime: Fetch runtime PM callbacks using a macro
2014-03-20mtd: nand: omap: remove is_elm_present flagPekon Gupta1-3/+0
'is_elm_present' flag is not used anywhere. This check is implicitely taken care while selecting appropriate ecc-scheme via DT or board-file. Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.hwctl: clean omap_enable_hwecc_bch for redundant ECC ↵Pekon Gupta1-13/+10
configs This patch - refactors GPMC configurations based on ecc-scheme - removed dependency on is_elm_present() flag, which is implicitely taken care by selecting appropriate ecc-scheme Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.hwctl: refactor omap_enable_hwecc_bch for ECC related ↵Pekon Gupta1-24/+50
GPMC configs Lots of if..then..else conditions in omap_enable_hwecc_bch() can be avoided if code is refactored based on ecc-scheme. Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.hwctl: rename omap3_enable_hwecc_bch to ↵Pekon Gupta1-8/+7
omap_enable_hwecc_bch This patch - renames omap3_enable_hwecc_bch -> omap_enable_hwecc_bch to keep nomenclature independent of any device family. - using '__maybe_unused' instead of `ifdef based conditional compilation to suppress warning for un-used functions Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch8 in ↵Pekon Gupta1-49/+10
omap_calculate_ecc_bch merge omap3_calculate_ecc_bch8() into omap_calculate_ecc_bch() so that common callback can be used for both OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +---------------------+-------------------------------------------------------+ |ecc-scheme | nand_chip->calculate() after this patch | +---------------------+-------------------------------------------------------+ |HAM1_ECC | omap_calculate_ecc() | +---------------------+-------------------------------------------------------+ |BCH4_HW_DETECTION_SW | omap_calculate_ecc_bch() | |BCH4_HW | omap_calculate_ecc_bch() | |BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() -> omap_calculate_ecc_bch()| |BCH8_HW | omap_calculate_ecc_bch() | +---------------------+-------------------------------------------------------+ Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in ↵Pekon Gupta1-41/+10
omap_calculate_ecc_bch merges omap3_calculate_ecc_bch4() into omap_calculate_ecc_bch() so that common callback can be used for both OMAP_ECC_BCH4_CODE_HW and OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ecc-schemes +---------------------+-------------------------------------------------------+ |ecc-scheme | nand_chip->calculate() after this patch | +---------------------+-------------------------------------------------------+ |HAM1_ECC | omap_calculate_ecc() | +---------------------+-------------------------------------------------------+ |BCH4_HW_DETECTION_SW | omap3_calculate_ecc_bch4() -> omap_calculate_ecc_bch()| |BCH4_HW | omap_calculate_ecc_bch() | |BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() | |BCH8_HW | omap_calculate_ecc_bch() | +---------------------+-------------------------------------------------------+ Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: refactor omap_calculate_ecc_bch for BCHx_HW ↵Pekon Gupta1-33/+35
ecc-scheme OMAP NAND driver supports multiple flavours of BCH4 and BCH8 ECC algorithms. +------+------------------------------------+---------------+---------------+ | Algo | ECC scheme |ECC calculation|Error detection| +------+------------------------------------+---------------+---------------+ | |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | | BCH4 |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) | +------+------------------------------------+---------------+---------------+ | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | | BCH8 |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | +------+------------------------------------+---------------+---------------+ This patch refactors omap_calculate_ecc_bch() so that - separate out ecc-scheme specific code so that common-code can be reused between different implementations of same ECC algorithm. - new ecc-schemes can be added with ease in future. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.calculate: rename omap3_calculate_ecc_bch to ↵Pekon Gupta1-5/+5
omap_calculate_ecc_bch rename omap3_calculate_ecc_bch -> omap_calculate_ecc_bch to keep nomenclature independent of any device family. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.correct: omap_elm_correct_data: fix programmed-page ↵Pekon Gupta1-10/+19
bit-flip correction logic This patch updates following checks when bit-flips are detected by ELM: - Do not evaluate bit-flips when un-correctable bit-flips is reported by ELM, because as per [1] when ELM reports an un-correctable bit-flips, 'number of error' field in its ELM_LOCATION_STATUS register is also invalid. - Return with error-code '-EBADMSG' on detection of un-correctable bit-flip. - Return with error-code '-EBADMSG' when bit-flips position is outside current Sector and OOB area. [1] ELM IP spec Table-25 ELM_LOCATION_STATUS Register. ELM_LOCATION_STATUS[8] = ECC_CORRECTABLE: Error location process exit status 0x0: ECC error location process failed. Number of errors and error locations are invalid. 0x1: all errors were successfully located. Number of errors and error locations are valid. Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: nand: omap: ecc.correct: omap_elm_correct_data: cleanup for future ↵Pekon Gupta1-25/+13
enhancements Current omap_elm_correct_data() code is not scalable for future ecc-schemes due to presence of tweaks and hard-coded macros for BCH4_ECC and BCH8_ECC ecc-schemes at multiple places. This patch: - replaces 'ecc_opt' with '(info->nand.ecc.strength == BCH8_MAX_ERROR) used to differentiate between BCH8_HW and BCH4_SW - replaces macros (defining magic number for specific ecc-scheme) with generic variables - removes dependency on macros defined in elm.h (like BCHx_ECC_OOB_BYTES) Tested-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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