drm/drm-misc - Kernel DRM miscellaneous fixes and cross-tree changes

Age	Commit message (Collapse)	Author	Files	Lines
2016-05-04	irqchip: Add Layerscape SCFG MSI controller support	Minghuan Lian	1	-0/+240
	Some kind of Freescale Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>