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path: root/drivers/clk/socfpga
AgeCommit message (Expand)AuthorFilesLines
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner1-10/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner3-36/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner3-33/+3
2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13Thomas Gleixner1-13/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd3-0/+3
2019-03-08Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', ...Stephen Boyd3-9/+15
2019-01-24clk: socfpga: Don't have get_parent for single parent opsStephen Boyd1-9/+13
2019-01-15clk: socfpga: stratix10: fix naming convention for the fixed-clocksDinh Nguyen1-10/+10
2019-01-11clk: socfpga: stratix10: fix rate calculation for pll clocksDinh Nguyen1-1/+1
2018-12-28clk: socfpga: fix refcount leakYangtao Li2-0/+2
2018-07-06clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen1-1/+1
2018-07-06clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen1-1/+6
2018-05-15clk: socfpga: stratix10: suppress unbinding platform's clock driverDinh Nguyen1-0/+1
2018-05-15clk: socfpga: stratix10: use platform driver APIsDinh Nguyen1-22/+17
2018-04-06clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen7-5/+853
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
2017-06-19clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen2-1/+4
2016-02-22clk: socfpga: allow for multiple parents on Arria10 periph clocksDinh Nguyen2-9/+4
2016-02-08clk: socfpga: fix __init annotationArnd Bergmann1-1/+1
2015-08-24clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen2-4/+15
2015-07-28clk: socfpga: switch to GENMASK()Andy Shevchenko5-5/+4
2015-07-20clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd7-7/+6
2015-06-09clk: socfpga: remove a stray tabDan Carpenter1-1/+1
2015-06-05clk: socfpga: make use of of_clk_parent_fill helper functionDinh Nguyen2-11/+2
2015-05-21clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen6-1/+469
2015-05-21clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen2-5/+5
2015-05-14clk: socfpga: Silence sparse warningStephen Boyd1-1/+1
2015-05-14clk: socfpga: Silence sparse warningStephen Boyd1-1/+1
2014-05-12Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-...Mike Turquette3-4/+23
2014-05-12clk: socfpga: add divider registers to the main pll outputsDinh Nguyen3-4/+23
2014-04-30clk: socfpga: fix clock driver for 3.15Dinh Nguyen2-20/+10
2014-03-18clk: socfpga: Fix section mismatch warningDinh Nguyen1-1/+1
2014-02-26clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen1-4/+22
2014-02-26clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen1-3/+5
2014-02-18clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"Dinh Nguyen1-0/+68
2014-02-18clk: socfpga: split clk codeSteffen Trumtrar6-306/+462
2014-02-18clk: socfpga: fix define typoSteffen Trumtrar1-3/+3
2014-02-18clk: socfpga: remove unused fieldSteffen Trumtrar1-1/+0
2014-02-18clk: socfpga: Remove socfpga_init_clocksDinh Nguyen1-10/+0
2014-02-18clk: socfpga: Look for the GPIO_DB_CLK by its offsetDinh Nguyen1-2/+3
2014-02-18clk: socfpga: Map the clk manager base address in the clock driverDinh Nguyen1-4/+16
2013-12-19clk: socfpga: Use NULL instead of 0Sachin Kamat1-1/+1
2013-11-27clk: socfpga: Remove check for "reg" property in socfpga_clk_initDinh Nguyen1-3/+1
2013-10-07clk: socfpga: Fix incorrect sdmmc clock nameDinh Nguyen1-1/+1
2013-06-11ARM: socfpga: Add support to gate peripheral clocksDinh Nguyen1-9/+185
2013-04-14ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entriesDinh Nguyen1-21/+142
2012-07-19ARM: socfpga: initial support for Altera's SOCFPGA platformDinh Nguyen2-0/+52
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