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Kernel DRM miscellaneous fixes and cross-tree changes
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arch
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arm64
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include
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asm
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tlbflush.h
Age
Commit message (
Expand
)
Author
Files
Lines
2017-02-01
arm64: Work around Falkor erratum 1009
Christopher Covington
1
-3
/
+15
2016-09-28
arm64: tlbflush.h: add __tlbi() macro
Mark Rutland
1
-8
/
+26
2015-10-07
arm64: tlb: remove redundant barrier from __flush_tlb_pgtable
Will Deacon
1
-1
/
+0
2015-10-07
arm64: tlbflush: remove redundant ASID casts to (unsigned long)
Will Deacon
1
-5
/
+4
2015-10-07
arm64: flush: use local TLB and I-cache invalidation
Will Deacon
1
-0
/
+8
2015-07-28
arm64: Use last level TLBI for user pte changes
Catalin Marinas
1
-5
/
+16
2015-07-28
arm64: Clean up __flush_tlb(_kernel)_range functions
Catalin Marinas
1
-26
/
+21
2015-07-27
arm64: move update_mmu_cache() into asm/pgtable.h
Will Deacon
1
-14
/
+0
2015-06-12
arm64: mm: remove reference to tlb.S from comment block
Vladimir Murzin
1
-2
/
+0
2015-03-14
arm64: Invalidate the TLB corresponding to intermediate page table levels
Catalin Marinas
1
-0
/
+13
2015-02-26
arm64: mm: remove unused functions and variable protoypes
Yingjoe Chen
1
-5
/
+0
2014-07-24
arm64: fix soft lockup due to large tlb flush range
Mark Salter
1
-3
/
+26
2014-07-24
arm64: Fix barriers used for page table modifications
Catalin Marinas
1
-2
/
+3
2014-05-09
arm64: barriers: make use of barrier options with explicit barriers
Will Deacon
1
-7
/
+7
2014-05-09
arm64: mm: Optimise tlb flush logic where we have >4K granule
Steve Capper
1
-5
/
+25
2013-06-14
ARM64: mm: THP support.
Steve Capper
1
-0
/
+2
2012-09-17
arm64: TLB maintenance functionality
Catalin Marinas
1
-0
/
+122