diff options
Diffstat (limited to 'arch/sh/kernel')
47 files changed, 1137 insertions, 865 deletions
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index 2600641a483f..eecad7cbd61e 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -17,5 +17,6 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ obj-$(CONFIG_UBC_WAKEUP) += ubc.o obj-$(CONFIG_SH_ADC) += adc.o +obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o obj-y += irq/ init.o clock.o diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c new file mode 100644 index 000000000000..b78c237ab366 --- /dev/null +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -0,0 +1,62 @@ +#include <linux/clk.h> +#include <linux/compiler.h> +#include <asm/clock.h> + +#ifdef CONFIG_SH_CLK_CPG_LEGACY +static struct clk master_clk = { + .name = "master_clk", + .flags = CLK_ENABLE_ON_INIT, + .rate = CONFIG_SH_PCLK_FREQ, +}; + +static struct clk peripheral_clk = { + .name = "peripheral_clk", + .parent = &master_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static struct clk bus_clk = { + .name = "bus_clk", + .parent = &master_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +static struct clk cpu_clk = { + .name = "cpu_clk", + .parent = &master_clk, + .flags = CLK_ENABLE_ON_INIT, +}; + +/* + * The ordering of these clocks matters, do not change it. + */ +static struct clk *onchip_clocks[] = { + &master_clk, + &peripheral_clk, + &bus_clk, + &cpu_clk, +}; + +int __init __deprecated cpg_clk_init(void) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) { + struct clk *clk = onchip_clocks[i]; + arch_init_clk_ops(&clk->ops, i); + if (clk->ops) + ret |= clk_register(clk); + } + + return ret; +} + +/* + * Placeholder for compatability, until the lazy CPUs do this + * on their own. + */ +int __init __weak arch_clk_init(void) +{ + return cpg_clk_init(); +} +#endif /* CONFIG_SH_CPG_CLK_LEGACY */ diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c index f54769f455b1..aa0fd0893585 100644 --- a/arch/sh/kernel/cpu/clock.c +++ b/arch/sh/kernel/cpu/clock.c @@ -1,15 +1,19 @@ /* * arch/sh/kernel/cpu/clock.c - SuperH clock framework * - * Copyright (C) 2005, 2006, 2007 Paul Mundt + * Copyright (C) 2005 - 2009 Paul Mundt * * This clock framework is derived from the OMAP version by: * - * Copyright (C) 2004 - 2005 Nokia Corporation + * Copyright (C) 2004 - 2008 Nokia Corporation * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> * * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> * + * With clkdev bits: + * + * Copyright (C) 2008 Russell King. + * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -24,141 +28,135 @@ #include <linux/seq_file.h> #include <linux/err.h> #include <linux/platform_device.h> -#include <linux/proc_fs.h> +#include <linux/debugfs.h> +#include <linux/cpufreq.h> #include <asm/clock.h> +#include <asm/machvec.h> static LIST_HEAD(clock_list); static DEFINE_SPINLOCK(clock_lock); static DEFINE_MUTEX(clock_list_sem); -/* - * Each subtype is expected to define the init routines for these clocks, - * as each subtype (or processor family) will have these clocks at the - * very least. These are all provided through the CPG, which even some of - * the more quirky parts (such as ST40, SH4-202, etc.) still have. - * - * The processor-specific code is expected to register any additional - * clock sources that are of interest. - */ -static struct clk master_clk = { - .name = "master_clk", - .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, - .rate = CONFIG_SH_PCLK_FREQ, -}; +void clk_rate_table_build(struct clk *clk, + struct cpufreq_frequency_table *freq_table, + int nr_freqs, + struct clk_div_mult_table *src_table, + unsigned long *bitmap) +{ + unsigned long mult, div; + unsigned long freq; + int i; -static struct clk module_clk = { - .name = "module_clk", - .parent = &master_clk, - .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, -}; + for (i = 0; i < nr_freqs; i++) { + div = 1; + mult = 1; -static struct clk bus_clk = { - .name = "bus_clk", - .parent = &master_clk, - .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, -}; + if (src_table->divisors && i < src_table->nr_divisors) + div = src_table->divisors[i]; -static struct clk cpu_clk = { - .name = "cpu_clk", - .parent = &master_clk, - .flags = CLK_ALWAYS_ENABLED, -}; + if (src_table->multipliers && i < src_table->nr_multipliers) + mult = src_table->multipliers[i]; -/* - * The ordering of these clocks matters, do not change it. - */ -static struct clk *onchip_clocks[] = { - &master_clk, - &module_clk, - &bus_clk, - &cpu_clk, -}; + if (!div || !mult || (bitmap && !test_bit(i, bitmap))) + freq = CPUFREQ_ENTRY_INVALID; + else + freq = clk->parent->rate * mult / div; -static void propagate_rate(struct clk *clk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clock_list, node) { - if (likely(clkp->parent != clk)) - continue; - if (likely(clkp->ops && clkp->ops->recalc)) - clkp->ops->recalc(clkp); - if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) - propagate_rate(clkp); + freq_table[i].index = i; + freq_table[i].frequency = freq; } + + /* Termination entry */ + freq_table[i].index = i; + freq_table[i].frequency = CPUFREQ_TABLE_END; } -static void __clk_init(struct clk *clk) +long clk_rate_table_round(struct clk *clk, + struct cpufreq_frequency_table *freq_table, + unsigned long rate) { - /* - * See if this is the first time we're enabling the clock, some - * clocks that are always enabled still require "special" - * initialization. This is especially true if the clock mode - * changes and the clock needs to hunt for the proper set of - * divisors to use before it can effectively recalc. - */ + unsigned long rate_error, rate_error_prev = ~0UL; + unsigned long rate_best_fit = rate; + unsigned long highest, lowest; + int i; - if (clk->flags & CLK_NEEDS_INIT) { - if (clk->ops && clk->ops->init) - clk->ops->init(clk); + highest = lowest = 0; - clk->flags &= ~CLK_NEEDS_INIT; - } -} + for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { + unsigned long freq = freq_table[i].frequency; -static int __clk_enable(struct clk *clk) -{ - if (!clk) - return -EINVAL; + if (freq == CPUFREQ_ENTRY_INVALID) + continue; - clk->usecount++; + if (freq > highest) + highest = freq; + if (freq < lowest) + lowest = freq; - /* nothing to do if always enabled */ - if (clk->flags & CLK_ALWAYS_ENABLED) - return 0; + rate_error = abs(freq - rate); + if (rate_error < rate_error_prev) { + rate_best_fit = freq; + rate_error_prev = rate_error; + } - if (clk->usecount == 1) { - __clk_init(clk); + if (rate_error == 0) + break; + } - __clk_enable(clk->parent); + if (rate >= highest) + rate_best_fit = highest; + if (rate <= lowest) + rate_best_fit = lowest; - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - } + return rate_best_fit; +} - return 0; +/* Used for clocks that always have same value as the parent clock */ +unsigned long followparent_recalc(struct clk *clk) +{ + return clk->parent ? clk->parent->rate : 0; } -int clk_enable(struct clk *clk) +int clk_reparent(struct clk *child, struct clk *parent) { - unsigned long flags; - int ret; + list_del_init(&child->sibling); + if (parent) + list_add(&child->sibling, &parent->children); + child->parent = parent; - spin_lock_irqsave(&clock_lock, flags); - ret = __clk_enable(clk); - spin_unlock_irqrestore(&clock_lock, flags); + /* now do the debugfs renaming to reattach the child + to the proper parent */ - return ret; + return 0; } -EXPORT_SYMBOL_GPL(clk_enable); -static void __clk_disable(struct clk *clk) +/* Propagate rate to children */ +void propagate_rate(struct clk *tclk) { - if (!clk) - return; + struct clk *clkp; - clk->usecount--; + list_for_each_entry(clkp, &tclk->children, sibling) { + if (clkp->ops && clkp->ops->recalc) + clkp->rate = clkp->ops->recalc(clkp); - WARN_ON(clk->usecount < 0); + propagate_rate(clkp); + } +} - if (clk->flags & CLK_ALWAYS_ENABLED) +static void __clk_disable(struct clk *clk) +{ + if (clk->usecount == 0) { + printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", + clk->name); + WARN_ON(1); return; + } - if (clk->usecount == 0) { + if (!(--clk->usecount)) { if (likely(clk->ops && clk->ops->disable)) clk->ops->disable(clk); - - __clk_disable(clk->parent); + if (likely(clk->parent)) + __clk_disable(clk->parent); } } @@ -166,29 +164,103 @@ void clk_disable(struct clk *clk) { unsigned long flags; + if (!clk) + return; + spin_lock_irqsave(&clock_lock, flags); __clk_disable(clk); spin_unlock_irqrestore(&clock_lock, flags); } EXPORT_SYMBOL_GPL(clk_disable); +static int __clk_enable(struct clk *clk) +{ + int ret = 0; + + if (clk->usecount++ == 0) { + if (clk->parent) { + ret = __clk_enable(clk->parent); + if (unlikely(ret)) + goto err; + } + + if (clk->ops && clk->ops->enable) { + ret = clk->ops->enable(clk); + if (ret) { + if (clk->parent) + __clk_disable(clk->parent); + goto err; + } + } + } + + return ret; +err: + clk->usecount--; + return ret; +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret; + + if (!clk) + return -EINVAL; + + spin_lock_irqsave(&clock_lock, flags); + ret = __clk_enable(clk); + spin_unlock_irqrestore(&clock_lock, flags); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_enable); + +static LIST_HEAD(root_clks); + +/** + * recalculate_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + * Called at init. + */ +void recalculate_root_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &root_clks, sibling) { + if (clkp->ops && clkp->ops->recalc) + clkp->rate = clkp->ops->recalc(clkp); + propagate_rate(clkp); + } +} + int clk_register(struct clk *clk) { + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + /* + * trap out already registered clocks + */ + if (clk->node.next || clk->node.prev) + return 0; + mutex_lock(&clock_list_sem); - list_add(&clk->node, &clock_list); + INIT_LIST_HEAD(&clk->children); clk->usecount = 0; - clk->flags |= CLK_NEEDS_INIT; - mutex_unlock(&clock_list_sem); + if (clk->parent) + list_add(&clk->sibling, &clk->parent->children); + else + list_add(&clk->sibling, &root_clks); - if (clk->flags & CLK_ALWAYS_ENABLED) { - __clk_init(clk); - pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name); - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - pr_debug( "Enabled."); - } + list_add(&clk->node, &clock_list); + if (clk->ops && clk->ops->init) + clk->ops->init(clk); + mutex_unlock(&clock_list_sem); return 0; } @@ -197,11 +269,21 @@ EXPORT_SYMBOL_GPL(clk_register); void clk_unregister(struct clk *clk) { mutex_lock(&clock_list_sem); + list_del(&clk->sibling); list_del(&clk->node); mutex_unlock(&clock_list_sem); } EXPORT_SYMBOL_GPL(clk_unregister); +static void clk_enable_init_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &clock_list, node) + if (clkp->flags & CLK_ENABLE_ON_INIT) + clk_enable(clkp); +} + unsigned long clk_get_rate(struct clk *clk) { return clk->rate; @@ -217,56 +299,59 @@ EXPORT_SYMBOL_GPL(clk_set_rate); int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) { int ret = -EOPNOTSUPP; + unsigned long flags; - if (likely(clk->ops && clk->ops->set_rate)) { - unsigned long flags; + spin_lock_irqsave(&clock_lock, flags); - spin_lock_irqsave(&clock_lock, flags); + if (likely(clk->ops && clk->ops->set_rate)) { ret = clk->ops->set_rate(clk, rate, algo_id); - spin_unlock_irqrestore(&clock_lock, flags); + if (ret != 0) + goto out_unlock; + } else { + clk->rate = rate; + ret = 0; } - if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) - propagate_rate(clk); + if (clk->ops && clk->ops->recalc) + clk->rate = clk->ops->recalc(clk); - return ret; -} -EXPORT_SYMBOL_GPL(clk_set_rate_ex); + propagate_rate(clk); -void clk_recalc_rate(struct clk *clk) -{ - if (likely(clk->ops && clk->ops->recalc)) { - unsigned long flags; - - spin_lock_irqsave(&clock_lock, flags); - clk->ops->recalc(clk); - spin_unlock_irqrestore(&clock_lock, flags); - } +out_unlock: + spin_unlock_irqrestore(&clock_lock, flags); - if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) - propagate_rate(clk); + return ret; } -EXPORT_SYMBOL_GPL(clk_recalc_rate); +EXPORT_SYMBOL_GPL(clk_set_rate_ex); int clk_set_parent(struct clk *clk, struct clk *parent) { + unsigned long flags; int ret = -EINVAL; - struct clk *old; if (!parent || !clk) return ret; + if (clk->parent == parent) + return 0; - old = clk->parent; - if (likely(clk->ops && clk->ops->set_parent)) { - unsigned long flags; - spin_lock_irqsave(&clock_lock, flags); - ret = clk->ops->set_parent(clk, parent); - spin_unlock_irqrestore(&clock_lock, flags); - clk->parent = (ret ? old : parent); - } + spin_lock_irqsave(&clock_lock, flags); + if (clk->usecount == 0) { + if (clk->ops->set_parent) + ret = clk->ops->set_parent(clk, parent); + else + ret = clk_reparent(clk, parent); + + if (ret == 0) { + pr_debug("clock: set parent of %s to %s (new rate %ld)\n", + clk->name, clk->parent->name, clk->rate); + if (clk->ops->recalc) + clk->rate = clk->ops->recalc(clk); + propagate_rate(clk); + } + } else + ret = -EBUSY; + spin_unlock_irqrestore(&clock_lock, flags); - if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) - propagate_rate(clk); return ret; } EXPORT_SYMBOL_GPL(clk_set_parent); @@ -294,14 +379,69 @@ long clk_round_rate(struct clk *clk, unsigned long rate) EXPORT_SYMBOL_GPL(clk_round_rate); /* + * Find the correct struct clk for the device and connection ID. + * We do slightly fuzzy matching here: + * An entry with a NULL ID is assumed to be a wildcard. + * If an entry has a device ID, it must match + * If an entry has a connection ID, it must match + * Then we take the most specific entry - with the following + * order of precidence: dev+con > dev only > con only. + */ +static struct clk *clk_find(const char *dev_id, const char *con_id) +{ + struct clk_lookup *p; + struct clk *clk = NULL; + int match, best = 0; + + list_for_each_entry(p, &clock_list, node) { + match = 0; + if (p->dev_id) { + if (!dev_id || strcmp(p->dev_id, dev_id)) + continue; + match += 2; + } + if (p->con_id) { + if (!con_id || strcmp(p->con_id, con_id)) + continue; + match += 1; + } + if (match == 0) + continue; + + if (match > best) { + clk = p->clk; + best = match; + } + } + return clk; +} + +struct clk *clk_get_sys(const char *dev_id, const char *con_id) +{ + struct clk *clk; + + mutex_lock(&clock_list_sem); + clk = clk_find(dev_id, con_id); + mutex_unlock(&clock_list_sem); + + return clk ? clk : ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL_GPL(clk_get_sys); + +/* * Returns a clock. Note that we first try to use device id on the bus * and clock name. If this fails, we try to use clock name only. */ struct clk *clk_get(struct device *dev, const char *id) { + const char *dev_id = dev ? dev_name(dev) : NULL; struct clk *p, *clk = ERR_PTR(-ENOENT); int idno; + clk = clk_get_sys(dev_id, id); + if (clk && !IS_ERR(clk)) + return clk; + if (dev == NULL || dev->bus != &platform_bus_type) idno = -1; else @@ -337,36 +477,6 @@ void clk_put(struct clk *clk) } EXPORT_SYMBOL_GPL(clk_put); -void __init __attribute__ ((weak)) -arch_init_clk_ops(struct clk_ops **ops, int type) -{ -} - -int __init __attribute__ ((weak)) -arch_clk_init(void) -{ - return 0; -} - -static int show_clocks(char *buf, char **start, off_t off, - int len, int *eof, void *data) -{ - struct clk *clk; - char *p = buf; - - list_for_each_entry_reverse(clk, &clock_list, node) { - unsigned long rate = clk_get_rate(clk); - - p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name, - rate / 1000000, (rate % 1000000) / 10000, - ((clk->flags & CLK_ALWAYS_ENABLED) || - clk->usecount > 0) ? - "enabled" : "disabled"); - } - - return p - buf; -} - #ifdef CONFIG_PM static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) { @@ -376,20 +486,22 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) switch (state.event) { case PM_EVENT_ON: /* Resumeing from hibernation */ - if (prev_state.event == PM_EVENT_FREEZE) { - list_for_each_entry(clkp, &clock_list, node) - if (likely(clkp->ops)) { - unsigned long rate = clkp->rate; - - if (likely(clkp->ops->set_parent)) - clkp->ops->set_parent(clkp, - clkp->parent); - if (likely(clkp->ops->set_rate)) - clkp->ops->set_rate(clkp, - rate, NO_CHANGE); - else if (likely(clkp->ops->recalc)) - clkp->ops->recalc(clkp); - } + if (prev_state.event != PM_EVENT_FREEZE) + break; + + list_for_each_entry(clkp, &clock_list, node) { + if (likely(clkp->ops)) { + unsigned long rate = clkp->rate; + + if (likely(clkp->ops->set_parent)) + clkp->ops->set_parent(clkp, + clkp->parent); + if (likely(clkp->ops->set_rate)) + clkp->ops->set_rate(clkp, + rate, NO_CHANGE); + else if (likely(clkp->ops->recalc)) + clkp->rate = clkp->ops->recalc(clkp); + } } break; case PM_EVENT_FREEZE: @@ -433,34 +545,116 @@ subsys_initcall(clk_sysdev_init); int __init clk_init(void) { - int i, ret = 0; - - BUG_ON(!master_clk.rate); - - for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) { - struct clk *clk = onchip_clocks[i]; + int ret; - arch_init_clk_ops(&clk->ops, i); - ret |= clk_register(clk); + ret = arch_clk_init(); + if (unlikely(ret)) { + pr_err("%s: CPU clock registration failed.\n", __func__); + return ret; } - ret |= arch_clk_init(); + if (sh_mv.mv_clk_init) { + ret = sh_mv.mv_clk_init(); + if (unlikely(ret)) { + pr_err("%s: machvec clock initialization failed.\n", + __func__); + return ret; + } + } /* Kick the child clocks.. */ - propagate_rate(&master_clk); - propagate_rate(&bus_clk); + recalculate_root_clocks(); + + /* Enable the necessary init clocks */ + clk_enable_init_clocks(); return ret; } -static int __init clk_proc_init(void) +/* + * debugfs support to trace clock tree hierarchy and attributes + */ +static struct dentry *clk_debugfs_root; + +static int clk_debugfs_register_one(struct clk *c) { - struct proc_dir_entry *p; - p = create_proc_read_entry("clocks", S_IRUSR, NULL, - show_clocks, NULL); - if (unlikely(!p)) - return -EINVAL; + int err; + struct dentry *d, *child; + struct clk *pa = c->parent; + char s[255]; + char *p = s; + + p += sprintf(p, "%s", c->name); + if (c->id >= 0) + sprintf(p, ":%d", c->id); + d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root); + if (!d) + return -ENOMEM; + c->dentry = d; + + d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags); + if (!d) { + err = -ENOMEM; + goto err_out; + } + return 0; + +err_out: + d = c->dentry; + list_for_each_entry(child, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(c->dentry); + return err; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->parent; + + if (pa && !pa->dentry) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + if (!c->dentry) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clock_list, node) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } return 0; +err_out: + debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */ + return err; } -subsys_initcall(clk_proc_init); +late_initcall(clk_debugfs_init); diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c index d2c157917999..4fe863170e31 100644 --- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c @@ -38,32 +38,27 @@ static struct clk_ops sh7619_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7619_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { - clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; + return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; } static struct clk_ops sh7619_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) -{ - clk->rate = clk->parent->rate; -} - static struct clk_ops sh7619_cpu_clk_ops = { - .recalc = cpu_clk_recalc, + .recalc = followparent_recalc, }; static struct clk_ops *sh7619_clk_ops[] = { @@ -78,4 +73,3 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) if (idx < ARRAY_SIZE(sh7619_clk_ops)) *ops = sh7619_clk_ops[idx]; } - diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 94ac27fc2237..13798733f2db 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c @@ -115,7 +115,7 @@ static struct sh_timer_config cmt0_platform_data = { .name = "CMT0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 0, /* disabled due to code generation issues */ }; @@ -147,7 +147,7 @@ static struct sh_timer_config cmt1_platform_data = { .name = "CMT1", .channel_offset = 0x08, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 0, /* disabled due to code generation issues */ }; diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c index 4a5e59732334..7814c76159a7 100644 --- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c @@ -34,37 +34,37 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12}; static void master_clk_init(struct clk *clk) { - clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; + return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; } static struct clk_ops sh7201_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7201_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7201_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7201_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c index fb781329848a..940986965102 100644 --- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c @@ -46,33 +46,28 @@ static struct clk_ops sh7203_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7203_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx-2]; + return clk->parent->rate / pfc_divisors[idx-2]; } static struct clk_ops sh7203_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) -{ - clk->rate = clk->parent->rate; -} - static struct clk_ops sh7203_cpu_clk_ops = { - .recalc = cpu_clk_recalc, + .recalc = followparent_recalc, }; static struct clk_ops *sh7203_clk_ops[] = { diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c index 82d7f991ef6b..c2268bdeceeb 100644 --- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c @@ -41,29 +41,29 @@ static struct clk_ops sh7206_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7206_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { - clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; + return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; } static struct clk_ops sh7206_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7206_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index a452d9649069..869c2da4820b 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c @@ -118,7 +118,7 @@ static struct sh_timer_config mtu2_0_platform_data = { .name = "MTU2_0", .channel_offset = -0x80, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -149,7 +149,7 @@ static struct sh_timer_config mtu2_1_platform_data = { .name = "MTU2_1", .channel_offset = -0x100, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -180,7 +180,7 @@ static struct sh_timer_config mtu2_2_platform_data = { .name = "MTU2_2", .channel_offset = 0x80, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 772358b7685e..d8febe128066 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c @@ -255,7 +255,7 @@ static struct sh_timer_config mtu2_0_platform_data = { .name = "MTU2_0", .channel_offset = -0x80, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -286,7 +286,7 @@ static struct sh_timer_config mtu2_1_platform_data = { .name = "MTU2_1", .channel_offset = -0x100, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -317,7 +317,7 @@ static struct sh_timer_config mtu2_2_platform_data = { .name = "MTU2_2", .channel_offset = 0x80, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index d7493418ba60..62e3039d2398 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c @@ -211,7 +211,7 @@ static struct sh_timer_config cmt0_platform_data = { .name = "CMT0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 0, /* disabled due to code generation issues */ }; @@ -243,7 +243,7 @@ static struct sh_timer_config cmt1_platform_data = { .name = "CMT1", .channel_offset = 0x08, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 0, /* disabled due to code generation issues */ }; @@ -275,7 +275,7 @@ static struct sh_timer_config mtu2_0_platform_data = { .name = "MTU2_0", .channel_offset = -0x80, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -306,7 +306,7 @@ static struct sh_timer_config mtu2_1_platform_data = { .name = "MTU2_1", .channel_offset = -0x100, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index 2fc6bff5c5fb..3e6f3d7a58be 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -171,7 +171,7 @@ static struct sh_timer_config cmt0_platform_data = { .name = "CMT0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 0, /* disabled due to code generation issues */ }; @@ -203,7 +203,7 @@ static struct sh_timer_config cmt1_platform_data = { .name = "CMT1", .channel_offset = 0x08, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 0, /* disabled due to code generation issues */ }; @@ -235,7 +235,7 @@ static struct sh_timer_config mtu2_0_platform_data = { .name = "MTU2_0", .channel_offset = -0x80, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -266,7 +266,7 @@ static struct sh_timer_config mtu2_1_platform_data = { .name = "MTU2_1", .channel_offset = -0x100, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -297,7 +297,7 @@ static struct sh_timer_config mtu2_2_platform_data = { .name = "MTU2_2", .channel_offset = 0x80, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c index c3c945958baf..27b8738f0b09 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh3.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c @@ -38,36 +38,36 @@ static struct clk_ops sh3_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh3_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); - clk->rate = clk->parent->rate / stc_multipliers[idx]; + return clk->parent->rate / stc_multipliers[idx]; } static struct clk_ops sh3_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh3_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c index dfdbf3277fd7..0ca8f2c3646c 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c @@ -39,30 +39,30 @@ static struct clk_ops sh7705_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = ctrl_inw(FRQCR) & 0x0003; - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7705_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8; - clk->rate = clk->parent->rate / stc_multipliers[idx]; + return clk->parent->rate / stc_multipliers[idx]; } static struct clk_ops sh7705_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4; - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7705_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c index 0cf96f9833bc..4bf7887d310a 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c @@ -34,36 +34,36 @@ static struct clk_ops sh7706_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7706_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); - clk->rate = clk->parent->rate / stc_multipliers[idx]; + return clk->parent->rate / stc_multipliers[idx]; } static struct clk_ops sh7706_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7706_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c index b791a29fdb62..fa30b6017730 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c @@ -41,12 +41,12 @@ static struct clk_ops sh7709_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7709_module_clk_ops = { @@ -56,25 +56,25 @@ static struct clk_ops sh7709_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = (frqcr & 0x0080) ? ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1; - clk->rate = clk->parent->rate * stc_multipliers[idx]; + return clk->parent->rate * stc_multipliers[idx]; } static struct clk_ops sh7709_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7709_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c index 4744c50ec449..030a58ba18a5 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c @@ -33,30 +33,30 @@ static struct clk_ops sh7710_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) & 0x0007); - clk->rate = clk->parent->rate / md_table[idx]; + return clk->parent->rate / md_table[idx]; } static struct clk_ops sh7710_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8; - clk->rate = clk->parent->rate / md_table[idx]; + return clk->parent->rate / md_table[idx]; } static struct clk_ops sh7710_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4; - clk->rate = clk->parent->rate / md_table[idx]; + return clk->parent->rate / md_table[idx]; } static struct clk_ops sh7710_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c index 54f54df51ef0..6428ee6c77ed 100644 --- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c +++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c @@ -33,24 +33,24 @@ static struct clk_ops sh7712_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = frqcr & 0x0007; - clk->rate = clk->parent->rate / divisors[idx]; + return clk->parent->rate / divisors[idx]; } static struct clk_ops sh7712_module_clk_ops = { .recalc = module_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = (frqcr & 0x0030) >> 4; - clk->rate = clk->parent->rate / divisors[idx]; + return clk->parent->rate / divisors[idx]; } static struct clk_ops sh7712_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 39513664d5d7..88f742fed9ed 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c @@ -121,7 +121,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -152,7 +152,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0xe, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -183,7 +183,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1a, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index 9412d915b84e..c56306798584 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c @@ -149,7 +149,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -180,7 +180,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0xe, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -211,7 +211,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1a, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 07ff38d055a7..efa76c8148f4 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c @@ -125,7 +125,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -156,7 +156,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0xe, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -187,7 +187,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1a, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index d8b46f5dff60..5b2107798edb 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c @@ -128,7 +128,7 @@ static struct sh_timer_config cmt0_platform_data = { .name = "CMT0", .channel_offset = 0x10, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 125, .clocksource_rating = 125, }; @@ -160,7 +160,7 @@ static struct sh_timer_config cmt1_platform_data = { .name = "CMT1", .channel_offset = 0x20, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource cmt1_resources[] = { @@ -190,7 +190,7 @@ static struct sh_timer_config cmt2_platform_data = { .name = "CMT2", .channel_offset = 0x30, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource cmt2_resources[] = { @@ -220,7 +220,7 @@ static struct sh_timer_config cmt3_platform_data = { .name = "CMT3", .channel_offset = 0x40, .timer_bit = 3, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource cmt3_resources[] = { @@ -250,7 +250,7 @@ static struct sh_timer_config cmt4_platform_data = { .name = "CMT4", .channel_offset = 0x50, .timer_bit = 4, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource cmt4_resources[] = { @@ -280,7 +280,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x02, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -311,7 +311,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0xe, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -342,7 +342,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1a, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c index a33429463e96..21421e34e7d5 100644 --- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c @@ -21,10 +21,10 @@ static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; -static void emi_clk_recalc(struct clk *clk) +static unsigned long emi_clk_recalc(struct clk *clk) { int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; - clk->rate = clk->parent->rate / frqcr3_divisors[idx]; + return clk->parent->rate / frqcr3_divisors[idx]; } static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) @@ -46,14 +46,14 @@ static struct clk_ops sh4202_emi_clk_ops = { static struct clk sh4202_emi_clk = { .name = "emi_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh4202_emi_clk_ops, }; -static void femi_clk_recalc(struct clk *clk) +static unsigned long femi_clk_recalc(struct clk *clk) { int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; - clk->rate = clk->parent->rate / frqcr3_divisors[idx]; + return clk->parent->rate / frqcr3_divisors[idx]; } static struct clk_ops sh4202_femi_clk_ops = { @@ -62,7 +62,7 @@ static struct clk_ops sh4202_femi_clk_ops = { static struct clk sh4202_femi_clk = { .name = "femi_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh4202_femi_clk_ops, }; @@ -90,10 +90,10 @@ static void shoc_clk_init(struct clk *clk) WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ } -static void shoc_clk_recalc(struct clk *clk) +static unsigned long shoc_clk_recalc(struct clk *clk) { int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; - clk->rate = clk->parent->rate / frqcr3_divisors[idx]; + return clk->parent->rate / frqcr3_divisors[idx]; } static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) @@ -140,7 +140,7 @@ static struct clk_ops sh4202_shoc_clk_ops = { static struct clk sh4202_shoc_clk = { .name = "shoc_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh4202_shoc_clk_ops, }; @@ -150,31 +150,22 @@ static struct clk *sh4202_onchip_clocks[] = { &sh4202_shoc_clk, }; -static int __init sh4202_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; + struct clk *clk; + int i, ret = 0; + + cpg_clk_init(); + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) { struct clk *clkp = sh4202_onchip_clocks[i]; clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); + ret |= clk_register(clkp); } - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); - clk_put(clk); - return 0; + return ret; } - -arch_initcall(sh4202_clk_init); - diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c index dca9f87a12d6..73294d9cd049 100644 --- a/arch/sh/kernel/cpu/sh4/clock-sh4.c +++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c @@ -35,30 +35,30 @@ static struct clk_ops sh4_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) & 0x0007); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh4_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007; - clk->rate = clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate / bfc_divisors[idx]; } static struct clk_ops sh4_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007; - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh4_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index be79fa136255..6d088d123591 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c @@ -38,7 +38,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -69,7 +69,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -100,7 +100,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 09da0c187d4c..851672d15cf4 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c @@ -65,7 +65,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -96,7 +96,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -127,7 +127,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { @@ -162,7 +162,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu3_resources[] = { @@ -192,7 +192,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu4_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index cd097335758f..5b822519bd90 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c @@ -164,7 +164,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -195,7 +195,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -226,7 +226,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 1ccdfc561fef..c090c9a373f6 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -151,27 +151,24 @@ static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 }; static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; #endif -static void master_clk_recalc(struct clk *clk) +static unsigned long master_clk_recalc(struct clk *clk) { unsigned frqcr = ctrl_inl(FRQCR); - clk->rate = CONFIG_SH_PCLK_FREQ * STCPLL(frqcr); + return CONFIG_SH_PCLK_FREQ * STCPLL(frqcr); } static void master_clk_init(struct clk *clk) { clk->parent = NULL; - clk->flags |= CLK_RATE_PROPAGATES; - clk->rate = CONFIG_SH_PCLK_FREQ; - master_clk_recalc(clk); + clk->rate = master_clk_recalc(clk); } - -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { unsigned long frqcr = ctrl_inl(FRQCR); - clk->rate = clk->parent->rate / STCPLL(frqcr); + return clk->parent->rate / STCPLL(frqcr); } #if defined(CONFIG_CPU_SUBTYPE_SH7724) @@ -283,14 +280,14 @@ static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate) return index; } -static void sh7722_frqcr_recalc(struct clk *clk) +static unsigned long sh7722_frqcr_recalc(struct clk *clk) { struct frqcr_context ctx = sh7722_get_clk_context(clk->name); unsigned long frqcr = ctrl_inl(FRQCR); int index; index = (frqcr >> ctx.shift) & ctx.mask; - clk->rate = clk->parent->rate * 2 / divisors2[index]; + return clk->parent->rate * 2 / divisors2[index]; } static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, @@ -439,11 +436,8 @@ static struct clk_ops sh7722_frqcr_clk_ops = { /* * clock ops methods for SIU A/B and IrDA clock - * */ - #ifndef CONFIG_CPU_SUBTYPE_SH7343 - static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) { unsigned long r; @@ -458,12 +452,12 @@ static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) return 0; } -static void sh7722_siu_recalc(struct clk *clk) +static unsigned long sh7722_siu_recalc(struct clk *clk) { unsigned long r; r = ctrl_inl(clk->arch_flags); - clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF]; + return clk->parent->rate * 2 / divisors2[r & 0xF]; } static int sh7722_siu_start_stop(struct clk *clk, int enable) @@ -478,9 +472,9 @@ static int sh7722_siu_start_stop(struct clk *clk, int enable) return 0; } -static void sh7722_siu_enable(struct clk *clk) +static int sh7722_siu_enable(struct clk *clk) { - sh7722_siu_start_stop(clk, 1); + return sh7722_siu_start_stop(clk, 1); } static void sh7722_siu_disable(struct clk *clk) @@ -497,12 +491,13 @@ static struct clk_ops sh7722_siu_clk_ops = { #endif /* CONFIG_CPU_SUBTYPE_SH7343 */ -static void sh7722_video_enable(struct clk *clk) +static int sh7722_video_enable(struct clk *clk) { unsigned long r; r = ctrl_inl(VCLKCR); ctrl_outl( r & ~(1<<8), VCLKCR); + return 0; } static void sh7722_video_disable(struct clk *clk) @@ -525,12 +520,12 @@ static int sh7722_video_set_rate(struct clk *clk, unsigned long rate, return 0; } -static void sh7722_video_recalc(struct clk *clk) +static unsigned long sh7722_video_recalc(struct clk *clk) { unsigned long r; r = ctrl_inl(VCLKCR); - clk->rate = clk->parent->rate / ((r & 0x3F) + 1); + return clk->parent->rate / ((r & 0x3F) + 1); } static struct clk_ops sh7722_video_clk_ops = { @@ -545,19 +540,16 @@ static struct clk_ops sh7722_video_clk_ops = { static struct clk sh7722_umem_clock = { .name = "umem_clk", .ops = &sh7722_frqcr_clk_ops, - .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_sh_clock = { .name = "sh_clk", .ops = &sh7722_frqcr_clk_ops, - .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_peripheral_clock = { .name = "peripheral_clk", .ops = &sh7722_frqcr_clk_ops, - .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_sdram_clock = { @@ -568,7 +560,6 @@ static struct clk sh7722_sdram_clock = { static struct clk sh7722_r_clock = { .name = "r_clk", .rate = 32768, - .flags = CLK_RATE_PROPAGATES, }; #if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\ @@ -627,7 +618,7 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, int enable) break; default: return -EINVAL; - } + } r = ctrl_inl(reg); @@ -640,9 +631,9 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, int enable) return 0; } -static void sh7722_mstpcr_enable(struct clk *clk) +static int sh7722_mstpcr_enable(struct clk *clk) { - sh7722_mstpcr_start_stop(clk, 1); + return sh7722_mstpcr_start_stop(clk, 1); } static void sh7722_mstpcr_disable(struct clk *clk) @@ -650,219 +641,214 @@ static void sh7722_mstpcr_disable(struct clk *clk) sh7722_mstpcr_start_stop(clk, 0); } -static void sh7722_mstpcr_recalc(struct clk *clk) -{ - if (clk->parent) - clk->rate = clk->parent->rate; -} - static struct clk_ops sh7722_mstpcr_clk_ops = { .enable = sh7722_mstpcr_enable, .disable = sh7722_mstpcr_disable, - .recalc = sh7722_mstpcr_recalc, + .recalc = followparent_recalc, }; -#define MSTPCR(_name, _parent, regnr, bitnr) \ +#define MSTPCR(_name, _parent, regnr, bitnr, _flags) \ { \ .name = _name, \ + .flags = _flags, \ .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \ .ops = (void *)_parent, \ } static struct clk sh7722_mstpcr_clocks[] = { #if defined(CONFIG_CPU_SUBTYPE_SH7722) - MSTPCR("uram0", "umem_clk", 0, 28), - MSTPCR("xymem0", "bus_clk", 0, 26), - MSTPCR("tmu0", "peripheral_clk", 0, 15), - MSTPCR("cmt0", "r_clk", 0, 14), - MSTPCR("rwdt0", "r_clk", 0, 13), - MSTPCR("flctl0", "peripheral_clk", 0, 10), - MSTPCR("scif0", "peripheral_clk", 0, 7), - MSTPCR("scif1", "peripheral_clk", 0, 6), - MSTPCR("scif2", "peripheral_clk", 0, 5), - MSTPCR("i2c0", "peripheral_clk", 1, 9), - MSTPCR("rtc0", "r_clk", 1, 8), - MSTPCR("sdhi0", "peripheral_clk", 2, 18), - MSTPCR("keysc0", "r_clk", 2, 14), - MSTPCR("usbf0", "peripheral_clk", 2, 11), - MSTPCR("2dg0", "bus_clk", 2, 9), - MSTPCR("siu0", "bus_clk", 2, 8), - MSTPCR("vou0", "bus_clk", 2, 5), - MSTPCR("jpu0", "bus_clk", 2, 6), - MSTPCR("beu0", "bus_clk", 2, 4), - MSTPCR("ceu0", "bus_clk", 2, 3), - MSTPCR("veu0", "bus_clk", 2, 2), - MSTPCR("vpu0", "bus_clk", 2, 1), - MSTPCR("lcdc0", "bus_clk", 2, 0), + MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT), + MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT), + MSTPCR("tmu0", "peripheral_clk", 0, 15, 0), + MSTPCR("cmt0", "r_clk", 0, 14, 0), + MSTPCR("rwdt0", "r_clk", 0, 13, 0), + MSTPCR("flctl0", "peripheral_clk", 0, 10, 0), + MSTPCR("scif0", "peripheral_clk", 0, 7, 0), + MSTPCR("scif1", "peripheral_clk", 0, 6, 0), + MSTPCR("scif2", "peripheral_clk", 0, 5, 0), + MSTPCR("i2c0", "peripheral_clk", 1, 9, 0), + MSTPCR("rtc0", "r_clk", 1, 8, 0), + MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0), + MSTPCR("keysc0", "r_clk", 2, 14, 0), + MSTPCR("usbf0", "peripheral_clk", 2, 11, 0), + MSTPCR("2dg0", "bus_clk", 2, 9, 0), + MSTPCR("siu0", "bus_clk", 2, 8, 0), + MSTPCR("vou0", "bus_clk", 2, 5, 0), + MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT), + MSTPCR("beu0", "bus_clk", 2, 4, 0), + MSTPCR("ceu0", "bus_clk", 2, 3, 0), + MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT), + MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), + MSTPCR("lcdc0", "bus_clk", 2, 0, 0), #endif #if defined(CONFIG_CPU_SUBTYPE_SH7723) /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ - MSTPCR("tlb0", "cpu_clk", 0, 31), - MSTPCR("ic0", "cpu_clk", 0, 30), - MSTPCR("oc0", "cpu_clk", 0, 29), - MSTPCR("l2c0", "sh_clk", 0, 28), - MSTPCR("ilmem0", "cpu_clk", 0, 27), - MSTPCR("fpu0", "cpu_clk", 0, 24), - MSTPCR("intc0", "cpu_clk", 0, 22), - MSTPCR("dmac0", "bus_clk", 0, 21), - MSTPCR("sh0", "sh_clk", 0, 20), - MSTPCR("hudi0", "peripheral_clk", 0, 19), - MSTPCR("ubc0", "cpu_clk", 0, 17), - MSTPCR("tmu0", "peripheral_clk", 0, 15), - MSTPCR("cmt0", "r_clk", 0, 14), - MSTPCR("rwdt0", "r_clk", 0, 13), - MSTPCR("dmac1", "bus_clk", 0, 12), - MSTPCR("tmu1", "peripheral_clk", 0, 11), - MSTPCR("flctl0", "peripheral_clk", 0, 10), - MSTPCR("scif0", "peripheral_clk", 0, 9), - MSTPCR("scif1", "peripheral_clk", 0, 8), - MSTPCR("scif2", "peripheral_clk", 0, 7), - MSTPCR("scif3", "bus_clk", 0, 6), - MSTPCR("scif4", "bus_clk", 0, 5), - MSTPCR("scif5", "bus_clk", 0, 4), - MSTPCR("msiof0", "bus_clk", 0, 2), - MSTPCR("msiof1", "bus_clk", 0, 1), - MSTPCR("meram0", "sh_clk", 0, 0), - MSTPCR("i2c0", "peripheral_clk", 1, 9), - MSTPCR("rtc0", "r_clk", 1, 8), - MSTPCR("atapi0", "sh_clk", 2, 28), - MSTPCR("adc0", "peripheral_clk", 2, 28), - MSTPCR("tpu0", "bus_clk", 2, 25), - MSTPCR("irda0", "peripheral_clk", 2, 24), - MSTPCR("tsif0", "bus_clk", 2, 22), - MSTPCR("icb0", "bus_clk", 2, 21), - MSTPCR("sdhi0", "bus_clk", 2, 18), - MSTPCR("sdhi1", "bus_clk", 2, 17), - MSTPCR("keysc0", "r_clk", 2, 14), - MSTPCR("usb0", "bus_clk", 2, 11), - MSTPCR("2dg0", "bus_clk", 2, 10), - MSTPCR("siu0", "bus_clk", 2, 8), - MSTPCR("veu1", "bus_clk", 2, 6), - MSTPCR("vou0", "bus_clk", 2, 5), - MSTPCR("beu0", "bus_clk", 2, 4), - MSTPCR("ceu0", "bus_clk", 2, 3), - MSTPCR("veu0", "bus_clk", 2, 2), - MSTPCR("vpu0", "bus_clk", 2, 1), - MSTPCR("lcdc0", "bus_clk", 2, 0), + MSTPCR("tlb0", "cpu_clk", 0, 31, 0), + MSTPCR("ic0", "cpu_clk", 0, 30, 0), + MSTPCR("oc0", "cpu_clk", 0, 29, 0), + MSTPCR("l2c0", "sh_clk", 0, 28, 0), + MSTPCR("ilmem0", "cpu_clk", 0, 27, 0), + MSTPCR("fpu0", "cpu_clk", 0, 24, 0), + MSTPCR("intc0", "cpu_clk", 0, 22, 0), + MSTPCR("dmac0", "bus_clk", 0, 21, 0), + MSTPCR("sh0", "sh_clk", 0, 20, 0), + MSTPCR("hudi0", "peripheral_clk", 0, 19, 0), + MSTPCR("ubc0", "cpu_clk", 0, 17, 0), + MSTPCR("tmu0", "peripheral_clk", 0, 15, 0), + MSTPCR("cmt0", "r_clk", 0, 14, 0), + MSTPCR("rwdt0", "r_clk", 0, 13, 0), + MSTPCR("dmac1", "bus_clk", 0, 12, 0), + MSTPCR("tmu1", "peripheral_clk", 0, 11, 0), + MSTPCR("flctl0", "peripheral_clk", 0, 10, 0), + MSTPCR("scif0", "peripheral_clk", 0, 9, 0), + MSTPCR("scif1", "peripheral_clk", 0, 8, 0), + MSTPCR("scif2", "peripheral_clk", 0, 7, 0), + MSTPCR("scif3", "bus_clk", 0, 6, 0), + MSTPCR("scif4", "bus_clk", 0, 5, 0), + MSTPCR("scif5", "bus_clk", 0, 4, 0), + MSTPCR("msiof0", "bus_clk", 0, 2, 0), + MSTPCR("msiof1", "bus_clk", 0, 1, 0), + MSTPCR("meram0", "sh_clk", 0, 0, CLK_ENABLE_ON_INIT), + MSTPCR("i2c0", "peripheral_clk", 1, 9, 0), + MSTPCR("rtc0", "r_clk", 1, 8, 0), + MSTPCR("atapi0", "sh_clk", 2, 28, 0), + MSTPCR("adc0", "peripheral_clk", 2, 28, 0), + MSTPCR("tpu0", "bus_clk", 2, 25, 0), + MSTPCR("irda0", "peripheral_clk", 2, 24, 0), + MSTPCR("tsif0", "bus_clk", 2, 22, 0), + MSTPCR("icb0", "bus_clk", 2, 21, 0), + MSTPCR("sdhi0", "bus_clk", 2, 18, 0), + MSTPCR("sdhi1", "bus_clk", 2, 17, 0), + MSTPCR("keysc0", "r_clk", 2, 14, 0), + MSTPCR("usb0", "bus_clk", 2, 11, 0), + MSTPCR("2dg0", "bus_clk", 2, 10, 0), + MSTPCR("siu0", "bus_clk", 2, 8, 0), + MSTPCR("veu1", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT), + MSTPCR("vou0", "bus_clk", 2, 5, 0), + MSTPCR("beu0", "bus_clk", 2, 4, 0), + MSTPCR("ceu0", "bus_clk", 2, 3, 0), + MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT), + MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), + MSTPCR("lcdc0", "bus_clk", 2, 0, 0), #endif #if defined(CONFIG_CPU_SUBTYPE_SH7724) /* See Datasheet : Overview -> Block Diagram */ - MSTPCR("tlb0", "cpu_clk", 0, 31), - MSTPCR("ic0", "cpu_clk", 0, 30), - MSTPCR("oc0", "cpu_clk", 0, 29), - MSTPCR("rs0", "bus_clk", 0, 28), - MSTPCR("ilmem0", "cpu_clk", 0, 27), - MSTPCR("l2c0", "sh_clk", 0, 26), - MSTPCR("fpu0", "cpu_clk", 0, 24), - MSTPCR("intc0", "peripheral_clk", 0, 22), - MSTPCR("dmac0", "bus_clk", 0, 21), - MSTPCR("sh0", "sh_clk", 0, 20), - MSTPCR("hudi0", "peripheral_clk", 0, 19), - MSTPCR("ubc0", "cpu_clk", 0, 17), - MSTPCR("tmu0", "peripheral_clk", 0, 15), - MSTPCR("cmt0", "r_clk", 0, 14), - MSTPCR("rwdt0", "r_clk", 0, 13), - MSTPCR("dmac1", "bus_clk", 0, 12), - MSTPCR("tmu1", "peripheral_clk", 0, 10), - MSTPCR("scif0", "peripheral_clk", 0, 9), - MSTPCR("scif1", "peripheral_clk", 0, 8), - MSTPCR("scif2", "peripheral_clk", 0, 7), - MSTPCR("scif3", "bus_clk", 0, 6), - MSTPCR("scif4", "bus_clk", 0, 5), - MSTPCR("scif5", "bus_clk", 0, 4), - MSTPCR("msiof0", "bus_clk", 0, 2), - MSTPCR("msiof1", "bus_clk", 0, 1), - MSTPCR("keysc0", "r_clk", 1, 12), - MSTPCR("rtc0", "r_clk", 1, 11), - MSTPCR("i2c0", "peripheral_clk", 1, 9), - MSTPCR("i2c1", "peripheral_clk", 1, 8), - MSTPCR("mmc0", "bus_clk", 2, 29), - MSTPCR("eth0", "bus_clk", 2, 28), - MSTPCR("atapi0", "bus_clk", 2, 26), - MSTPCR("tpu0", "bus_clk", 2, 25), - MSTPCR("irda0", "peripheral_clk", 2, 24), - MSTPCR("tsif0", "bus_clk", 2, 22), - MSTPCR("usb1", "bus_clk", 2, 21), - MSTPCR("usb0", "bus_clk", 2, 20), - MSTPCR("2dg0", "bus_clk", 2, 19), - MSTPCR("sdhi0", "bus_clk", 2, 18), - MSTPCR("sdhi1", "bus_clk", 2, 17), - MSTPCR("veu1", "bus_clk", 2, 15), - MSTPCR("ceu1", "bus_clk", 2, 13), - MSTPCR("beu1", "bus_clk", 2, 12), - MSTPCR("2ddmac0", "sh_clk", 2, 10), - MSTPCR("spu0", "bus_clk", 2, 9), - MSTPCR("jpu0", "bus_clk", 2, 6), - MSTPCR("vou0", "bus_clk", 2, 5), - MSTPCR("beu0", "bus_clk", 2, 4), - MSTPCR("ceu0", "bus_clk", 2, 3), - MSTPCR("veu0", "bus_clk", 2, 2), - MSTPCR("vpu0", "bus_clk", 2, 1), - MSTPCR("lcdc0", "bus_clk", 2, 0), + MSTPCR("tlb0", "cpu_clk", 0, 31, 0), + MSTPCR("ic0", "cpu_clk", 0, 30, 0), + MSTPCR("oc0", "cpu_clk", 0, 29, 0), + MSTPCR("rs0", "bus_clk", 0, 28, 0), + MSTPCR("ilmem0", "cpu_clk", 0, 27, 0), + MSTPCR("l2c0", "sh_clk", 0, 26, 0), + MSTPCR("fpu0", "cpu_clk", 0, 24, 0), + MSTPCR("intc0", "peripheral_clk", 0, 22, 0), + MSTPCR("dmac0", "bus_clk", 0, 21, 0), + MSTPCR("sh0", "sh_clk", 0, 20, 0), + MSTPCR("hudi0", "peripheral_clk", 0, 19, 0), + MSTPCR("ubc0", "cpu_clk", 0, 17, 0), + MSTPCR("tmu0", "peripheral_clk", 0, 15, 0), + MSTPCR("cmt0", "r_clk", 0, 14, 0), + MSTPCR("rwdt0", "r_clk", 0, 13, 0), + MSTPCR("dmac1", "bus_clk", 0, 12, 0), + MSTPCR("tmu1", "peripheral_clk", 0, 10, 0), + MSTPCR("scif0", "peripheral_clk", 0, 9, 0), + MSTPCR("scif1", "peripheral_clk", 0, 8, 0), + MSTPCR("scif2", "peripheral_clk", 0, 7, 0), + MSTPCR("scif3", "bus_clk", 0, 6, 0), + MSTPCR("scif4", "bus_clk", 0, 5, 0), + MSTPCR("scif5", "bus_clk", 0, 4, 0), + MSTPCR("msiof0", "bus_clk", 0, 2, 0), + MSTPCR("msiof1", "bus_clk", 0, 1, 0), + MSTPCR("keysc0", "r_clk", 1, 12, 0), + MSTPCR("rtc0", "r_clk", 1, 11, 0), + MSTPCR("i2c0", "peripheral_clk", 1, 9, 0), + MSTPCR("i2c1", "peripheral_clk", 1, 8, 0), + MSTPCR("mmc0", "bus_clk", 2, 29, 0), + MSTPCR("eth0", "bus_clk", 2, 28, 0), + MSTPCR("atapi0", "bus_clk", 2, 26, 0), + MSTPCR("tpu0", "bus_clk", 2, 25, 0), + MSTPCR("irda0", "peripheral_clk", 2, 24, 0), + MSTPCR("tsif0", "bus_clk", 2, 22, 0), + MSTPCR("usb1", "bus_clk", 2, 21, 0), + MSTPCR("usb0", "bus_clk", 2, 20, 0), + MSTPCR("2dg0", "bus_clk", 2, 19, 0), + MSTPCR("sdhi0", "bus_clk", 2, 18, 0), + MSTPCR("sdhi1", "bus_clk", 2, 17, 0), + MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT), + MSTPCR("ceu1", "bus_clk", 2, 13, 0), + MSTPCR("beu1", "bus_clk", 2, 12, 0), + MSTPCR("2ddmac0", "sh_clk", 2, 10, 0), + MSTPCR("spu0", "bus_clk", 2, 9, 0), + MSTPCR("jpu0", "bus_clk", 2, 6, 0), + MSTPCR("vou0", "bus_clk", 2, 5, 0), + MSTPCR("beu0", "bus_clk", 2, 4, 0), + MSTPCR("ceu0", "bus_clk", 2, 3, 0), + MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT), + MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), + MSTPCR("lcdc0", "bus_clk", 2, 0, 0), #endif #if defined(CONFIG_CPU_SUBTYPE_SH7343) - MSTPCR("uram0", "umem_clk", 0, 28), - MSTPCR("xymem0", "bus_clk", 0, 26), - MSTPCR("tmu0", "peripheral_clk", 0, 15), - MSTPCR("cmt0", "r_clk", 0, 14), - MSTPCR("rwdt0", "r_clk", 0, 13), - MSTPCR("scif0", "peripheral_clk", 0, 7), - MSTPCR("scif1", "peripheral_clk", 0, 6), - MSTPCR("scif2", "peripheral_clk", 0, 5), - MSTPCR("scif3", "peripheral_clk", 0, 4), - MSTPCR("i2c0", "peripheral_clk", 1, 9), - MSTPCR("i2c1", "peripheral_clk", 1, 8), - MSTPCR("sdhi0", "peripheral_clk", 2, 18), - MSTPCR("keysc0", "r_clk", 2, 14), - MSTPCR("usbf0", "peripheral_clk", 2, 11), - MSTPCR("siu0", "bus_clk", 2, 8), - MSTPCR("jpu0", "bus_clk", 2, 6), - MSTPCR("vou0", "bus_clk", 2, 5), - MSTPCR("beu0", "bus_clk", 2, 4), - MSTPCR("ceu0", "bus_clk", 2, 3), - MSTPCR("veu0", "bus_clk", 2, 2), - MSTPCR("vpu0", "bus_clk", 2, 1), - MSTPCR("lcdc0", "bus_clk", 2, 0), + MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT), + MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT), + MSTPCR("tmu0", "peripheral_clk", 0, 15, 0), + MSTPCR("cmt0", "r_clk", 0, 14, 0), + MSTPCR("rwdt0", "r_clk", 0, 13, 0), + MSTPCR("scif0", "peripheral_clk", 0, 7, 0), + MSTPCR("scif1", "peripheral_clk", 0, 6, 0), + MSTPCR("scif2", "peripheral_clk", 0, 5, 0), + MSTPCR("scif3", "peripheral_clk", 0, 4, 0), + MSTPCR("i2c0", "peripheral_clk", 1, 9, 0), + MSTPCR("i2c1", "peripheral_clk", 1, 8, 0), + MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0), + MSTPCR("keysc0", "r_clk", 2, 14, 0), + MSTPCR("usbf0", "peripheral_clk", 2, 11, 0), + MSTPCR("siu0", "bus_clk", 2, 8, 0), + MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT), + MSTPCR("vou0", "bus_clk", 2, 5, 0), + MSTPCR("beu0", "bus_clk", 2, 4, 0), + MSTPCR("ceu0", "bus_clk", 2, 3, 0), + MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT), + MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), + MSTPCR("lcdc0", "bus_clk", 2, 0, 0), #endif #if defined(CONFIG_CPU_SUBTYPE_SH7366) /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ - MSTPCR("tlb0", "cpu_clk", 0, 31), - MSTPCR("ic0", "cpu_clk", 0, 30), - MSTPCR("oc0", "cpu_clk", 0, 29), - MSTPCR("rsmem0", "sh_clk", 0, 28), - MSTPCR("xymem0", "cpu_clk", 0, 26), - MSTPCR("intc30", "peripheral_clk", 0, 23), - MSTPCR("intc0", "peripheral_clk", 0, 22), - MSTPCR("dmac0", "bus_clk", 0, 21), - MSTPCR("sh0", "sh_clk", 0, 20), - MSTPCR("hudi0", "peripheral_clk", 0, 19), - MSTPCR("ubc0", "cpu_clk", 0, 17), - MSTPCR("tmu0", "peripheral_clk", 0, 15), - MSTPCR("cmt0", "r_clk", 0, 14), - MSTPCR("rwdt0", "r_clk", 0, 13), - MSTPCR("flctl0", "peripheral_clk", 0, 10), - MSTPCR("scif0", "peripheral_clk", 0, 7), - MSTPCR("scif1", "bus_clk", 0, 6), - MSTPCR("scif2", "bus_clk", 0, 5), - MSTPCR("msiof0", "peripheral_clk", 0, 2), - MSTPCR("sbr0", "peripheral_clk", 0, 1), - MSTPCR("i2c0", "peripheral_clk", 1, 9), - MSTPCR("icb0", "bus_clk", 2, 27), - MSTPCR("meram0", "sh_clk", 2, 26), - MSTPCR("dacc0", "peripheral_clk", 2, 24), - MSTPCR("dacy0", "peripheral_clk", 2, 23), - MSTPCR("tsif0", "bus_clk", 2, 22), - MSTPCR("sdhi0", "bus_clk", 2, 18), - MSTPCR("mmcif0", "bus_clk", 2, 17), - MSTPCR("usb0", "bus_clk", 2, 11), - MSTPCR("siu0", "bus_clk", 2, 8), - MSTPCR("veu1", "bus_clk", 2, 7), - MSTPCR("vou0", "bus_clk", 2, 5), - MSTPCR("beu0", "bus_clk", 2, 4), - MSTPCR("ceu0", "bus_clk", 2, 3), - MSTPCR("veu0", "bus_clk", 2, 2), - MSTPCR("vpu0", "bus_clk", 2, 1), - MSTPCR("lcdc0", "bus_clk", 2, 0), + MSTPCR("tlb0", "cpu_clk", 0, 31, 0), + MSTPCR("ic0", "cpu_clk", 0, 30, 0), + MSTPCR("oc0", "cpu_clk", 0, 29, 0), + MSTPCR("rsmem0", "sh_clk", 0, 28, CLK_ENABLE_ON_INIT), + MSTPCR("xymem0", "cpu_clk", 0, 26, CLK_ENABLE_ON_INIT), + MSTPCR("intc30", "peripheral_clk", 0, 23, 0), + MSTPCR("intc0", "peripheral_clk", 0, 22, 0), + MSTPCR("dmac0", "bus_clk", 0, 21, 0), + MSTPCR("sh0", "sh_clk", 0, 20, 0), + MSTPCR("hudi0", "peripheral_clk", 0, 19, 0), + MSTPCR("ubc0", "cpu_clk", 0, 17, 0), + MSTPCR("tmu0", "peripheral_clk", 0, 15, 0), + MSTPCR("cmt0", "r_clk", 0, 14, 0), + MSTPCR("rwdt0", "r_clk", 0, 13, 0), + MSTPCR("flctl0", "peripheral_clk", 0, 10, 0), + MSTPCR("scif0", "peripheral_clk", 0, 7, 0), + MSTPCR("scif1", "bus_clk", 0, 6, 0), + MSTPCR("scif2", "bus_clk", 0, 5, 0), + MSTPCR("msiof0", "peripheral_clk", 0, 2, 0), + MSTPCR("sbr0", "peripheral_clk", 0, 1, 0), + MSTPCR("i2c0", "peripheral_clk", 1, 9, 0), + MSTPCR("icb0", "bus_clk", 2, 27, 0), + MSTPCR("meram0", "sh_clk", 2, 26, 0), + MSTPCR("dacc0", "peripheral_clk", 2, 24, 0), + MSTPCR("dacy0", "peripheral_clk", 2, 23, 0), + MSTPCR("tsif0", "bus_clk", 2, 22, 0), + MSTPCR("sdhi0", "bus_clk", 2, 18, 0), + MSTPCR("mmcif0", "bus_clk", 2, 17, 0), + MSTPCR("usb0", "bus_clk", 2, 11, 0), + MSTPCR("siu0", "bus_clk", 2, 8, 0), + MSTPCR("veu1", "bus_clk", 2, 7, CLK_ENABLE_ON_INIT), + MSTPCR("vou0", "bus_clk", 2, 5, 0), + MSTPCR("beu0", "bus_clk", 2, 4, 0), + MSTPCR("ceu0", "bus_clk", 2, 3, 0), + MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT), + MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), + MSTPCR("lcdc0", "bus_clk", 2, 0, 0), #endif }; @@ -897,7 +883,7 @@ struct clk_ops *onchip_ops[] = { void __init arch_init_clk_ops(struct clk_ops **ops, int type) { - BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops)); + BUG_ON(type < 0 || type >= ARRAY_SIZE(onchip_ops)); *ops = onchip_ops[type]; } @@ -906,6 +892,8 @@ int __init arch_clk_init(void) struct clk *clk; int i; + cpg_clk_init(); + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); @@ -926,7 +914,7 @@ int __init arch_clk_init(void) clk_put(clk); } - clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */ + propagate_rate(&sh7722_r_clock); /* make sure rate gets propagated */ return 0; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c index 3177d0d1e06d..370cd47642ef 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c @@ -29,33 +29,28 @@ static struct clk_ops sh7763_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); - clk->rate = clk->parent->rate / p0fc_divisors[idx]; + return clk->parent->rate / p0fc_divisors[idx]; } static struct clk_ops sh7763_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); - clk->rate = clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate / bfc_divisors[idx]; } static struct clk_ops sh7763_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) -{ - clk->rate = clk->parent->rate; -} - static struct clk_ops sh7763_cpu_clk_ops = { - .recalc = cpu_clk_recalc, + .recalc = followparent_recalc, }; static struct clk_ops *sh7763_clk_ops[] = { @@ -71,10 +66,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) *ops = sh7763_clk_ops[idx]; } -static void shyway_clk_recalc(struct clk *clk) +static unsigned long shyway_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); - clk->rate = clk->parent->rate / cfc_divisors[idx]; + return clk->parent->rate / cfc_divisors[idx]; } static struct clk_ops sh7763_shyway_clk_ops = { @@ -83,7 +78,7 @@ static struct clk_ops sh7763_shyway_clk_ops = { static struct clk sh7763_shyway_clk = { .name = "shyway_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh7763_shyway_clk_ops, }; @@ -95,31 +90,22 @@ static struct clk *sh7763_onchip_clocks[] = { &sh7763_shyway_clk, }; -static int __init sh7763_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; + struct clk *clk; + int i, ret = 0; + + cpg_clk_init(); + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { struct clk *clkp = sh7763_onchip_clocks[i]; clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); + ret |= clk_register(clkp); } - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); - clk_put(clk); - return 0; + return ret; } - -arch_initcall(sh7763_clk_init); - diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c index 8e236062c721..e0b896769205 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c @@ -28,30 +28,30 @@ static struct clk_ops sh7770_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7770_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inl(FRQCR) & 0x000f); - clk->rate = clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate / bfc_divisors[idx]; } static struct clk_ops sh7770_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7770_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c index 01f3da619d3d..a249d823578e 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c @@ -29,30 +29,30 @@ static struct clk_ops sh7780_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inl(FRQCR) & 0x0003); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7780_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); - clk->rate = clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate / bfc_divisors[idx]; } static struct clk_ops sh7780_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7780_cpu_clk_ops = { @@ -72,10 +72,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) *ops = sh7780_clk_ops[idx]; } -static void shyway_clk_recalc(struct clk *clk) +static unsigned long shyway_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); - clk->rate = clk->parent->rate / cfc_divisors[idx]; + return clk->parent->rate / cfc_divisors[idx]; } static struct clk_ops sh7780_shyway_clk_ops = { @@ -84,7 +84,7 @@ static struct clk_ops sh7780_shyway_clk_ops = { static struct clk sh7780_shyway_clk = { .name = "shyway_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh7780_shyway_clk_ops, }; @@ -96,31 +96,22 @@ static struct clk *sh7780_onchip_clocks[] = { &sh7780_shyway_clk, }; -static int __init sh7780_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; + struct clk *clk; + int i, ret = 0; + cpg_clk_init(); + + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) { struct clk *clkp = sh7780_onchip_clocks[i]; clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); + ret |= clk_register(clkp); } - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); - clk_put(clk); - return 0; + return ret; } - -arch_initcall(sh7780_clk_init); - diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index 27fa81bef6a0..a4a9bcbec664 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -3,7 +3,7 @@ * * SH7785 support for the clock framework * - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 - 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -11,152 +11,257 @@ */ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/cpufreq.h> #include <asm/clock.h> #include <asm/freq.h> -#include <asm/io.h> - -static int ifc_divisors[] = { 1, 2, 4, 6 }; -static int ufc_divisors[] = { 1, 1, 4, 6 }; -static int sfc_divisors[] = { 1, 1, 4, 6 }; -static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, - 24, 32, 36, 48, 1, 1, 1, 1 }; -static int mfc_divisors[] = { 1, 1, 4, 6 }; -static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, - 24, 32, 36, 48, 1, 1, 1, 1 }; - -static void master_clk_init(struct clk *clk) -{ - clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f]; -} -static struct clk_ops sh7785_master_clk_ops = { - .init = master_clk_init, +static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48 }; + +static struct clk_div_mult_table cpg_div = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), }; -static void module_clk_recalc(struct clk *clk) -{ - int idx = (ctrl_inl(FRQMR1) & 0x000f); - clk->rate = clk->parent->rate / pfc_divisors[idx]; -} +struct clk_priv { + unsigned int shift; + + /* allowable divisor bitmap */ + unsigned long div_bitmap; -static struct clk_ops sh7785_module_clk_ops = { - .recalc = module_clk_recalc, + /* Supportable frequencies + termination entry */ + struct cpufreq_frequency_table freq_table[ARRAY_SIZE(div2)+1]; }; -static void bus_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); - clk->rate = clk->parent->rate / bfc_divisors[idx]; +#define FRQMR_CLK_DATA(_name, _shift, _div_bitmap) \ +static struct clk_priv _name##_data = { \ + .shift = _shift, \ + .div_bitmap = _div_bitmap, \ + \ + .freq_table[0] = { \ + .index = 0, \ + .frequency = CPUFREQ_TABLE_END, \ + }, \ } -static struct clk_ops sh7785_bus_clk_ops = { - .recalc = bus_clk_recalc, -}; +FRQMR_CLK_DATA(pfc, 0, 0x0f80); +FRQMR_CLK_DATA(s3fc, 4, 0x0ff0); +FRQMR_CLK_DATA(s2fc, 8, 0x0030); +FRQMR_CLK_DATA(mfc, 12, 0x000c); +FRQMR_CLK_DATA(bfc, 16, 0x0fe0); +FRQMR_CLK_DATA(sfc, 20, 0x000c); +FRQMR_CLK_DATA(ufc, 24, 0x000c); +FRQMR_CLK_DATA(ifc, 28, 0x000e); -static void cpu_clk_recalc(struct clk *clk) +static unsigned long frqmr_recalc(struct clk *clk) { - int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + struct clk_priv *data = clk->priv; + unsigned int idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f; + + clk_rate_table_build(clk, data->freq_table, ARRAY_SIZE(div2), + &cpg_div, &data->div_bitmap); + + return data->freq_table[idx].frequency; } -static struct clk_ops sh7785_cpu_clk_ops = { - .recalc = cpu_clk_recalc, -}; +static long frqmr_round_rate(struct clk *clk, unsigned long rate) +{ + struct clk_priv *data = clk->priv; + + return clk_rate_table_round(clk, data->freq_table, rate); +} -static struct clk_ops *sh7785_clk_ops[] = { - &sh7785_master_clk_ops, - &sh7785_module_clk_ops, - &sh7785_bus_clk_ops, - &sh7785_cpu_clk_ops, +static struct clk_ops frqmr_clk_ops = { + .recalc = frqmr_recalc, + .round_rate = frqmr_round_rate, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +static unsigned long pll_recalc(struct clk *clk) { - if (idx < ARRAY_SIZE(sh7785_clk_ops)) - *ops = sh7785_clk_ops[idx]; + /* + * XXX: PLL1 multiplier is locked for the default clock mode, + * when mode pin detection and configuration support is added, + * select the multiplier dynamically. + */ + return clk->parent->rate * 36; } -static void shyway_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); - clk->rate = clk->parent->rate / sfc_divisors[idx]; -} +static struct clk_ops pll_clk_ops = { + .recalc = pll_recalc, +}; -static struct clk_ops sh7785_shyway_clk_ops = { - .recalc = shyway_clk_recalc, +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .name = "extal", + .id = -1, + .rate = 33333333, }; -static struct clk sh7785_shyway_clk = { - .name = "shyway_clk", - .flags = CLK_ALWAYS_ENABLED, - .ops = &sh7785_shyway_clk_ops, +static struct clk pll_clk = { + .name = "pll_clk", + .id = -1, + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, }; -static void ddr_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); - clk->rate = clk->parent->rate / mfc_divisors[idx]; -} +static struct clk cpu_clk = { + .name = "cpu_clk", /* Ick */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, + .priv = &ifc_data, +}; -static struct clk_ops sh7785_ddr_clk_ops = { - .recalc = ddr_clk_recalc, +static struct clk shyway_clk = { + .name = "shyway_clk", /* SHck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, + .priv = &sfc_data, }; -static struct clk sh7785_ddr_clk = { - .name = "ddr_clk", - .flags = CLK_ALWAYS_ENABLED, - .ops = &sh7785_ddr_clk_ops, +static struct clk peripheral_clk = { + .name = "peripheral_clk", /* Pck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, + .priv = &pfc_data, }; -static void ram_clk_recalc(struct clk *clk) -{ - int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003); - clk->rate = clk->parent->rate / ufc_divisors[idx]; -} +static struct clk ddr_clk = { + .name = "ddr_clk", /* DDRck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, + .priv = &mfc_data, +}; -static struct clk_ops sh7785_ram_clk_ops = { - .recalc = ram_clk_recalc, +static struct clk bus_clk = { + .name = "bus_clk", /* Bck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, + .priv = &bfc_data, }; -static struct clk sh7785_ram_clk = { - .name = "ram_clk", - .flags = CLK_ALWAYS_ENABLED, - .ops = &sh7785_ram_clk_ops, +static struct clk ga_clk = { + .name = "ga_clk", /* GAck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .priv = &s2fc_data, }; -/* - * Additional SH7785-specific on-chip clocks that aren't already part of the - * clock framework - */ -static struct clk *sh7785_onchip_clocks[] = { - &sh7785_shyway_clk, - &sh7785_ddr_clk, - &sh7785_ram_clk, +static struct clk du_clk = { + .name = "du_clk", /* DUck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .priv = &s3fc_data, +}; + +static struct clk umem_clk = { + .name = "umem_clk", /* uck */ + .id = -1, + .ops = &frqmr_clk_ops, + .parent = &pll_clk, + .flags = CLK_ENABLE_ON_INIT, + .priv = &ufc_data, }; -static int __init sh7785_clk_init(void) +static struct clk *clks[] = { + &extal_clk, + &pll_clk, + &cpu_clk, + ­way_clk, + &peripheral_clk, + &ddr_clk, + &bus_clk, + &ga_clk, + &du_clk, + &umem_clk, +}; + +static int mstpcr_clk_enable(struct clk *clk) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; + __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit), + clk->enable_reg); + return 0; +} - for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) { - struct clk *clkp = sh7785_onchip_clocks[i]; +static void mstpcr_clk_disable(struct clk *clk) +{ + __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit), + clk->enable_reg); +} - clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); - } +static struct clk_ops mstpcr_clk_ops = { + .enable = mstpcr_clk_enable, + .disable = mstpcr_clk_disable, + .recalc = followparent_recalc, +}; - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); +#define MSTPCR0 0xffc80030 +#define MSTPCR1 0xffc80034 - clk_put(clk); +#define CLK(_name, _id, _parent, _enable_reg, \ + _enable_bit, _flags) \ +{ \ + .name = _name, \ + .id = _id, \ + .parent = _parent, \ + .enable_reg = (void __iomem *)_enable_reg, \ + .enable_bit = _enable_bit, \ + .flags = _flags, \ + .ops = &mstpcr_clk_ops, \ +} - return 0; +static struct clk mstpcr_clks[] = { + /* MSTPCR0 */ + CLK("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0), + CLK("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0), + CLK("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0), + CLK("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0), + CLK("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0), + CLK("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0), + CLK("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0), + CLK("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0), + CLK("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0), + CLK("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0), + CLK("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0), + CLK("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0), + CLK("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0), + CLK("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0), + CLK("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0), + CLK("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0), + + /* MSTPCR1 */ + CLK("hudi_fck", -1, NULL, MSTPCR1, 19, 0), + CLK("ubc_fck", -1, NULL, MSTPCR1, 17, 0), + CLK("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), + CLK("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), + CLK("gdta_fck", -1, NULL, MSTPCR1, 0, 0), +}; + +int __init arch_clk_init(void) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(mstpcr_clks); i++) + ret |= clk_register(&mstpcr_clks[i]); + + return ret; } -arch_initcall(sh7785_clk_init); diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c index f84a9c134471..a0e8869071ac 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c @@ -36,30 +36,30 @@ static struct clk_ops sh7786_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inl(FRQMR1) & 0x000f); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7786_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); - clk->rate = clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate / bfc_divisors[idx]; } static struct clk_ops sh7786_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7786_cpu_clk_ops = { @@ -79,10 +79,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) *ops = sh7786_clk_ops[idx]; } -static void shyway_clk_recalc(struct clk *clk) +static unsigned long shyway_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); - clk->rate = clk->parent->rate / sfc_divisors[idx]; + return clk->parent->rate / sfc_divisors[idx]; } static struct clk_ops sh7786_shyway_clk_ops = { @@ -91,14 +91,14 @@ static struct clk_ops sh7786_shyway_clk_ops = { static struct clk sh7786_shyway_clk = { .name = "shyway_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh7786_shyway_clk_ops, }; -static void ddr_clk_recalc(struct clk *clk) +static unsigned long ddr_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); - clk->rate = clk->parent->rate / mfc_divisors[idx]; + return clk->parent->rate / mfc_divisors[idx]; } static struct clk_ops sh7786_ddr_clk_ops = { @@ -107,7 +107,7 @@ static struct clk_ops sh7786_ddr_clk_ops = { static struct clk sh7786_ddr_clk = { .name = "ddr_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &sh7786_ddr_clk_ops, }; @@ -120,29 +120,22 @@ static struct clk *sh7786_onchip_clocks[] = { &sh7786_ddr_clk, }; -static int __init sh7786_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; + struct clk *clk; + int i, ret = 0; + cpg_clk_init(); + + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) { struct clk *clkp = sh7786_onchip_clocks[i]; clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); + ret |= clk_register(clkp); } - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); - clk_put(clk); - return 0; + return ret; } -arch_initcall(sh7786_clk_init); diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c index c630b29e06a8..23c27d32d982 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c @@ -40,30 +40,30 @@ static struct clk_ops shx3_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); - clk->rate = clk->parent->rate / pfc_divisors[idx]; + return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops shx3_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); - clk->rate = clk->parent->rate / bfc_divisors[idx]; + return clk->parent->rate / bfc_divisors[idx]; } static struct clk_ops shx3_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); - clk->rate = clk->parent->rate / ifc_divisors[idx]; + return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops shx3_cpu_clk_ops = { @@ -83,10 +83,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) *ops = shx3_clk_ops[idx]; } -static void shyway_clk_recalc(struct clk *clk) +static unsigned long shyway_clk_recalc(struct clk *clk) { int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); - clk->rate = clk->parent->rate / cfc_divisors[idx]; + return clk->parent->rate / cfc_divisors[idx]; } static struct clk_ops shx3_shyway_clk_ops = { @@ -95,7 +95,7 @@ static struct clk_ops shx3_shyway_clk_ops = { static struct clk shx3_shyway_clk = { .name = "shyway_clk", - .flags = CLK_ALWAYS_ENABLED, + .flags = CLK_ENABLE_ON_INIT, .ops = &shx3_shyway_clk_ops, }; @@ -107,29 +107,22 @@ static struct clk *shx3_onchip_clocks[] = { &shx3_shyway_clk, }; -static int __init shx3_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; + struct clk *clk; + int i, ret = 0; + cpg_clk_init(); + + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { struct clk *clkp = shx3_onchip_clocks[i]; clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); + ret |= clk_register(clkp); } - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); - clk_put(clk); - return 0; + return ret; } -arch_initcall(shx3_clk_init); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 51204dc7ca21..6307e087c864 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -318,12 +318,6 @@ static struct platform_device *sh7343_devices[] __initdata = { static int __init sh7343_devices_setup(void) { - clk_always_enable("uram0"); /* URAM */ - clk_always_enable("xymem0"); /* XYMEM */ - clk_always_enable("veu0"); /* VEU */ - clk_always_enable("vpu0"); /* VPU */ - clk_always_enable("jpu0"); /* JPU */ - platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); platform_resource_setup_memory(&veu_device, "veu", 2 << 20); platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 04de0fa85120..318516f6bfad 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -307,12 +307,6 @@ static struct platform_device *sh7366_devices[] __initdata = { static int __init sh7366_devices_setup(void) { - clk_always_enable("rsmem0"); /* RSMEM */ - clk_always_enable("xymem0"); /* XYMEM */ - clk_always_enable("veu1"); /* VEU-2 */ - clk_always_enable("veu0"); /* VEU-1 */ - clk_always_enable("vpu0"); /* VPU */ - platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 5d6247fecd63..ea524a2da3e4 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -352,12 +352,6 @@ static struct platform_device *sh7722_devices[] __initdata = { static int __init sh7722_devices_setup(void) { - clk_always_enable("uram0"); /* URAM */ - clk_always_enable("xymem0"); /* XYMEM */ - clk_always_enable("veu0"); /* VEU */ - clk_always_enable("vpu0"); /* VPU */ - clk_always_enable("jpu0"); /* JPU */ - platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); platform_resource_setup_memory(&veu_device, "veu", 2 << 20); platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 1429fc5e4286..04cb4aae7ea7 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -460,11 +460,6 @@ static struct platform_device *sh7723_devices[] __initdata = { static int __init sh7723_devices_setup(void) { - clk_always_enable("meram0"); /* MERAM */ - clk_always_enable("veu1"); /* VEU2H1 */ - clk_always_enable("veu0"); /* VEU2H0 */ - clk_always_enable("vpu0"); /* VPU */ - platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 852f8104f03a..191f0e2a7e08 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -470,10 +470,6 @@ static struct platform_device *sh7724_devices[] __initdata = { static int __init sh7724_devices_setup(void) { - clk_always_enable("vpu0"); /* VPU */ - clk_always_enable("veu1"); /* VEU3F1 */ - clk_always_enable("veu0"); /* VEU3F0 */ - platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index c91f34c9aa83..f1e0c0d36da7 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -118,7 +118,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -149,7 +149,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -180,7 +180,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { @@ -210,7 +210,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu3_resources[] = { @@ -240,7 +240,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu4_resources[] = { @@ -270,7 +270,7 @@ static struct sh_timer_config tmu5_platform_data = { .name = "TMU5", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu5_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 0feba41d218d..1e86209db284 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c @@ -82,7 +82,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -113,7 +113,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -144,7 +144,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { @@ -174,7 +174,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu3_resources[] = { @@ -204,7 +204,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu4_resources[] = { @@ -234,7 +234,7 @@ static struct sh_timer_config tmu5_platform_data = { .name = "TMU5", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu5_resources[] = { @@ -264,7 +264,7 @@ static struct sh_timer_config tmu6_platform_data = { .name = "TMU6", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu6_resources[] = { @@ -294,7 +294,7 @@ static struct sh_timer_config tmu7_platform_data = { .name = "TMU7", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu7_resources[] = { @@ -324,7 +324,7 @@ static struct sh_timer_config tmu8_platform_data = { .name = "TMU8", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu8_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index f1df02095062..715e05b431e5 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -18,7 +18,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -49,7 +49,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -80,7 +80,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { @@ -110,7 +110,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu3_resources[] = { @@ -140,7 +140,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu4_resources[] = { @@ -170,7 +170,7 @@ static struct sh_timer_config tmu5_platform_data = { .name = "TMU5", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu5_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index dc5d3e507a21..af561402570b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -20,7 +20,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "tmu012_fck", .clockevent_rating = 200, }; @@ -51,7 +51,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "tmu012_fck", .clocksource_rating = 200, }; @@ -82,7 +82,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "tmu012_fck", }; static struct resource tmu2_resources[] = { @@ -112,7 +112,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "tmu345_fck", }; static struct resource tmu3_resources[] = { @@ -142,7 +142,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "tmu345_fck", }; static struct resource tmu4_resources[] = { @@ -172,7 +172,7 @@ static struct sh_timer_config tmu5_platform_data = { .name = "TMU5", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "tmu345_fck", }; static struct resource tmu5_resources[] = { @@ -204,31 +204,37 @@ static struct plat_sci_port sci_platform_data[] = { .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .irqs = { 40, 40, 40, 40 }, + .clk = "scif_fck", }, { .mapbase = 0xffeb0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .irqs = { 44, 44, 44, 44 }, + .clk = "scif_fck", }, { .mapbase = 0xffec0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .irqs = { 60, 60, 60, 60 }, + .clk = "scif_fck", }, { .mapbase = 0xffed0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .irqs = { 61, 61, 61, 61 }, + .clk = "scif_fck", }, { .mapbase = 0xffee0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .irqs = { 62, 62, 62, 62 }, + .clk = "scif_fck", }, { .mapbase = 0xffef0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, .irqs = { 63, 63, 63, 63 }, + .clk = "scif_fck", }, { .flags = 0, } diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 2c464bf5a899..93e0d2c017e8 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -75,7 +75,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -106,7 +106,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -137,7 +137,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { @@ -167,7 +167,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu3_resources[] = { @@ -197,7 +197,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu4_resources[] = { @@ -227,7 +227,7 @@ static struct sh_timer_config tmu5_platform_data = { .name = "TMU5", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu5_resources[] = { @@ -257,7 +257,7 @@ static struct sh_timer_config tmu6_platform_data = { .name = "TMU6", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu6_resources[] = { @@ -287,7 +287,7 @@ static struct sh_timer_config tmu7_platform_data = { .name = "TMU7", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu7_resources[] = { @@ -317,7 +317,7 @@ static struct sh_timer_config tmu8_platform_data = { .name = "TMU8", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu8_resources[] = { @@ -347,7 +347,7 @@ static struct sh_timer_config tmu9_platform_data = { .name = "TMU9", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu9_resources[] = { @@ -377,7 +377,7 @@ static struct sh_timer_config tmu10_platform_data = { .name = "TMU10", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu10_resources[] = { @@ -407,7 +407,7 @@ static struct sh_timer_config tmu11_platform_data = { .name = "TMU11", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu11_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 9d5185b42f13..53c65fd9ccef 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -53,7 +53,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -84,7 +84,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -115,7 +115,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { @@ -145,7 +145,7 @@ static struct sh_timer_config tmu3_platform_data = { .name = "TMU3", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu3_resources[] = { @@ -175,7 +175,7 @@ static struct sh_timer_config tmu4_platform_data = { .name = "TMU4", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu4_resources[] = { @@ -205,7 +205,7 @@ static struct sh_timer_config tmu5_platform_data = { .name = "TMU5", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu5_resources[] = { diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c index 5486324880e1..7f864ebc51d3 100644 --- a/arch/sh/kernel/cpu/sh5/clock-sh5.c +++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c @@ -32,30 +32,30 @@ static struct clk_ops sh5_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc(struct clk *clk) +static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; - clk->rate = clk->parent->rate / ifc_table[idx]; + return clk->parent->rate / ifc_table[idx]; } static struct clk_ops sh5_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc(struct clk *clk) +static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; - clk->rate = clk->parent->rate / ifc_table[idx]; + return clk->parent->rate / ifc_table[idx]; } static struct clk_ops sh5_bus_clk_ops = { .recalc = bus_clk_recalc, }; -static void cpu_clk_recalc(struct clk *clk) +static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(cprc_base) & 0x0007); - clk->rate = clk->parent->rate / ifc_table[idx]; + return clk->parent->rate / ifc_table[idx]; } static struct clk_ops sh5_cpu_clk_ops = { diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c index 678d69bdebba..f5ff1ac57fc2 100644 --- a/arch/sh/kernel/cpu/sh5/setup-sh5.c +++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c @@ -75,7 +75,7 @@ static struct sh_timer_config tmu0_platform_data = { .name = "TMU0", .channel_offset = 0x04, .timer_bit = 0, - .clk = "module_clk", + .clk = "peripheral_clk", .clockevent_rating = 200, }; @@ -106,7 +106,7 @@ static struct sh_timer_config tmu1_platform_data = { .name = "TMU1", .channel_offset = 0x10, .timer_bit = 1, - .clk = "module_clk", + .clk = "peripheral_clk", .clocksource_rating = 200, }; @@ -137,7 +137,7 @@ static struct sh_timer_config tmu2_platform_data = { .name = "TMU2", .channel_offset = 0x1c, .timer_bit = 2, - .clk = "module_clk", + .clk = "peripheral_clk", }; static struct resource tmu2_resources[] = { |