diff options
| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2015-09-10 07:03:25 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-09-14 19:47:31 +0100 |
| commit | 5c6901d98b35c3192336e419344f0f22f86b8845 (patch) | |
| tree | 231f83d3affa3634afcee574dab1fa8517d13dcc /sound/soc | |
| parent | f1df12290722f998f5eb173ae30434d313aea54c (diff) | |
ASoC: rsnd: ADG initial setup on rsnd_adg_ssi_clk_init()
ADG is special IP since it doesn't have MSTP. And now, ADG has common
mod base register access. We can now setup ADG initial setting when
probe timing. It is needed if sound card is based on AUIDO_CLK which
is used as Master clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc')
| -rw-r--r-- | sound/soc/sh/rcar/adg.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c index 48bb38d38499..276703ba3e1f 100644 --- a/sound/soc/sh/rcar/adg.c +++ b/sound/soc/sh/rcar/adg.c @@ -25,7 +25,6 @@ struct rsnd_adg { int rbga_rate_for_441khz_div_6; /* RBGA */ int rbgb_rate_for_48khz_div_6; /* RBGB */ - u32 ckr; }; #define for_each_rsnd_clk(pos, adg, i) \ @@ -323,7 +322,6 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate) { struct rsnd_priv *priv = rsnd_mod_to_priv(mod); struct rsnd_adg *adg = rsnd_priv_to_adg(priv); - struct rsnd_mod *adg_mod = rsnd_mod_get(adg); struct device *dev = rsnd_priv_to_dev(priv); struct clk *clk; int i; @@ -366,11 +364,6 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate) found_clock: - /* see rsnd_adg_ssi_clk_init() */ - rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, adg->ckr); - rsnd_mod_write(adg_mod, BRRA, 0x00000002); /* 1/6 */ - rsnd_mod_write(adg_mod, BRRB, 0x00000002); /* 1/6 */ - /* * This "mod" = "ssi" here. * we can get "ssi id" from mod @@ -386,6 +379,7 @@ found_clock: static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg) { struct clk *clk; + struct rsnd_mod *adg_mod = rsnd_mod_get(adg); unsigned long rate; u32 ckr; int i; @@ -405,6 +399,7 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg) * and, BRGB outputs 48.0kHz base parent clock 1/32 here. * see * rsnd_adg_ssi_clk_try_start() + * rsnd_ssi_master_clk_start() */ ckr = 0; adg->rbga_rate_for_441khz_div_6 = 0; @@ -428,7 +423,9 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg) } } - adg->ckr = ckr; + rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr); + rsnd_mod_write(adg_mod, BRRA, 0x00000002); /* 1/6 */ + rsnd_mod_write(adg_mod, BRRB, 0x00000002); /* 1/6 */ } int rsnd_adg_probe(struct platform_device *pdev, |