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author | Mengdong Lin <mengdong.lin@intel.com> | 2014-07-03 17:02:23 +0800 |
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committer | Takashi Iwai <tiwai@suse.de> | 2014-07-04 07:47:22 +0200 |
commit | e4d9e513dedb5ac4e166c1053314fa935ddecc8c (patch) | |
tree | 7c5159dd08ef78189302ef7669ddd532b6dd09cc /sound/pci/hda/hda_intel_trace.h | |
parent | c149dcb5c60bfea8871f16dfcc0690255eeb825f (diff) |
ALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA controllersound-3.16-rc4
For HSW/BDW display HD-A controller, hda_set_bclk() is defined to set BCLK
by programming the M/N values as per the core display clock (CDCLK) queried from
i915 display driver.
And the audio driver will also set BCLK in azx_first_init() since the display
driver can turn off the shared power in boot phase if only eDP is connected
and M/N values will be lost and must be reprogrammed.
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/hda/hda_intel_trace.h')
0 files changed, 0 insertions, 0 deletions